root/arch/mips/include/asm/cpu.h

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   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * cpu.h: Values of the PRId register used to match up
   4  *        various MIPS cpu types.
   5  *
   6  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   7  * Copyright (C) 2004, 2013  Maciej W. Rozycki
   8  */
   9 #ifndef _ASM_CPU_H
  10 #define _ASM_CPU_H
  11 
  12 #include <linux/bits.h>
  13 
  14 /*
  15    As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
  16    register 15, select 0) is defined in this (backwards compatible) way:
  17 
  18   +----------------+----------------+----------------+----------------+
  19   | Company Options| Company ID     | Processor ID   | Revision       |
  20   +----------------+----------------+----------------+----------------+
  21    31            24 23            16 15             8 7
  22 
  23    I don't have docs for all the previous processors, but my impression is
  24    that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
  25    spec.
  26 */
  27 
  28 #define PRID_OPT_MASK           0xff000000
  29 
  30 /*
  31  * Assigned Company values for bits 23:16 of the PRId register.
  32  */
  33 
  34 #define PRID_COMP_MASK          0xff0000
  35 
  36 #define PRID_COMP_LEGACY        0x000000
  37 #define PRID_COMP_MIPS          0x010000
  38 #define PRID_COMP_BROADCOM      0x020000
  39 #define PRID_COMP_ALCHEMY       0x030000
  40 #define PRID_COMP_SIBYTE        0x040000
  41 #define PRID_COMP_SANDCRAFT     0x050000
  42 #define PRID_COMP_NXP           0x060000
  43 #define PRID_COMP_TOSHIBA       0x070000
  44 #define PRID_COMP_LSI           0x080000
  45 #define PRID_COMP_LEXRA         0x0b0000
  46 #define PRID_COMP_NETLOGIC      0x0c0000
  47 #define PRID_COMP_CAVIUM        0x0d0000
  48 #define PRID_COMP_LOONGSON      0x140000
  49 #define PRID_COMP_INGENIC_D0    0xd00000        /* JZ4740, JZ4750 */
  50 #define PRID_COMP_INGENIC_D1    0xd10000        /* JZ4770, JZ4775, X1000 */
  51 #define PRID_COMP_INGENIC_E1    0xe10000        /* JZ4780 */
  52 
  53 /*
  54  * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
  55  * register.  In order to detect a certain CPU type exactly eventually
  56  * additional registers may need to be examined.
  57  */
  58 
  59 #define PRID_IMP_MASK           0xff00
  60 
  61 /*
  62  * These are valid when 23:16 == PRID_COMP_LEGACY
  63  */
  64 
  65 #define PRID_IMP_R2000          0x0100
  66 #define PRID_IMP_AU1_REV1       0x0100
  67 #define PRID_IMP_AU1_REV2       0x0200
  68 #define PRID_IMP_R3000          0x0200          /* Same as R2000A  */
  69 #define PRID_IMP_R6000          0x0300          /* Same as R3000A  */
  70 #define PRID_IMP_R4000          0x0400
  71 #define PRID_IMP_R6000A         0x0600
  72 #define PRID_IMP_R10000         0x0900
  73 #define PRID_IMP_R4300          0x0b00
  74 #define PRID_IMP_VR41XX         0x0c00
  75 #define PRID_IMP_R12000         0x0e00
  76 #define PRID_IMP_R14000         0x0f00          /* R14K && R16K */
  77 #define PRID_IMP_R8000          0x1000
  78 #define PRID_IMP_PR4450         0x1200
  79 #define PRID_IMP_R4600          0x2000
  80 #define PRID_IMP_R4700          0x2100
  81 #define PRID_IMP_TX39           0x2200
  82 #define PRID_IMP_R4640          0x2200
  83 #define PRID_IMP_R4650          0x2200          /* Same as R4640 */
  84 #define PRID_IMP_R5000          0x2300
  85 #define PRID_IMP_TX49           0x2d00
  86 #define PRID_IMP_SONIC          0x2400
  87 #define PRID_IMP_MAGIC          0x2500
  88 #define PRID_IMP_RM7000         0x2700
  89 #define PRID_IMP_NEVADA         0x2800          /* RM5260 ??? */
  90 #define PRID_IMP_RM9000         0x3400
  91 #define PRID_IMP_LOONGSON_32    0x4200  /* Loongson-1 */
  92 #define PRID_IMP_R5432          0x5400
  93 #define PRID_IMP_R5500          0x5500
  94 #define PRID_IMP_LOONGSON_64    0x6300  /* Loongson-2/3 */
  95 
  96 #define PRID_IMP_UNKNOWN        0xff00
  97 
  98 /*
  99  * These are the PRID's for when 23:16 == PRID_COMP_MIPS
 100  */
 101 
 102 #define PRID_IMP_QEMU_GENERIC   0x0000
 103 #define PRID_IMP_4KC            0x8000
 104 #define PRID_IMP_5KC            0x8100
 105 #define PRID_IMP_20KC           0x8200
 106 #define PRID_IMP_4KEC           0x8400
 107 #define PRID_IMP_4KSC           0x8600
 108 #define PRID_IMP_25KF           0x8800
 109 #define PRID_IMP_5KE            0x8900
 110 #define PRID_IMP_4KECR2         0x9000
 111 #define PRID_IMP_4KEMPR2        0x9100
 112 #define PRID_IMP_4KSD           0x9200
 113 #define PRID_IMP_24K            0x9300
 114 #define PRID_IMP_34K            0x9500
 115 #define PRID_IMP_24KE           0x9600
 116 #define PRID_IMP_74K            0x9700
 117 #define PRID_IMP_1004K          0x9900
 118 #define PRID_IMP_1074K          0x9a00
 119 #define PRID_IMP_M14KC          0x9c00
 120 #define PRID_IMP_M14KEC         0x9e00
 121 #define PRID_IMP_INTERAPTIV_UP  0xa000
 122 #define PRID_IMP_INTERAPTIV_MP  0xa100
 123 #define PRID_IMP_PROAPTIV_UP    0xa200
 124 #define PRID_IMP_PROAPTIV_MP    0xa300
 125 #define PRID_IMP_P6600          0xa400
 126 #define PRID_IMP_M5150          0xa700
 127 #define PRID_IMP_P5600          0xa800
 128 #define PRID_IMP_I6400          0xa900
 129 #define PRID_IMP_M6250          0xab00
 130 #define PRID_IMP_I6500          0xb000
 131 
 132 /*
 133  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
 134  */
 135 
 136 #define PRID_IMP_SB1            0x0100
 137 #define PRID_IMP_SB1A           0x1100
 138 
 139 /*
 140  * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
 141  */
 142 
 143 #define PRID_IMP_SR71000        0x0400
 144 
 145 /*
 146  * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
 147  */
 148 
 149 #define PRID_IMP_BMIPS32_REV4   0x4000
 150 #define PRID_IMP_BMIPS32_REV8   0x8000
 151 #define PRID_IMP_BMIPS3300      0x9000
 152 #define PRID_IMP_BMIPS3300_ALT  0x9100
 153 #define PRID_IMP_BMIPS3300_BUG  0x0000
 154 #define PRID_IMP_BMIPS43XX      0xa000
 155 #define PRID_IMP_BMIPS5000      0x5a00
 156 #define PRID_IMP_BMIPS5200      0x5b00
 157 
 158 #define PRID_REV_BMIPS4380_LO   0x0040
 159 #define PRID_REV_BMIPS4380_HI   0x006f
 160 
 161 /*
 162  * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
 163  */
 164 
 165 #define PRID_IMP_CAVIUM_CN38XX 0x0000
 166 #define PRID_IMP_CAVIUM_CN31XX 0x0100
 167 #define PRID_IMP_CAVIUM_CN30XX 0x0200
 168 #define PRID_IMP_CAVIUM_CN58XX 0x0300
 169 #define PRID_IMP_CAVIUM_CN56XX 0x0400
 170 #define PRID_IMP_CAVIUM_CN50XX 0x0600
 171 #define PRID_IMP_CAVIUM_CN52XX 0x0700
 172 #define PRID_IMP_CAVIUM_CN63XX 0x9000
 173 #define PRID_IMP_CAVIUM_CN68XX 0x9100
 174 #define PRID_IMP_CAVIUM_CN66XX 0x9200
 175 #define PRID_IMP_CAVIUM_CN61XX 0x9300
 176 #define PRID_IMP_CAVIUM_CNF71XX 0x9400
 177 #define PRID_IMP_CAVIUM_CN78XX 0x9500
 178 #define PRID_IMP_CAVIUM_CN70XX 0x9600
 179 #define PRID_IMP_CAVIUM_CN73XX 0x9700
 180 #define PRID_IMP_CAVIUM_CNF75XX 0x9800
 181 
 182 /*
 183  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
 184  */
 185 
 186 #define PRID_IMP_XBURST        0x0200
 187 
 188 /*
 189  * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
 190  */
 191 #define PRID_IMP_NETLOGIC_XLR732        0x0000
 192 #define PRID_IMP_NETLOGIC_XLR716        0x0200
 193 #define PRID_IMP_NETLOGIC_XLR532        0x0900
 194 #define PRID_IMP_NETLOGIC_XLR308        0x0600
 195 #define PRID_IMP_NETLOGIC_XLR532C       0x0800
 196 #define PRID_IMP_NETLOGIC_XLR516C       0x0a00
 197 #define PRID_IMP_NETLOGIC_XLR508C       0x0b00
 198 #define PRID_IMP_NETLOGIC_XLR308C       0x0f00
 199 #define PRID_IMP_NETLOGIC_XLS608        0x8000
 200 #define PRID_IMP_NETLOGIC_XLS408        0x8800
 201 #define PRID_IMP_NETLOGIC_XLS404        0x8c00
 202 #define PRID_IMP_NETLOGIC_XLS208        0x8e00
 203 #define PRID_IMP_NETLOGIC_XLS204        0x8f00
 204 #define PRID_IMP_NETLOGIC_XLS108        0xce00
 205 #define PRID_IMP_NETLOGIC_XLS104        0xcf00
 206 #define PRID_IMP_NETLOGIC_XLS616B       0x4000
 207 #define PRID_IMP_NETLOGIC_XLS608B       0x4a00
 208 #define PRID_IMP_NETLOGIC_XLS416B       0x4400
 209 #define PRID_IMP_NETLOGIC_XLS412B       0x4c00
 210 #define PRID_IMP_NETLOGIC_XLS408B       0x4e00
 211 #define PRID_IMP_NETLOGIC_XLS404B       0x4f00
 212 #define PRID_IMP_NETLOGIC_AU13XX        0x8000
 213 
 214 #define PRID_IMP_NETLOGIC_XLP8XX        0x1000
 215 #define PRID_IMP_NETLOGIC_XLP3XX        0x1100
 216 #define PRID_IMP_NETLOGIC_XLP2XX        0x1200
 217 #define PRID_IMP_NETLOGIC_XLP9XX        0x1500
 218 #define PRID_IMP_NETLOGIC_XLP5XX        0x1300
 219 
 220 /*
 221  * Particular Revision values for bits 7:0 of the PRId register.
 222  */
 223 
 224 #define PRID_REV_MASK           0x00ff
 225 
 226 /*
 227  * Definitions for 7:0 on legacy processors
 228  */
 229 
 230 #define PRID_REV_TX4927                 0x0022
 231 #define PRID_REV_TX4937                 0x0030
 232 #define PRID_REV_R4400                  0x0040
 233 #define PRID_REV_R3000A                 0x0030
 234 #define PRID_REV_R3000                  0x0020
 235 #define PRID_REV_R2000A                 0x0010
 236 #define PRID_REV_TX3912                 0x0010
 237 #define PRID_REV_TX3922                 0x0030
 238 #define PRID_REV_TX3927                 0x0040
 239 #define PRID_REV_VR4111                 0x0050
 240 #define PRID_REV_VR4181                 0x0050  /* Same as VR4111 */
 241 #define PRID_REV_VR4121                 0x0060
 242 #define PRID_REV_VR4122                 0x0070
 243 #define PRID_REV_VR4181A                0x0070  /* Same as VR4122 */
 244 #define PRID_REV_VR4130                 0x0080
 245 #define PRID_REV_34K_V1_0_2             0x0022
 246 #define PRID_REV_LOONGSON1B             0x0020
 247 #define PRID_REV_LOONGSON1C             0x0020  /* Same as Loongson-1B */
 248 #define PRID_REV_LOONGSON2E             0x0002
 249 #define PRID_REV_LOONGSON2F             0x0003
 250 #define PRID_REV_LOONGSON3A_R1          0x0005
 251 #define PRID_REV_LOONGSON3B_R1          0x0006
 252 #define PRID_REV_LOONGSON3B_R2          0x0007
 253 #define PRID_REV_LOONGSON3A_R2_0        0x0008
 254 #define PRID_REV_LOONGSON3A_R3_0        0x0009
 255 #define PRID_REV_LOONGSON3A_R2_1        0x000c
 256 #define PRID_REV_LOONGSON3A_R3_1        0x000d
 257 
 258 /*
 259  * Older processors used to encode processor version and revision in two
 260  * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
 261  * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
 262  * the patch number.  *ARGH*
 263  */
 264 #define PRID_REV_ENCODE_44(ver, rev)                                    \
 265         ((ver) << 4 | (rev))
 266 #define PRID_REV_ENCODE_332(ver, rev, patch)                            \
 267         ((ver) << 5 | (rev) << 2 | (patch))
 268 
 269 /*
 270  * FPU implementation/revision register (CP1 control register 0).
 271  *
 272  * +---------------------------------+----------------+----------------+
 273  * | 0                               | Implementation | Revision       |
 274  * +---------------------------------+----------------+----------------+
 275  *  31                             16 15             8 7              0
 276  */
 277 
 278 #define FPIR_IMP_MASK           0xff00
 279 
 280 #define FPIR_IMP_NONE           0x0000
 281 
 282 #if !defined(__ASSEMBLY__)
 283 
 284 enum cpu_type_enum {
 285         CPU_UNKNOWN,
 286 
 287         /*
 288          * R2000 class processors
 289          */
 290         CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
 291         CPU_R3081, CPU_R3081E,
 292 
 293         /*
 294          * R4000 class processors
 295          */
 296         CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200,
 297         CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
 298         CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R10000,
 299         CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
 300         CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
 301         CPU_SR71000, CPU_TX49XX,
 302 
 303         /*
 304          * TX3900 class processors
 305          */
 306         CPU_TX3912, CPU_TX3922, CPU_TX3927,
 307 
 308         /*
 309          * MIPS32 class processors
 310          */
 311         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
 312         CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
 313         CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON1, CPU_M14KC,
 314         CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
 315         CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
 316 
 317         /*
 318          * MIPS64 class processors
 319          */
 320         CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
 321         CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
 322         CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500,
 323 
 324         CPU_QEMU_GENERIC,
 325 
 326         CPU_LAST
 327 };
 328 
 329 #endif /* !__ASSEMBLY */
 330 
 331 /*
 332  * ISA Level encodings
 333  *
 334  */
 335 #define MIPS_CPU_ISA_II         0x00000001
 336 #define MIPS_CPU_ISA_III        0x00000002
 337 #define MIPS_CPU_ISA_IV         0x00000004
 338 #define MIPS_CPU_ISA_V          0x00000008
 339 #define MIPS_CPU_ISA_M32R1      0x00000010
 340 #define MIPS_CPU_ISA_M32R2      0x00000020
 341 #define MIPS_CPU_ISA_M64R1      0x00000040
 342 #define MIPS_CPU_ISA_M64R2      0x00000080
 343 #define MIPS_CPU_ISA_M32R6      0x00000100
 344 #define MIPS_CPU_ISA_M64R6      0x00000200
 345 
 346 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
 347         MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6)
 348 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
 349         MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
 350         MIPS_CPU_ISA_M64R6)
 351 
 352 /*
 353  * CPU Option encodings
 354  */
 355 #define MIPS_CPU_TLB            BIT_ULL( 0)     /* CPU has TLB */
 356 #define MIPS_CPU_4KEX           BIT_ULL( 1)     /* "R4K" exception model */
 357 #define MIPS_CPU_3K_CACHE       BIT_ULL( 2)     /* R3000-style caches */
 358 #define MIPS_CPU_4K_CACHE       BIT_ULL( 3)     /* R4000-style caches */
 359 #define MIPS_CPU_TX39_CACHE     BIT_ULL( 4)     /* TX3900-style caches */
 360 #define MIPS_CPU_FPU            BIT_ULL( 5)     /* CPU has FPU */
 361 #define MIPS_CPU_32FPR          BIT_ULL( 6)     /* 32 dbl. prec. FP registers */
 362 #define MIPS_CPU_COUNTER        BIT_ULL( 7)     /* Cycle count/compare */
 363 #define MIPS_CPU_WATCH          BIT_ULL( 8)     /* watchpoint registers */
 364 #define MIPS_CPU_DIVEC          BIT_ULL( 9)     /* dedicated interrupt vector */
 365 #define MIPS_CPU_VCE            BIT_ULL(10)     /* virt. coherence conflict possible */
 366 #define MIPS_CPU_CACHE_CDEX_P   BIT_ULL(11)     /* Create_Dirty_Exclusive CACHE op */
 367 #define MIPS_CPU_CACHE_CDEX_S   BIT_ULL(12)     /* ... same for seconary cache ... */
 368 #define MIPS_CPU_MCHECK         BIT_ULL(13)     /* Machine check exception */
 369 #define MIPS_CPU_EJTAG          BIT_ULL(14)     /* EJTAG exception */
 370 #define MIPS_CPU_NOFPUEX        BIT_ULL(15)     /* no FPU exception */
 371 #define MIPS_CPU_LLSC           BIT_ULL(16)     /* CPU has ll/sc instructions */
 372 #define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17)   /* P-cache subset enforced */
 373 #define MIPS_CPU_PREFETCH       BIT_ULL(18)     /* CPU has usable prefetch */
 374 #define MIPS_CPU_VINT           BIT_ULL(19)     /* CPU supports MIPSR2 vectored interrupts */
 375 #define MIPS_CPU_VEIC           BIT_ULL(20)     /* CPU supports MIPSR2 external interrupt controller mode */
 376 #define MIPS_CPU_ULRI           BIT_ULL(21)     /* CPU has ULRI feature */
 377 #define MIPS_CPU_PCI            BIT_ULL(22)     /* CPU has Perf Ctr Int indicator */
 378 #define MIPS_CPU_RIXI           BIT_ULL(23)     /* CPU has TLB Read/eXec Inhibit */
 379 #define MIPS_CPU_MICROMIPS      BIT_ULL(24)     /* CPU has microMIPS capability */
 380 #define MIPS_CPU_TLBINV         BIT_ULL(25)     /* CPU supports TLBINV/F */
 381 #define MIPS_CPU_SEGMENTS       BIT_ULL(26)     /* CPU supports Segmentation Control registers */
 382 #define MIPS_CPU_EVA            BIT_ULL(27)     /* CPU supports Enhanced Virtual Addressing */
 383 #define MIPS_CPU_HTW            BIT_ULL(28)     /* CPU support Hardware Page Table Walker */
 384 #define MIPS_CPU_RIXIEX         BIT_ULL(29)     /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
 385 #define MIPS_CPU_MAAR           BIT_ULL(30)     /* MAAR(I) registers are present */
 386 #define MIPS_CPU_FRE            BIT_ULL(31)     /* FRE & UFE bits implemented */
 387 #define MIPS_CPU_RW_LLB         BIT_ULL(32)     /* LLADDR/LLB writes are allowed */
 388 #define MIPS_CPU_LPA            BIT_ULL(33)     /* CPU supports Large Physical Addressing */
 389 #define MIPS_CPU_CDMM           BIT_ULL(34)     /* CPU has Common Device Memory Map */
 390 #define MIPS_CPU_BP_GHIST       BIT_ULL(35)     /* R12K+ Branch Prediction Global History */
 391 #define MIPS_CPU_SP             BIT_ULL(36)     /* Small (1KB) page support */
 392 #define MIPS_CPU_FTLB           BIT_ULL(37)     /* CPU has Fixed-page-size TLB */
 393 #define MIPS_CPU_NAN_LEGACY     BIT_ULL(38)     /* Legacy NaN implemented */
 394 #define MIPS_CPU_NAN_2008       BIT_ULL(39)     /* 2008 NaN implemented */
 395 #define MIPS_CPU_VP             BIT_ULL(40)     /* MIPSr6 Virtual Processors (multi-threading) */
 396 #define MIPS_CPU_LDPTE          BIT_ULL(41)     /* CPU has ldpte/lddir instructions */
 397 #define MIPS_CPU_MVH            BIT_ULL(42)     /* CPU supports MFHC0/MTHC0 */
 398 #define MIPS_CPU_EBASE_WG       BIT_ULL(43)     /* CPU has EBase.WG */
 399 #define MIPS_CPU_BADINSTR       BIT_ULL(44)     /* CPU has BadInstr register */
 400 #define MIPS_CPU_BADINSTRP      BIT_ULL(45)     /* CPU has BadInstrP register */
 401 #define MIPS_CPU_CTXTC          BIT_ULL(46)     /* CPU has [X]ConfigContext registers */
 402 #define MIPS_CPU_PERF           BIT_ULL(47)     /* CPU has MIPS performance counters */
 403 #define MIPS_CPU_GUESTCTL0EXT   BIT_ULL(48)     /* CPU has VZ GuestCtl0Ext register */
 404 #define MIPS_CPU_GUESTCTL1      BIT_ULL(49)     /* CPU has VZ GuestCtl1 register */
 405 #define MIPS_CPU_GUESTCTL2      BIT_ULL(50)     /* CPU has VZ GuestCtl2 register */
 406 #define MIPS_CPU_GUESTID        BIT_ULL(51)     /* CPU uses VZ ASE GuestID feature */
 407 #define MIPS_CPU_DRG            BIT_ULL(52)     /* CPU has VZ Direct Root to Guest (DRG) */
 408 #define MIPS_CPU_UFR            BIT_ULL(53)     /* CPU supports User mode FR switching */
 409 #define MIPS_CPU_SHARED_FTLB_RAM \
 410                                 BIT_ULL(54)     /* CPU shares FTLB RAM with another */
 411 #define MIPS_CPU_SHARED_FTLB_ENTRIES \
 412                                 BIT_ULL(55)     /* CPU shares FTLB entries with another */
 413 #define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
 414                                 BIT_ULL(56)     /* CPU has perf counters implemented per TC (MIPSMT ASE) */
 415 #define MIPS_CPU_MMID           BIT_ULL(57)     /* CPU supports MemoryMapIDs */
 416 
 417 /*
 418  * CPU ASE encodings
 419  */
 420 #define MIPS_ASE_MIPS16         0x00000001 /* code compression */
 421 #define MIPS_ASE_MDMX           0x00000002 /* MIPS digital media extension */
 422 #define MIPS_ASE_MIPS3D         0x00000004 /* MIPS-3D */
 423 #define MIPS_ASE_SMARTMIPS      0x00000008 /* SmartMIPS */
 424 #define MIPS_ASE_DSP            0x00000010 /* Signal Processing ASE */
 425 #define MIPS_ASE_MIPSMT         0x00000020 /* CPU supports MIPS MT */
 426 #define MIPS_ASE_DSP2P          0x00000040 /* Signal Processing ASE Rev 2 */
 427 #define MIPS_ASE_VZ             0x00000080 /* Virtualization ASE */
 428 #define MIPS_ASE_MSA            0x00000100 /* MIPS SIMD Architecture */
 429 #define MIPS_ASE_DSP3           0x00000200 /* Signal Processing ASE Rev 3*/
 430 #define MIPS_ASE_MIPS16E2       0x00000400 /* MIPS16e2 */
 431 #define MIPS_ASE_LOONGSON_MMI   0x00000800 /* Loongson MultiMedia extensions Instructions */
 432 #define MIPS_ASE_LOONGSON_CAM   0x00001000 /* Loongson CAM */
 433 #define MIPS_ASE_LOONGSON_EXT   0x00002000 /* Loongson EXTensions */
 434 #define MIPS_ASE_LOONGSON_EXT2  0x00004000 /* Loongson EXTensions R2 */
 435 
 436 #endif /* _ASM_CPU_H */
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