1 /***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28 /*
29 *
30 * Helper functions to abstract board specific data about
31 * network ports from the rest of the cvmx-helper files.
32 */
33
34 #include <linux/bug.h>
35 #include <asm/octeon/octeon.h>
36 #include <asm/octeon/cvmx-bootinfo.h>
37
38 #include <asm/octeon/cvmx-config.h>
39
40 #include <asm/octeon/cvmx-helper.h>
41 #include <asm/octeon/cvmx-helper-util.h>
42 #include <asm/octeon/cvmx-helper-board.h>
43
44 #include <asm/octeon/cvmx-gmxx-defs.h>
45 #include <asm/octeon/cvmx-asxx-defs.h>
46
47 /**
48 * Return the MII PHY address associated with the given IPD
49 * port. A result of -1 means there isn't a MII capable PHY
50 * connected to this port. On chips supporting multiple MII
51 * busses the bus number is encoded in bits <15:8>.
52 *
53 * This function must be modified for every new Octeon board.
54 * Internally it uses switch statements based on the cvmx_sysinfo
55 * data to determine board types and revisions. It replies on the
56 * fact that every Octeon board receives a unique board type
57 * enumeration from the bootloader.
58 *
59 * @ipd_port: Octeon IPD port to get the MII address for.
60 *
61 * Returns MII PHY address and bus number or -1.
62 */
63 int cvmx_helper_board_get_mii_address(int ipd_port)
64 {
65 switch (cvmx_sysinfo_get()->board_type) {
66 case CVMX_BOARD_TYPE_SIM:
67 /* Simulator doesn't have MII */
68 return -1;
69 case CVMX_BOARD_TYPE_EBT3000:
70 case CVMX_BOARD_TYPE_EBT5800:
71 case CVMX_BOARD_TYPE_THUNDER:
72 case CVMX_BOARD_TYPE_NICPRO2:
73 /* Interface 0 is SPI4, interface 1 is RGMII */
74 if ((ipd_port >= 16) && (ipd_port < 20))
75 return ipd_port - 16;
76 else
77 return -1;
78 case CVMX_BOARD_TYPE_KODAMA:
79 case CVMX_BOARD_TYPE_EBH3100:
80 case CVMX_BOARD_TYPE_HIKARI:
81 case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
82 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
83 case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
84 /*
85 * Port 0 is WAN connected to a PHY, Port 1 is GMII
86 * connected to a switch
87 */
88 if (ipd_port == 0)
89 return 4;
90 else if (ipd_port == 1)
91 return 9;
92 else
93 return -1;
94 case CVMX_BOARD_TYPE_NAC38:
95 /* Board has 8 RGMII ports PHYs are 0-7 */
96 if ((ipd_port >= 0) && (ipd_port < 4))
97 return ipd_port;
98 else if ((ipd_port >= 16) && (ipd_port < 20))
99 return ipd_port - 16 + 4;
100 else
101 return -1;
102 case CVMX_BOARD_TYPE_EBH3000:
103 /* Board has dual SPI4 and no PHYs */
104 return -1;
105 case CVMX_BOARD_TYPE_EBH5200:
106 case CVMX_BOARD_TYPE_EBH5201:
107 case CVMX_BOARD_TYPE_EBT5200:
108 /* Board has 2 management ports */
109 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) &&
110 (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
111 return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT;
112 /*
113 * Board has 4 SGMII ports. The PHYs start right after the MII
114 * ports MII0 = 0, MII1 = 1, SGMII = 2-5.
115 */
116 if ((ipd_port >= 0) && (ipd_port < 4))
117 return ipd_port + 2;
118 else
119 return -1;
120 case CVMX_BOARD_TYPE_EBH5600:
121 case CVMX_BOARD_TYPE_EBH5601:
122 case CVMX_BOARD_TYPE_EBH5610:
123 /* Board has 1 management port */
124 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
125 return 0;
126 /*
127 * Board has 8 SGMII ports. 4 connect out, two connect
128 * to a switch, and 2 loop to each other
129 */
130 if ((ipd_port >= 0) && (ipd_port < 4))
131 return ipd_port + 1;
132 else
133 return -1;
134 case CVMX_BOARD_TYPE_CUST_NB5:
135 if (ipd_port == 2)
136 return 4;
137 else
138 return -1;
139 case CVMX_BOARD_TYPE_NIC_XLE_4G:
140 /* Board has 4 SGMII ports. connected QLM3(interface 1) */
141 if ((ipd_port >= 16) && (ipd_port < 20))
142 return ipd_port - 16 + 1;
143 else
144 return -1;
145 case CVMX_BOARD_TYPE_NIC_XLE_10G:
146 case CVMX_BOARD_TYPE_NIC10E:
147 return -1;
148 case CVMX_BOARD_TYPE_NIC4E:
149 if (ipd_port >= 0 && ipd_port <= 3)
150 return (ipd_port + 0x1f) & 0x1f;
151 else
152 return -1;
153 case CVMX_BOARD_TYPE_NIC2E:
154 if (ipd_port >= 0 && ipd_port <= 1)
155 return ipd_port + 1;
156 else
157 return -1;
158 case CVMX_BOARD_TYPE_BBGW_REF:
159 /*
160 * No PHYs are connected to Octeon, everything is
161 * through switch.
162 */
163 return -1;
164
165 case CVMX_BOARD_TYPE_CUST_WSX16:
166 if (ipd_port >= 0 && ipd_port <= 3)
167 return ipd_port;
168 else if (ipd_port >= 16 && ipd_port <= 19)
169 return ipd_port - 16 + 4;
170 else
171 return -1;
172 case CVMX_BOARD_TYPE_UBNT_E100:
173 if (ipd_port >= 0 && ipd_port <= 2)
174 return 7 - ipd_port;
175 else
176 return -1;
177 case CVMX_BOARD_TYPE_KONTRON_S1901:
178 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
179 return 1;
180 else
181 return -1;
182
183 }
184
185 /* Some unknown board. Somebody forgot to update this function... */
186 cvmx_dprintf
187 ("cvmx_helper_board_get_mii_address: Unknown board type %d\n",
188 cvmx_sysinfo_get()->board_type);
189 return -1;
190 }
191
192 /**
193 * This function is the board specific method of determining an
194 * ethernet ports link speed. Most Octeon boards have Marvell PHYs
195 * and are handled by the fall through case. This function must be
196 * updated for boards that don't have the normal Marvell PHYs.
197 *
198 * This function must be modified for every new Octeon board.
199 * Internally it uses switch statements based on the cvmx_sysinfo
200 * data to determine board types and revisions. It relies on the
201 * fact that every Octeon board receives a unique board type
202 * enumeration from the bootloader.
203 *
204 * @ipd_port: IPD input port associated with the port we want to get link
205 * status for.
206 *
207 * Returns The ports link status. If the link isn't fully resolved, this must
208 * return zero.
209 */
210 cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
211 {
212 cvmx_helper_link_info_t result;
213
214 WARN(!octeon_is_simulation(),
215 "Using deprecated link status - please update your DT");
216
217 /* Unless we fix it later, all links are defaulted to down */
218 result.u64 = 0;
219
220 if (octeon_is_simulation()) {
221 /* The simulator gives you a simulated 1Gbps full duplex link */
222 result.s.link_up = 1;
223 result.s.full_duplex = 1;
224 result.s.speed = 1000;
225 return result;
226 }
227
228 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
229 || OCTEON_IS_MODEL(OCTEON_CN58XX)
230 || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
231 /*
232 * We don't have a PHY address, so attempt to use
233 * in-band status. It is really important that boards
234 * not supporting in-band status never get
235 * here. Reading broken in-band status tends to do bad
236 * things
237 */
238 union cvmx_gmxx_rxx_rx_inbnd inband_status;
239 int interface = cvmx_helper_get_interface_num(ipd_port);
240 int index = cvmx_helper_get_interface_index_num(ipd_port);
241 inband_status.u64 =
242 cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));
243
244 result.s.link_up = inband_status.s.status;
245 result.s.full_duplex = inband_status.s.duplex;
246 switch (inband_status.s.speed) {
247 case 0: /* 10 Mbps */
248 result.s.speed = 10;
249 break;
250 case 1: /* 100 Mbps */
251 result.s.speed = 100;
252 break;
253 case 2: /* 1 Gbps */
254 result.s.speed = 1000;
255 break;
256 case 3: /* Illegal */
257 result.u64 = 0;
258 break;
259 }
260 } else {
261 /*
262 * We don't have a PHY address and we don't have
263 * in-band status. There is no way to determine the
264 * link speed. Return down assuming this port isn't
265 * wired
266 */
267 result.u64 = 0;
268 }
269
270 /* If link is down, return all fields as zero. */
271 if (!result.s.link_up)
272 result.u64 = 0;
273
274 return result;
275 }
276
277 /**
278 * This function is called by cvmx_helper_interface_probe() after it
279 * determines the number of ports Octeon can support on a specific
280 * interface. This function is the per board location to override
281 * this value. It is called with the number of ports Octeon might
282 * support and should return the number of actual ports on the
283 * board.
284 *
285 * This function must be modifed for every new Octeon board.
286 * Internally it uses switch statements based on the cvmx_sysinfo
287 * data to determine board types and revisions. It relys on the
288 * fact that every Octeon board receives a unique board type
289 * enumeration from the bootloader.
290 *
291 * @interface: Interface to probe
292 * @supported_ports:
293 * Number of ports Octeon supports.
294 *
295 * Returns Number of ports the actual board supports. Many times this will
296 * simple be "support_ports".
297 */
298 int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
299 {
300 switch (cvmx_sysinfo_get()->board_type) {
301 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
302 if (interface == 0)
303 return 2;
304 break;
305 case CVMX_BOARD_TYPE_BBGW_REF:
306 if (interface == 0)
307 return 2;
308 break;
309 case CVMX_BOARD_TYPE_NIC_XLE_4G:
310 if (interface == 0)
311 return 0;
312 break;
313 /* The 2nd interface on the EBH5600 is connected to the Marvel switch,
314 which we don't support. Disable ports connected to it */
315 case CVMX_BOARD_TYPE_EBH5600:
316 if (interface == 1)
317 return 0;
318 break;
319 }
320 return supported_ports;
321 }
322
323 /**
324 * Get the clock type used for the USB block based on board type.
325 * Used by the USB code for auto configuration of clock type.
326 *
327 * Return USB clock type enumeration
328 */
329 enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void)
330 {
331 switch (cvmx_sysinfo_get()->board_type) {
332 case CVMX_BOARD_TYPE_BBGW_REF:
333 case CVMX_BOARD_TYPE_LANAI2_A:
334 case CVMX_BOARD_TYPE_LANAI2_U:
335 case CVMX_BOARD_TYPE_LANAI2_G:
336 case CVMX_BOARD_TYPE_NIC10E_66:
337 case CVMX_BOARD_TYPE_UBNT_E100:
338 return USB_CLOCK_TYPE_CRYSTAL_12;
339 case CVMX_BOARD_TYPE_NIC10E:
340 return USB_CLOCK_TYPE_REF_12;
341 default:
342 break;
343 }
344 /* Most boards except NIC10e use a 12MHz crystal */
345 if (OCTEON_IS_OCTEON2())
346 return USB_CLOCK_TYPE_CRYSTAL_12;
347 return USB_CLOCK_TYPE_REF_48;
348 }