root/arch/mips/loongson64/common/cs5536/cs5536_acc.c

DEFINITIONS

1. pci_acc_write_reg
2. pci_acc_read_reg

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * the ACC Virtual Support Module of AMD CS5536
   4  *
   5  * Copyright (C) 2007 Lemote, Inc.
   6  * Author : jlliu, liujl@lemote.com
   7  *
   8  * Copyright (C) 2009 Lemote, Inc.
   9  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  10  */
  11 
  12 #include <cs5536/cs5536.h>
  13 #include <cs5536/cs5536_pci.h>
  14 
  15 void pci_acc_write_reg(int reg, u32 value)
  16 {
  17         u32 hi = 0, lo = value;
  18 
  19         switch (reg) {
  20         case PCI_COMMAND:
  21                 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
  22                 if (value & PCI_COMMAND_MASTER)
  23                         lo |= (0x03 << 8);
  24                 else
  25                         lo &= ~(0x03 << 8);
  26                 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
  27                 break;
  28         case PCI_STATUS:
  29                 if (value & PCI_STATUS_PARITY) {
  30                         _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
  31                         if (lo & SB_PARE_ERR_FLAG) {
  32                                 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
  33                                 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
  34                         }
  35                 }
  36                 break;
  37         case PCI_BAR0_REG:
  38                 if (value == PCI_BAR_RANGE_MASK) {
  39                         _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
  40                         lo |= SOFT_BAR_ACC_FLAG;
  41                         _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
  42                 } else if (value & 0x01) {
  43                         value &= 0xfffffffc;
  44                         hi = 0xA0000000 | ((value & 0x000ff000) >> 12);
  45                         lo = 0x000fff80 | ((value & 0x00000fff) << 20);
  46                         _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo);
  47                 }
  48                 break;
  49         case PCI_ACC_INT_REG:
  50                 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
  51                 /* disable all the usb interrupt in PIC */
  52                 lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
  53                 if (value)      /* enable all the acc interrupt in PIC */
  54                         lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT);
  55                 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
  56                 break;
  57         default:
  58                 break;
  59         }
  60 }
  61 
  62 u32 pci_acc_read_reg(int reg)
  63 {
  64         u32 hi, lo;
  65         u32 conf_data = 0;
  66 
  67         switch (reg) {
  68         case PCI_VENDOR_ID:
  69                 conf_data =
  70                     CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID);
  71                 break;
  72         case PCI_COMMAND:
  73                 _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
  74                 if (((lo & 0xfff00000) || (hi & 0x000000ff))
  75                     && ((hi & 0xf0000000) == 0xa0000000))
  76                         conf_data |= PCI_COMMAND_IO;
  77                 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
  78                 if ((lo & 0x300) == 0x300)
  79                         conf_data |= PCI_COMMAND_MASTER;
  80                 break;
  81         case PCI_STATUS:
  82                 conf_data |= PCI_STATUS_66MHZ;
  83                 conf_data |= PCI_STATUS_FAST_BACK;
  84                 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
  85                 if (lo & SB_PARE_ERR_FLAG)
  86                         conf_data |= PCI_STATUS_PARITY;
  87                 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
  88                 break;
  89         case PCI_CLASS_REVISION:
  90                 _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
  91                 conf_data = lo & 0x000000ff;
  92                 conf_data |= (CS5536_ACC_CLASS_CODE << 8);
  93                 break;
  94         case PCI_CACHE_LINE_SIZE:
  95                 conf_data =
  96                     CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
  97                                             PCI_NORMAL_LATENCY_TIMER);
  98                 break;
  99         case PCI_BAR0_REG:
 100                 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
 101                 if (lo & SOFT_BAR_ACC_FLAG) {
 102                         conf_data = CS5536_ACC_RANGE |
 103                             PCI_BASE_ADDRESS_SPACE_IO;
 104                         lo &= ~SOFT_BAR_ACC_FLAG;
 105                         _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
 106                 } else {
 107                         _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
 108                         conf_data = (hi & 0x000000ff) << 12;
 109                         conf_data |= (lo & 0xfff00000) >> 20;
 110                         conf_data |= 0x01;
 111                         conf_data &= ~0x02;
 112                 }
 113                 break;
 114         case PCI_CARDBUS_CIS:
 115                 conf_data = PCI_CARDBUS_CIS_POINTER;
 116                 break;
 117         case PCI_SUBSYSTEM_VENDOR_ID:
 118                 conf_data =
 119                     CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID);
 120                 break;
 121         case PCI_ROM_ADDRESS:
 122                 conf_data = PCI_EXPANSION_ROM_BAR;
 123                 break;
 124         case PCI_CAPABILITY_LIST:
 125                 conf_data = PCI_CAPLIST_USB_POINTER;
 126                 break;
 127         case PCI_INTERRUPT_LINE:
 128                 conf_data =
 129                     CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
 130                 break;
 131         default:
 132                 break;
 133         }
 134 
 135         return conf_data;
 136 }