root/arch/mips/loongson64/lemote-2f/irq.c

DEFINITIONS

1. mach_i8259_irq
2. i8259_irqdispatch
3. mach_irq_dispatch
4. ip6_action
5. mach_init_irq

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2007 Lemote Inc.
   4  * Author: Fuxin Zhang, zhangfx@lemote.com
   5  */
   6 
   7 #include <linux/export.h>
   8 #include <linux/init.h>
   9 #include <linux/interrupt.h>
  10 
  11 #include <asm/irq_cpu.h>
  12 #include <asm/i8259.h>
  13 #include <asm/mipsregs.h>
  14 
  15 #include <loongson.h>
  16 #include <machine.h>
  17 
  18 #define LOONGSON_TIMER_IRQ      (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
  19 #define LOONGSON_NORTH_BRIDGE_IRQ       (MIPS_CPU_IRQ_BASE + 6) /* bonito */
  20 #define LOONGSON_UART_IRQ       (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
  21 #define LOONGSON_SOUTH_BRIDGE_IRQ       (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
  22 
  23 #define LOONGSON_INT_BIT_INT0           (1 << 11)
  24 #define LOONGSON_INT_BIT_INT1           (1 << 12)
  25 
  26 /*
  27  * The generic i8259_irq() make the kernel hang on booting.  Since we cannot
  28  * get the irq via the IRR directly, we access the ISR instead.
  29  */
  30 int mach_i8259_irq(void)
  31 {
  32         int irq, isr;
  33 
  34         irq = -1;
  35 
  36         if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
  37                 raw_spin_lock(&i8259A_lock);
  38                 isr = inb(PIC_MASTER_CMD) &
  39                         ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
  40                 if (!isr)
  41                         isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8;
  42                 irq = ffs(isr) - 1;
  43                 if (unlikely(irq == 7)) {
  44                         /*
  45                          * This may be a spurious interrupt.
  46                          *
  47                          * Read the interrupt status register (ISR). If the most
  48                          * significant bit is not set then there is no valid
  49                          * interrupt.
  50                          */
  51                         outb(0x0B, PIC_MASTER_ISR);     /* ISR register */
  52                         if (~inb(PIC_MASTER_ISR) & 0x80)
  53                                 irq = -1;
  54                 }
  55                 raw_spin_unlock(&i8259A_lock);
  56         }
  57 
  58         return irq;
  59 }
  60 EXPORT_SYMBOL(mach_i8259_irq);
  61 
  62 static void i8259_irqdispatch(void)
  63 {
  64         int irq;
  65 
  66         irq = mach_i8259_irq();
  67         if (irq >= 0)
  68                 do_IRQ(irq);
  69         else
  70                 spurious_interrupt();
  71 }
  72 
  73 void mach_irq_dispatch(unsigned int pending)
  74 {
  75         if (pending & CAUSEF_IP7)
  76                 do_IRQ(LOONGSON_TIMER_IRQ);
  77         else if (pending & CAUSEF_IP6) {        /* North Bridge, Perf counter */
  78                 do_perfcnt_IRQ();
  79                 bonito_irqdispatch();
  80         } else if (pending & CAUSEF_IP3)        /* CPU UART */
  81                 do_IRQ(LOONGSON_UART_IRQ);
  82         else if (pending & CAUSEF_IP2)  /* South Bridge */
  83                 i8259_irqdispatch();
  84         else
  85                 spurious_interrupt();
  86 }
  87 
  88 static irqreturn_t ip6_action(int cpl, void *dev_id)
  89 {
  90         return IRQ_HANDLED;
  91 }
  92 
  93 static struct irqaction ip6_irqaction = {
  94         .handler = ip6_action,
  95         .name = "cascade",
  96         .flags = IRQF_SHARED | IRQF_NO_THREAD,
  97 };
  98 
  99 static struct irqaction cascade_irqaction = {
 100         .handler = no_action,
 101         .name = "cascade",
 102         .flags = IRQF_NO_THREAD | IRQF_NO_SUSPEND,
 103 };
 104 
 105 void __init mach_init_irq(void)
 106 {
 107         /* init all controller
 108          *   0-15         ------> i8259 interrupt
 109          *   16-23        ------> mips cpu interrupt
 110          *   32-63        ------> bonito irq
 111          */
 112 
 113         /* setup cs5536 as high level trigger */
 114         LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
 115         LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
 116 
 117         /* Sets the first-level interrupt dispatcher. */
 118         mips_cpu_irq_init();
 119         init_i8259_irqs();
 120         bonito_irq_init();
 121 
 122         /* setup north bridge irq (bonito) */
 123         setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction);
 124         /* setup source bridge irq (i8259) */
 125         setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction);
 126 }