root/scripts/dtc/include-prefixes/dt-bindings/memory/tegra30-mc.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
   3 #define DT_BINDINGS_MEMORY_TEGRA30_MC_H
   4 
   5 #define TEGRA_SWGROUP_PTC       0
   6 #define TEGRA_SWGROUP_DC        1
   7 #define TEGRA_SWGROUP_DCB       2
   8 #define TEGRA_SWGROUP_EPP       3
   9 #define TEGRA_SWGROUP_G2        4
  10 #define TEGRA_SWGROUP_MPE       5
  11 #define TEGRA_SWGROUP_VI        6
  12 #define TEGRA_SWGROUP_AFI       7
  13 #define TEGRA_SWGROUP_AVPC      8
  14 #define TEGRA_SWGROUP_NV        9
  15 #define TEGRA_SWGROUP_NV2       10
  16 #define TEGRA_SWGROUP_HDA       11
  17 #define TEGRA_SWGROUP_HC        12
  18 #define TEGRA_SWGROUP_PPCS      13
  19 #define TEGRA_SWGROUP_SATA      14
  20 #define TEGRA_SWGROUP_VDE       15
  21 #define TEGRA_SWGROUP_MPCORELP  16
  22 #define TEGRA_SWGROUP_MPCORE    17
  23 #define TEGRA_SWGROUP_ISP       18
  24 
  25 #define TEGRA30_MC_RESET_AFI            0
  26 #define TEGRA30_MC_RESET_AVPC           1
  27 #define TEGRA30_MC_RESET_DC             2
  28 #define TEGRA30_MC_RESET_DCB            3
  29 #define TEGRA30_MC_RESET_EPP            4
  30 #define TEGRA30_MC_RESET_2D             5
  31 #define TEGRA30_MC_RESET_HC             6
  32 #define TEGRA30_MC_RESET_HDA            7
  33 #define TEGRA30_MC_RESET_ISP            8
  34 #define TEGRA30_MC_RESET_MPCORE         9
  35 #define TEGRA30_MC_RESET_MPCORELP       10
  36 #define TEGRA30_MC_RESET_MPE            11
  37 #define TEGRA30_MC_RESET_3D             12
  38 #define TEGRA30_MC_RESET_3D2            13
  39 #define TEGRA30_MC_RESET_PPCS           14
  40 #define TEGRA30_MC_RESET_SATA           15
  41 #define TEGRA30_MC_RESET_VDE            16
  42 #define TEGRA30_MC_RESET_VI             17
  43 
  44 #endif