root/scripts/dtc/include-prefixes/dt-bindings/clock/mt2701-clk.h

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INCLUDED FROM


   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Shunli Wang <shunli.wang@mediatek.com>
   5  */
   6 
   7 #ifndef _DT_BINDINGS_CLK_MT2701_H
   8 #define _DT_BINDINGS_CLK_MT2701_H
   9 
  10 /* TOPCKGEN */
  11 #define CLK_TOP_SYSPLL                          1
  12 #define CLK_TOP_SYSPLL_D2                       2
  13 #define CLK_TOP_SYSPLL_D3                       3
  14 #define CLK_TOP_SYSPLL_D5                       4
  15 #define CLK_TOP_SYSPLL_D7                       5
  16 #define CLK_TOP_SYSPLL1_D2                      6
  17 #define CLK_TOP_SYSPLL1_D4                      7
  18 #define CLK_TOP_SYSPLL1_D8                      8
  19 #define CLK_TOP_SYSPLL1_D16                     9
  20 #define CLK_TOP_SYSPLL2_D2                      10
  21 #define CLK_TOP_SYSPLL2_D4                      11
  22 #define CLK_TOP_SYSPLL2_D8                      12
  23 #define CLK_TOP_SYSPLL3_D2                      13
  24 #define CLK_TOP_SYSPLL3_D4                      14
  25 #define CLK_TOP_SYSPLL4_D2                      15
  26 #define CLK_TOP_SYSPLL4_D4                      16
  27 #define CLK_TOP_UNIVPLL                         17
  28 #define CLK_TOP_UNIVPLL_D2                      18
  29 #define CLK_TOP_UNIVPLL_D3                      19
  30 #define CLK_TOP_UNIVPLL_D5                      20
  31 #define CLK_TOP_UNIVPLL_D7                      21
  32 #define CLK_TOP_UNIVPLL_D26                     22
  33 #define CLK_TOP_UNIVPLL_D52                     23
  34 #define CLK_TOP_UNIVPLL_D108                    24
  35 #define CLK_TOP_USB_PHY48M                      25
  36 #define CLK_TOP_UNIVPLL1_D2                     26
  37 #define CLK_TOP_UNIVPLL1_D4                     27
  38 #define CLK_TOP_UNIVPLL1_D8                     28
  39 #define CLK_TOP_UNIVPLL2_D2                     29
  40 #define CLK_TOP_UNIVPLL2_D4                     30
  41 #define CLK_TOP_UNIVPLL2_D8                     31
  42 #define CLK_TOP_UNIVPLL2_D16                    32
  43 #define CLK_TOP_UNIVPLL2_D32                    33
  44 #define CLK_TOP_UNIVPLL3_D2                     34
  45 #define CLK_TOP_UNIVPLL3_D4                     35
  46 #define CLK_TOP_UNIVPLL3_D8                     36
  47 #define CLK_TOP_MSDCPLL                         37
  48 #define CLK_TOP_MSDCPLL_D2                      38
  49 #define CLK_TOP_MSDCPLL_D4                      39
  50 #define CLK_TOP_MSDCPLL_D8                      40
  51 #define CLK_TOP_MMPLL                           41
  52 #define CLK_TOP_MMPLL_D2                        42
  53 #define CLK_TOP_DMPLL                           43
  54 #define CLK_TOP_DMPLL_D2                        44
  55 #define CLK_TOP_DMPLL_D4                        45
  56 #define CLK_TOP_DMPLL_X2                        46
  57 #define CLK_TOP_TVDPLL                          47
  58 #define CLK_TOP_TVDPLL_D2                       48
  59 #define CLK_TOP_TVDPLL_D4                       49
  60 #define CLK_TOP_TVD2PLL                         50
  61 #define CLK_TOP_TVD2PLL_D2                      51
  62 #define CLK_TOP_HADDS2PLL_98M                   52
  63 #define CLK_TOP_HADDS2PLL_294M                  53
  64 #define CLK_TOP_HADDS2_FB                       54
  65 #define CLK_TOP_MIPIPLL_D2                      55
  66 #define CLK_TOP_MIPIPLL_D4                      56
  67 #define CLK_TOP_HDMIPLL                         57
  68 #define CLK_TOP_HDMIPLL_D2                      58
  69 #define CLK_TOP_HDMIPLL_D3                      59
  70 #define CLK_TOP_HDMI_SCL_RX                     60
  71 #define CLK_TOP_HDMI_0_PIX340M                  61
  72 #define CLK_TOP_HDMI_0_DEEP340M                 62
  73 #define CLK_TOP_HDMI_0_PLL340M                  63
  74 #define CLK_TOP_AUD1PLL_98M                     64
  75 #define CLK_TOP_AUD2PLL_90M                     65
  76 #define CLK_TOP_AUDPLL                          66
  77 #define CLK_TOP_AUDPLL_D4                       67
  78 #define CLK_TOP_AUDPLL_D8                       68
  79 #define CLK_TOP_AUDPLL_D16                      69
  80 #define CLK_TOP_AUDPLL_D24                      70
  81 #define CLK_TOP_ETHPLL_500M                     71
  82 #define CLK_TOP_VDECPLL                         72
  83 #define CLK_TOP_VENCPLL                         73
  84 #define CLK_TOP_MIPIPLL                         74
  85 #define CLK_TOP_ARMPLL_1P3G                     75
  86 
  87 #define CLK_TOP_MM_SEL                          76
  88 #define CLK_TOP_DDRPHYCFG_SEL                   77
  89 #define CLK_TOP_MEM_SEL                         78
  90 #define CLK_TOP_AXI_SEL                         79
  91 #define CLK_TOP_CAMTG_SEL                       80
  92 #define CLK_TOP_MFG_SEL                         81
  93 #define CLK_TOP_VDEC_SEL                        82
  94 #define CLK_TOP_PWM_SEL                         83
  95 #define CLK_TOP_MSDC30_0_SEL                    84
  96 #define CLK_TOP_USB20_SEL                       85
  97 #define CLK_TOP_SPI0_SEL                        86
  98 #define CLK_TOP_UART_SEL                        87
  99 #define CLK_TOP_AUDINTBUS_SEL                   88
 100 #define CLK_TOP_AUDIO_SEL                       89
 101 #define CLK_TOP_MSDC30_2_SEL                    90
 102 #define CLK_TOP_MSDC30_1_SEL                    91
 103 #define CLK_TOP_DPI1_SEL                        92
 104 #define CLK_TOP_DPI0_SEL                        93
 105 #define CLK_TOP_SCP_SEL                         94
 106 #define CLK_TOP_PMICSPI_SEL                     95
 107 #define CLK_TOP_APLL_SEL                        96
 108 #define CLK_TOP_HDMI_SEL                        97
 109 #define CLK_TOP_TVE_SEL                         98
 110 #define CLK_TOP_EMMC_HCLK_SEL                   99
 111 #define CLK_TOP_NFI2X_SEL                       100
 112 #define CLK_TOP_RTC_SEL                         101
 113 #define CLK_TOP_OSD_SEL                         102
 114 #define CLK_TOP_NR_SEL                          103
 115 #define CLK_TOP_DI_SEL                          104
 116 #define CLK_TOP_FLASH_SEL                       105
 117 #define CLK_TOP_ASM_M_SEL                       106
 118 #define CLK_TOP_ASM_I_SEL                       107
 119 #define CLK_TOP_INTDIR_SEL                      108
 120 #define CLK_TOP_HDMIRX_BIST_SEL                 109
 121 #define CLK_TOP_ETHIF_SEL                       110
 122 #define CLK_TOP_MS_CARD_SEL                     111
 123 #define CLK_TOP_ASM_H_SEL                       112
 124 #define CLK_TOP_SPI1_SEL                        113
 125 #define CLK_TOP_CMSYS_SEL                       114
 126 #define CLK_TOP_MSDC30_3_SEL                    115
 127 #define CLK_TOP_HDMIRX26_24_SEL                 116
 128 #define CLK_TOP_AUD2DVD_SEL                     117
 129 #define CLK_TOP_8BDAC_SEL                       118
 130 #define CLK_TOP_SPI2_SEL                        119
 131 #define CLK_TOP_AUD_MUX1_SEL                    120
 132 #define CLK_TOP_AUD_MUX2_SEL                    121
 133 #define CLK_TOP_AUDPLL_MUX_SEL                  122
 134 #define CLK_TOP_AUD_K1_SRC_SEL                  123
 135 #define CLK_TOP_AUD_K2_SRC_SEL                  124
 136 #define CLK_TOP_AUD_K3_SRC_SEL                  125
 137 #define CLK_TOP_AUD_K4_SRC_SEL                  126
 138 #define CLK_TOP_AUD_K5_SRC_SEL                  127
 139 #define CLK_TOP_AUD_K6_SRC_SEL                  128
 140 #define CLK_TOP_PADMCLK_SEL                     129
 141 #define CLK_TOP_AUD_EXTCK1_DIV                  130
 142 #define CLK_TOP_AUD_EXTCK2_DIV                  131
 143 #define CLK_TOP_AUD_MUX1_DIV                    132
 144 #define CLK_TOP_AUD_MUX2_DIV                    133
 145 #define CLK_TOP_AUD_K1_SRC_DIV                  134
 146 #define CLK_TOP_AUD_K2_SRC_DIV                  135
 147 #define CLK_TOP_AUD_K3_SRC_DIV                  136
 148 #define CLK_TOP_AUD_K4_SRC_DIV                  137
 149 #define CLK_TOP_AUD_K5_SRC_DIV                  138
 150 #define CLK_TOP_AUD_K6_SRC_DIV                  139
 151 #define CLK_TOP_AUD_I2S1_MCLK                   140
 152 #define CLK_TOP_AUD_I2S2_MCLK                   141
 153 #define CLK_TOP_AUD_I2S3_MCLK                   142
 154 #define CLK_TOP_AUD_I2S4_MCLK                   143
 155 #define CLK_TOP_AUD_I2S5_MCLK                   144
 156 #define CLK_TOP_AUD_I2S6_MCLK                   145
 157 #define CLK_TOP_AUD_48K_TIMING                  146
 158 #define CLK_TOP_AUD_44K_TIMING                  147
 159 
 160 #define CLK_TOP_32K_INTERNAL                    148
 161 #define CLK_TOP_32K_EXTERNAL                    149
 162 #define CLK_TOP_CLK26M_D8                       150
 163 #define CLK_TOP_8BDAC                           151
 164 #define CLK_TOP_WBG_DIG_416M                    152
 165 #define CLK_TOP_DPI                             153
 166 #define CLK_TOP_DSI0_LNTC_DSI                   154
 167 #define CLK_TOP_AUD_EXT1                        155
 168 #define CLK_TOP_AUD_EXT2                        156
 169 #define CLK_TOP_NFI1X_PAD                       157
 170 #define CLK_TOP_AXISEL_D4                       158
 171 #define CLK_TOP_NR                              159
 172 
 173 /* APMIXEDSYS */
 174 
 175 #define CLK_APMIXED_ARMPLL                      1
 176 #define CLK_APMIXED_MAINPLL                     2
 177 #define CLK_APMIXED_UNIVPLL                     3
 178 #define CLK_APMIXED_MMPLL                       4
 179 #define CLK_APMIXED_MSDCPLL                     5
 180 #define CLK_APMIXED_TVDPLL                      6
 181 #define CLK_APMIXED_AUD1PLL                     7
 182 #define CLK_APMIXED_TRGPLL                      8
 183 #define CLK_APMIXED_ETHPLL                      9
 184 #define CLK_APMIXED_VDECPLL                     10
 185 #define CLK_APMIXED_HADDS2PLL                   11
 186 #define CLK_APMIXED_AUD2PLL                     12
 187 #define CLK_APMIXED_TVD2PLL                     13
 188 #define CLK_APMIXED_HDMI_REF                    14
 189 #define CLK_APMIXED_NR                          15
 190 
 191 /* DDRPHY */
 192 
 193 #define CLK_DDRPHY_VENCPLL                      1
 194 #define CLK_DDRPHY_NR                           2
 195 
 196 /* INFRACFG */
 197 
 198 #define CLK_INFRA_DBG                           1
 199 #define CLK_INFRA_SMI                           2
 200 #define CLK_INFRA_QAXI_CM4                      3
 201 #define CLK_INFRA_AUD_SPLIN_B                   4
 202 #define CLK_INFRA_AUDIO                         5
 203 #define CLK_INFRA_EFUSE                         6
 204 #define CLK_INFRA_L2C_SRAM                      7
 205 #define CLK_INFRA_M4U                           8
 206 #define CLK_INFRA_CONNMCU                       9
 207 #define CLK_INFRA_TRNG                          10
 208 #define CLK_INFRA_RAMBUFIF                      11
 209 #define CLK_INFRA_CPUM                          12
 210 #define CLK_INFRA_KP                            13
 211 #define CLK_INFRA_CEC                           14
 212 #define CLK_INFRA_IRRX                          15
 213 #define CLK_INFRA_PMICSPI                       16
 214 #define CLK_INFRA_PMICWRAP                      17
 215 #define CLK_INFRA_DDCCI                         18
 216 #define CLK_INFRA_CLK_13M                       19
 217 #define CLK_INFRA_CPUSEL                        20
 218 #define CLK_INFRA_NR                            21
 219 
 220 /* PERICFG */
 221 
 222 #define CLK_PERI_NFI                            1
 223 #define CLK_PERI_THERM                          2
 224 #define CLK_PERI_PWM1                           3
 225 #define CLK_PERI_PWM2                           4
 226 #define CLK_PERI_PWM3                           5
 227 #define CLK_PERI_PWM4                           6
 228 #define CLK_PERI_PWM5                           7
 229 #define CLK_PERI_PWM6                           8
 230 #define CLK_PERI_PWM7                           9
 231 #define CLK_PERI_PWM                            10
 232 #define CLK_PERI_USB0                           11
 233 #define CLK_PERI_USB1                           12
 234 #define CLK_PERI_AP_DMA                         13
 235 #define CLK_PERI_MSDC30_0                       14
 236 #define CLK_PERI_MSDC30_1                       15
 237 #define CLK_PERI_MSDC30_2                       16
 238 #define CLK_PERI_MSDC30_3                       17
 239 #define CLK_PERI_MSDC50_3                       18
 240 #define CLK_PERI_NLI                            19
 241 #define CLK_PERI_UART0                          20
 242 #define CLK_PERI_UART1                          21
 243 #define CLK_PERI_UART2                          22
 244 #define CLK_PERI_UART3                          23
 245 #define CLK_PERI_BTIF                           24
 246 #define CLK_PERI_I2C0                           25
 247 #define CLK_PERI_I2C1                           26
 248 #define CLK_PERI_I2C2                           27
 249 #define CLK_PERI_I2C3                           28
 250 #define CLK_PERI_AUXADC                         29
 251 #define CLK_PERI_SPI0                           30
 252 #define CLK_PERI_ETH                            31
 253 #define CLK_PERI_USB0_MCU                       32
 254 
 255 #define CLK_PERI_USB1_MCU                       33
 256 #define CLK_PERI_USB_SLV                        34
 257 #define CLK_PERI_GCPU                           35
 258 #define CLK_PERI_NFI_ECC                        36
 259 #define CLK_PERI_NFI_PAD                        37
 260 #define CLK_PERI_FLASH                          38
 261 #define CLK_PERI_HOST89_INT                     39
 262 #define CLK_PERI_HOST89_SPI                     40
 263 #define CLK_PERI_HOST89_DVD                     41
 264 #define CLK_PERI_SPI1                           42
 265 #define CLK_PERI_SPI2                           43
 266 #define CLK_PERI_FCI                            44
 267 
 268 #define CLK_PERI_UART0_SEL                      45
 269 #define CLK_PERI_UART1_SEL                      46
 270 #define CLK_PERI_UART2_SEL                      47
 271 #define CLK_PERI_UART3_SEL                      48
 272 #define CLK_PERI_NR                             49
 273 
 274 /* AUDIO */
 275 
 276 #define CLK_AUD_AFE                             1
 277 #define CLK_AUD_LRCK_DETECT                     2
 278 #define CLK_AUD_I2S                             3
 279 #define CLK_AUD_APLL_TUNER                      4
 280 #define CLK_AUD_HDMI                            5
 281 #define CLK_AUD_SPDF                            6
 282 #define CLK_AUD_SPDF2                           7
 283 #define CLK_AUD_APLL                            8
 284 #define CLK_AUD_TML                             9
 285 #define CLK_AUD_AHB_IDLE_EXT                    10
 286 #define CLK_AUD_AHB_IDLE_INT                    11
 287 
 288 #define CLK_AUD_I2SIN1                          12
 289 #define CLK_AUD_I2SIN2                          13
 290 #define CLK_AUD_I2SIN3                          14
 291 #define CLK_AUD_I2SIN4                          15
 292 #define CLK_AUD_I2SIN5                          16
 293 #define CLK_AUD_I2SIN6                          17
 294 #define CLK_AUD_I2SO1                           18
 295 #define CLK_AUD_I2SO2                           19
 296 #define CLK_AUD_I2SO3                           20
 297 #define CLK_AUD_I2SO4                           21
 298 #define CLK_AUD_I2SO5                           22
 299 #define CLK_AUD_I2SO6                           23
 300 #define CLK_AUD_ASRCI1                          24
 301 #define CLK_AUD_ASRCI2                          25
 302 #define CLK_AUD_ASRCO1                          26
 303 #define CLK_AUD_ASRCO2                          27
 304 #define CLK_AUD_ASRC11                          28
 305 #define CLK_AUD_ASRC12                          29
 306 #define CLK_AUD_HDMIRX                          30
 307 #define CLK_AUD_INTDIR                          31
 308 #define CLK_AUD_A1SYS                           32
 309 #define CLK_AUD_A2SYS                           33
 310 #define CLK_AUD_AFE_CONN                        34
 311 #define CLK_AUD_AFE_PCMIF                       35
 312 #define CLK_AUD_AFE_MRGIF                       36
 313 
 314 #define CLK_AUD_MMIF_UL1                        37
 315 #define CLK_AUD_MMIF_UL2                        38
 316 #define CLK_AUD_MMIF_UL3                        39
 317 #define CLK_AUD_MMIF_UL4                        40
 318 #define CLK_AUD_MMIF_UL5                        41
 319 #define CLK_AUD_MMIF_UL6                        42
 320 #define CLK_AUD_MMIF_DL1                        43
 321 #define CLK_AUD_MMIF_DL2                        44
 322 #define CLK_AUD_MMIF_DL3                        45
 323 #define CLK_AUD_MMIF_DL4                        46
 324 #define CLK_AUD_MMIF_DL5                        47
 325 #define CLK_AUD_MMIF_DL6                        48
 326 #define CLK_AUD_MMIF_DLMCH                      49
 327 #define CLK_AUD_MMIF_ARB1                       50
 328 #define CLK_AUD_MMIF_AWB1                       51
 329 #define CLK_AUD_MMIF_AWB2                       52
 330 #define CLK_AUD_MMIF_DAI                        53
 331 
 332 #define CLK_AUD_DMIC1                           54
 333 #define CLK_AUD_DMIC2                           55
 334 #define CLK_AUD_ASRCI3                          56
 335 #define CLK_AUD_ASRCI4                          57
 336 #define CLK_AUD_ASRCI5                          58
 337 #define CLK_AUD_ASRCI6                          59
 338 #define CLK_AUD_ASRCO3                          60
 339 #define CLK_AUD_ASRCO4                          61
 340 #define CLK_AUD_ASRCO5                          62
 341 #define CLK_AUD_ASRCO6                          63
 342 #define CLK_AUD_MEM_ASRC1                       64
 343 #define CLK_AUD_MEM_ASRC2                       65
 344 #define CLK_AUD_MEM_ASRC3                       66
 345 #define CLK_AUD_MEM_ASRC4                       67
 346 #define CLK_AUD_MEM_ASRC5                       68
 347 #define CLK_AUD_DSD_ENC                         69
 348 #define CLK_AUD_ASRC_BRG                        70
 349 #define CLK_AUD_NR                              71
 350 
 351 /* MMSYS */
 352 
 353 #define CLK_MM_SMI_COMMON                       1
 354 #define CLK_MM_SMI_LARB0                        2
 355 #define CLK_MM_CMDQ                             3
 356 #define CLK_MM_MUTEX                            4
 357 #define CLK_MM_DISP_COLOR                       5
 358 #define CLK_MM_DISP_BLS                         6
 359 #define CLK_MM_DISP_WDMA                        7
 360 #define CLK_MM_DISP_RDMA                        8
 361 #define CLK_MM_DISP_OVL                         9
 362 #define CLK_MM_MDP_TDSHP                        10
 363 #define CLK_MM_MDP_WROT                         11
 364 #define CLK_MM_MDP_WDMA                         12
 365 #define CLK_MM_MDP_RSZ1                         13
 366 #define CLK_MM_MDP_RSZ0                         14
 367 #define CLK_MM_MDP_RDMA                         15
 368 #define CLK_MM_MDP_BLS_26M                      16
 369 #define CLK_MM_CAM_MDP                          17
 370 #define CLK_MM_FAKE_ENG                         18
 371 #define CLK_MM_MUTEX_32K                        19
 372 #define CLK_MM_DISP_RDMA1                       20
 373 #define CLK_MM_DISP_UFOE                        21
 374 
 375 #define CLK_MM_DSI_ENGINE                       22
 376 #define CLK_MM_DSI_DIG                          23
 377 #define CLK_MM_DPI_DIGL                         24
 378 #define CLK_MM_DPI_ENGINE                       25
 379 #define CLK_MM_DPI1_DIGL                        26
 380 #define CLK_MM_DPI1_ENGINE                      27
 381 #define CLK_MM_TVE_OUTPUT                       28
 382 #define CLK_MM_TVE_INPUT                        29
 383 #define CLK_MM_HDMI_PIXEL                       30
 384 #define CLK_MM_HDMI_PLL                         31
 385 #define CLK_MM_HDMI_AUDIO                       32
 386 #define CLK_MM_HDMI_SPDIF                       33
 387 #define CLK_MM_TVE_FMM                          34
 388 #define CLK_MM_NR                               35
 389 
 390 /* IMGSYS */
 391 
 392 #define CLK_IMG_SMI_COMM                        1
 393 #define CLK_IMG_RESZ                            2
 394 #define CLK_IMG_JPGDEC_SMI                      3
 395 #define CLK_IMG_JPGDEC                          4
 396 #define CLK_IMG_VENC_LT                         5
 397 #define CLK_IMG_VENC                            6
 398 #define CLK_IMG_NR                              7
 399 
 400 /* VDEC */
 401 
 402 #define CLK_VDEC_CKGEN                          1
 403 #define CLK_VDEC_LARB                           2
 404 #define CLK_VDEC_NR                             3
 405 
 406 /* HIFSYS */
 407 
 408 #define CLK_HIFSYS_USB0PHY                      1
 409 #define CLK_HIFSYS_USB1PHY                      2
 410 #define CLK_HIFSYS_PCIE0                        3
 411 #define CLK_HIFSYS_PCIE1                        4
 412 #define CLK_HIFSYS_PCIE2                        5
 413 #define CLK_HIFSYS_NR                           6
 414 
 415 /* ETHSYS */
 416 #define CLK_ETHSYS_HSDMA                        1
 417 #define CLK_ETHSYS_ESW                          2
 418 #define CLK_ETHSYS_GP2                          3
 419 #define CLK_ETHSYS_GP1                          4
 420 #define CLK_ETHSYS_PCM                          5
 421 #define CLK_ETHSYS_GDMA                         6
 422 #define CLK_ETHSYS_I2S                          7
 423 #define CLK_ETHSYS_CRYPTO                       8
 424 #define CLK_ETHSYS_NR                           9
 425 
 426 /* G3DSYS */
 427 #define CLK_G3DSYS_CORE                         1
 428 #define CLK_G3DSYS_NR                           2
 429 
 430 /* BDP */
 431 
 432 #define CLK_BDP_BRG_BA                          1
 433 #define CLK_BDP_BRG_DRAM                        2
 434 #define CLK_BDP_LARB_DRAM                       3
 435 #define CLK_BDP_WR_VDI_PXL                      4
 436 #define CLK_BDP_WR_VDI_DRAM                     5
 437 #define CLK_BDP_WR_B                            6
 438 #define CLK_BDP_DGI_IN                          7
 439 #define CLK_BDP_DGI_OUT                         8
 440 #define CLK_BDP_FMT_MAST_27                     9
 441 #define CLK_BDP_FMT_B                           10
 442 #define CLK_BDP_OSD_B                           11
 443 #define CLK_BDP_OSD_DRAM                        12
 444 #define CLK_BDP_OSD_AGENT                       13
 445 #define CLK_BDP_OSD_PXL                         14
 446 #define CLK_BDP_RLE_B                           15
 447 #define CLK_BDP_RLE_AGENT                       16
 448 #define CLK_BDP_RLE_DRAM                        17
 449 #define CLK_BDP_F27M                            18
 450 #define CLK_BDP_F27M_VDOUT                      19
 451 #define CLK_BDP_F27_74_74                       20
 452 #define CLK_BDP_F2FS                            21
 453 #define CLK_BDP_F2FS74_148                      22
 454 #define CLK_BDP_FB                              23
 455 #define CLK_BDP_VDO_DRAM                        24
 456 #define CLK_BDP_VDO_2FS                         25
 457 #define CLK_BDP_VDO_B                           26
 458 #define CLK_BDP_WR_DI_PXL                       27
 459 #define CLK_BDP_WR_DI_DRAM                      28
 460 #define CLK_BDP_WR_DI_B                         29
 461 #define CLK_BDP_NR_PXL                          30
 462 #define CLK_BDP_NR_DRAM                         31
 463 #define CLK_BDP_NR_B                            32
 464 
 465 #define CLK_BDP_RX_F                            33
 466 #define CLK_BDP_RX_X                            34
 467 #define CLK_BDP_RXPDT                           35
 468 #define CLK_BDP_RX_CSCL_N                       36
 469 #define CLK_BDP_RX_CSCL                         37
 470 #define CLK_BDP_RX_DDCSCL_N                     38
 471 #define CLK_BDP_RX_DDCSCL                       39
 472 #define CLK_BDP_RX_VCO                          40
 473 #define CLK_BDP_RX_DP                           41
 474 #define CLK_BDP_RX_P                            42
 475 #define CLK_BDP_RX_M                            43
 476 #define CLK_BDP_RX_PLL                          44
 477 #define CLK_BDP_BRG_RT_B                        45
 478 #define CLK_BDP_BRG_RT_DRAM                     46
 479 #define CLK_BDP_LARBRT_DRAM                     47
 480 #define CLK_BDP_TMDS_SYN                        48
 481 #define CLK_BDP_HDMI_MON                        49
 482 #define CLK_BDP_NR                              50
 483 
 484 #endif /* _DT_BINDINGS_CLK_MT2701_H */

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