root/scripts/dtc/include-prefixes/dt-bindings/clock/am3.h

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INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright 2017 Texas Instruments, Inc.
   4  */
   5 #ifndef __DT_BINDINGS_CLK_AM3_H
   6 #define __DT_BINDINGS_CLK_AM3_H
   7 
   8 #define AM3_CLKCTRL_OFFSET      0x0
   9 #define AM3_CLKCTRL_INDEX(offset)       ((offset) - AM3_CLKCTRL_OFFSET)
  10 
  11 /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
  12 
  13 /* l4_per clocks */
  14 #define AM3_L4_PER_CLKCTRL_OFFSET       0x14
  15 #define AM3_L4_PER_CLKCTRL_INDEX(offset)        ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
  16 #define AM3_CPGMAC0_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0x14)
  17 #define AM3_LCDC_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0x18)
  18 #define AM3_USB_OTG_HS_CLKCTRL  AM3_L4_PER_CLKCTRL_INDEX(0x1c)
  19 #define AM3_TPTC0_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x24)
  20 #define AM3_EMIF_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0x28)
  21 #define AM3_OCMCRAM_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0x2c)
  22 #define AM3_GPMC_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0x30)
  23 #define AM3_MCASP0_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x34)
  24 #define AM3_UART6_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x38)
  25 #define AM3_MMC1_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0x3c)
  26 #define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40)
  27 #define AM3_I2C3_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0x44)
  28 #define AM3_I2C2_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0x48)
  29 #define AM3_SPI0_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0x4c)
  30 #define AM3_SPI1_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0x50)
  31 #define AM3_L4_LS_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x60)
  32 #define AM3_MCASP1_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x68)
  33 #define AM3_UART2_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x6c)
  34 #define AM3_UART3_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x70)
  35 #define AM3_UART4_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x74)
  36 #define AM3_UART5_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x78)
  37 #define AM3_TIMER7_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x7c)
  38 #define AM3_TIMER2_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x80)
  39 #define AM3_TIMER3_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x84)
  40 #define AM3_TIMER4_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0x88)
  41 #define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90)
  42 #define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94)
  43 #define AM3_SHAM_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0xa0)
  44 #define AM3_GPIO2_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0xac)
  45 #define AM3_GPIO3_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0xb0)
  46 #define AM3_GPIO4_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0xb4)
  47 #define AM3_TPCC_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0xbc)
  48 #define AM3_D_CAN0_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0xc0)
  49 #define AM3_D_CAN1_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0xc4)
  50 #define AM3_EPWMSS1_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0xcc)
  51 #define AM3_EPWMSS0_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0xd4)
  52 #define AM3_EPWMSS2_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0xd8)
  53 #define AM3_L3_INSTR_CLKCTRL    AM3_L4_PER_CLKCTRL_INDEX(0xdc)
  54 #define AM3_L3_MAIN_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0xe0)
  55 #define AM3_PRUSS_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0xe8)
  56 #define AM3_TIMER5_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0xec)
  57 #define AM3_TIMER6_CLKCTRL      AM3_L4_PER_CLKCTRL_INDEX(0xf0)
  58 #define AM3_MMC2_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0xf4)
  59 #define AM3_MMC3_CLKCTRL        AM3_L4_PER_CLKCTRL_INDEX(0xf8)
  60 #define AM3_TPTC1_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0xfc)
  61 #define AM3_TPTC2_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x100)
  62 #define AM3_SPINLOCK_CLKCTRL    AM3_L4_PER_CLKCTRL_INDEX(0x10c)
  63 #define AM3_MAILBOX_CLKCTRL     AM3_L4_PER_CLKCTRL_INDEX(0x110)
  64 #define AM3_L4_HS_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x120)
  65 #define AM3_OCPWP_CLKCTRL       AM3_L4_PER_CLKCTRL_INDEX(0x130)
  66 #define AM3_CLKDIV32K_CLKCTRL   AM3_L4_PER_CLKCTRL_INDEX(0x14c)
  67 
  68 /* l4_wkup clocks */
  69 #define AM3_L4_WKUP_CLKCTRL_OFFSET      0x4
  70 #define AM3_L4_WKUP_CLKCTRL_INDEX(offset)       ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
  71 #define AM3_CONTROL_CLKCTRL     AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
  72 #define AM3_GPIO1_CLKCTRL       AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
  73 #define AM3_L4_WKUP_CLKCTRL     AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
  74 #define AM3_DEBUGSS_CLKCTRL     AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
  75 #define AM3_WKUP_M3_CLKCTRL     AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
  76 #define AM3_UART1_CLKCTRL       AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
  77 #define AM3_I2C1_CLKCTRL        AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
  78 #define AM3_ADC_TSC_CLKCTRL     AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
  79 #define AM3_SMARTREFLEX0_CLKCTRL        AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
  80 #define AM3_TIMER1_CLKCTRL      AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
  81 #define AM3_SMARTREFLEX1_CLKCTRL        AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
  82 #define AM3_WD_TIMER2_CLKCTRL   AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
  83 
  84 /* mpu clocks */
  85 #define AM3_MPU_CLKCTRL_OFFSET  0x4
  86 #define AM3_MPU_CLKCTRL_INDEX(offset)   ((offset) - AM3_MPU_CLKCTRL_OFFSET)
  87 #define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4)
  88 
  89 /* l4_rtc clocks */
  90 #define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
  91 
  92 /* gfx_l3 clocks */
  93 #define AM3_GFX_L3_CLKCTRL_OFFSET       0x4
  94 #define AM3_GFX_L3_CLKCTRL_INDEX(offset)        ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
  95 #define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4)
  96 
  97 /* l4_cefuse clocks */
  98 #define AM3_L4_CEFUSE_CLKCTRL_OFFSET    0x20
  99 #define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset)     ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
 100 #define AM3_CEFUSE_CLKCTRL      AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
 101 
 102 /* XXX: Compatibility part end */
 103 
 104 /* l4ls clocks */
 105 #define AM3_L4LS_CLKCTRL_OFFSET 0x38
 106 #define AM3_L4LS_CLKCTRL_INDEX(offset)  ((offset) - AM3_L4LS_CLKCTRL_OFFSET)
 107 #define AM3_L4LS_UART6_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x38)
 108 #define AM3_L4LS_MMC1_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x3c)
 109 #define AM3_L4LS_ELM_CLKCTRL    AM3_L4LS_CLKCTRL_INDEX(0x40)
 110 #define AM3_L4LS_I2C3_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x44)
 111 #define AM3_L4LS_I2C2_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x48)
 112 #define AM3_L4LS_SPI0_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x4c)
 113 #define AM3_L4LS_SPI1_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x50)
 114 #define AM3_L4LS_L4_LS_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x60)
 115 #define AM3_L4LS_UART2_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x6c)
 116 #define AM3_L4LS_UART3_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x70)
 117 #define AM3_L4LS_UART4_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x74)
 118 #define AM3_L4LS_UART5_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x78)
 119 #define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c)
 120 #define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80)
 121 #define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84)
 122 #define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88)
 123 #define AM3_L4LS_RNG_CLKCTRL    AM3_L4LS_CLKCTRL_INDEX(0x90)
 124 #define AM3_L4LS_GPIO2_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0xac)
 125 #define AM3_L4LS_GPIO3_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0xb0)
 126 #define AM3_L4LS_GPIO4_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0xb4)
 127 #define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0)
 128 #define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4)
 129 #define AM3_L4LS_EPWMSS1_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0xcc)
 130 #define AM3_L4LS_EPWMSS0_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0xd4)
 131 #define AM3_L4LS_EPWMSS2_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0xd8)
 132 #define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec)
 133 #define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0)
 134 #define AM3_L4LS_MMC2_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0xf4)
 135 #define AM3_L4LS_SPINLOCK_CLKCTRL       AM3_L4LS_CLKCTRL_INDEX(0x10c)
 136 #define AM3_L4LS_MAILBOX_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0x110)
 137 #define AM3_L4LS_OCPWP_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x130)
 138 
 139 /* l3s clocks */
 140 #define AM3_L3S_CLKCTRL_OFFSET  0x1c
 141 #define AM3_L3S_CLKCTRL_INDEX(offset)   ((offset) - AM3_L3S_CLKCTRL_OFFSET)
 142 #define AM3_L3S_USB_OTG_HS_CLKCTRL      AM3_L3S_CLKCTRL_INDEX(0x1c)
 143 #define AM3_L3S_GPMC_CLKCTRL    AM3_L3S_CLKCTRL_INDEX(0x30)
 144 #define AM3_L3S_MCASP0_CLKCTRL  AM3_L3S_CLKCTRL_INDEX(0x34)
 145 #define AM3_L3S_MCASP1_CLKCTRL  AM3_L3S_CLKCTRL_INDEX(0x68)
 146 #define AM3_L3S_MMC3_CLKCTRL    AM3_L3S_CLKCTRL_INDEX(0xf8)
 147 
 148 /* l3 clocks */
 149 #define AM3_L3_CLKCTRL_OFFSET   0x24
 150 #define AM3_L3_CLKCTRL_INDEX(offset)    ((offset) - AM3_L3_CLKCTRL_OFFSET)
 151 #define AM3_L3_TPTC0_CLKCTRL    AM3_L3_CLKCTRL_INDEX(0x24)
 152 #define AM3_L3_EMIF_CLKCTRL     AM3_L3_CLKCTRL_INDEX(0x28)
 153 #define AM3_L3_OCMCRAM_CLKCTRL  AM3_L3_CLKCTRL_INDEX(0x2c)
 154 #define AM3_L3_AES_CLKCTRL      AM3_L3_CLKCTRL_INDEX(0x94)
 155 #define AM3_L3_SHAM_CLKCTRL     AM3_L3_CLKCTRL_INDEX(0xa0)
 156 #define AM3_L3_TPCC_CLKCTRL     AM3_L3_CLKCTRL_INDEX(0xbc)
 157 #define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc)
 158 #define AM3_L3_L3_MAIN_CLKCTRL  AM3_L3_CLKCTRL_INDEX(0xe0)
 159 #define AM3_L3_TPTC1_CLKCTRL    AM3_L3_CLKCTRL_INDEX(0xfc)
 160 #define AM3_L3_TPTC2_CLKCTRL    AM3_L3_CLKCTRL_INDEX(0x100)
 161 
 162 /* l4hs clocks */
 163 #define AM3_L4HS_CLKCTRL_OFFSET 0x120
 164 #define AM3_L4HS_CLKCTRL_INDEX(offset)  ((offset) - AM3_L4HS_CLKCTRL_OFFSET)
 165 #define AM3_L4HS_L4_HS_CLKCTRL  AM3_L4HS_CLKCTRL_INDEX(0x120)
 166 
 167 /* pruss_ocp clocks */
 168 #define AM3_PRUSS_OCP_CLKCTRL_OFFSET    0xe8
 169 #define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset)     ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
 170 #define AM3_PRUSS_OCP_PRUSS_CLKCTRL     AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
 171 
 172 /* cpsw_125mhz clocks */
 173 #define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14)
 174 
 175 /* lcdc clocks */
 176 #define AM3_LCDC_CLKCTRL_OFFSET 0x18
 177 #define AM3_LCDC_CLKCTRL_INDEX(offset)  ((offset) - AM3_LCDC_CLKCTRL_OFFSET)
 178 #define AM3_LCDC_LCDC_CLKCTRL   AM3_LCDC_CLKCTRL_INDEX(0x18)
 179 
 180 /* clk_24mhz clocks */
 181 #define AM3_CLK_24MHZ_CLKCTRL_OFFSET    0x14c
 182 #define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset)     ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
 183 #define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
 184 
 185 /* l4_wkup clocks */
 186 #define AM3_L4_WKUP_CONTROL_CLKCTRL     AM3_CLKCTRL_INDEX(0x4)
 187 #define AM3_L4_WKUP_GPIO1_CLKCTRL       AM3_CLKCTRL_INDEX(0x8)
 188 #define AM3_L4_WKUP_L4_WKUP_CLKCTRL     AM3_CLKCTRL_INDEX(0xc)
 189 #define AM3_L4_WKUP_UART1_CLKCTRL       AM3_CLKCTRL_INDEX(0xb4)
 190 #define AM3_L4_WKUP_I2C1_CLKCTRL        AM3_CLKCTRL_INDEX(0xb8)
 191 #define AM3_L4_WKUP_ADC_TSC_CLKCTRL     AM3_CLKCTRL_INDEX(0xbc)
 192 #define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL        AM3_CLKCTRL_INDEX(0xc0)
 193 #define AM3_L4_WKUP_TIMER1_CLKCTRL      AM3_CLKCTRL_INDEX(0xc4)
 194 #define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL        AM3_CLKCTRL_INDEX(0xc8)
 195 #define AM3_L4_WKUP_WD_TIMER2_CLKCTRL   AM3_CLKCTRL_INDEX(0xd4)
 196 
 197 /* l3_aon clocks */
 198 #define AM3_L3_AON_CLKCTRL_OFFSET       0x14
 199 #define AM3_L3_AON_CLKCTRL_INDEX(offset)        ((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
 200 #define AM3_L3_AON_DEBUGSS_CLKCTRL      AM3_L3_AON_CLKCTRL_INDEX(0x14)
 201 
 202 /* l4_wkup_aon clocks */
 203 #define AM3_L4_WKUP_AON_CLKCTRL_OFFSET  0xb0
 204 #define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset)   ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
 205 #define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
 206 
 207 /* mpu clocks */
 208 #define AM3_MPU_MPU_CLKCTRL     AM3_CLKCTRL_INDEX(0x4)
 209 
 210 /* l4_rtc clocks */
 211 #define AM3_L4_RTC_RTC_CLKCTRL  AM3_CLKCTRL_INDEX(0x0)
 212 
 213 /* gfx_l3 clocks */
 214 #define AM3_GFX_L3_GFX_CLKCTRL  AM3_CLKCTRL_INDEX(0x4)
 215 
 216 /* l4_cefuse clocks */
 217 #define AM3_L4_CEFUSE_CEFUSE_CLKCTRL    AM3_CLKCTRL_INDEX(0x20)
 218 
 219 #endif
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