1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43 #ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
44 #define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
45
46 #define CLK_PLL_AUDIO 2
47 #define CLK_PLL_PERIPH0 3
48
49 #define CLK_C0CPUX 12
50 #define CLK_C1CPUX 13
51
52 #define CLK_OUT_A 27
53 #define CLK_OUT_B 28
54
55 #define CLK_NAND0_0 29
56 #define CLK_NAND0_1 30
57 #define CLK_NAND1_0 31
58 #define CLK_NAND1_1 32
59 #define CLK_MMC0 33
60 #define CLK_MMC0_SAMPLE 34
61 #define CLK_MMC0_OUTPUT 35
62 #define CLK_MMC1 36
63 #define CLK_MMC1_SAMPLE 37
64 #define CLK_MMC1_OUTPUT 38
65 #define CLK_MMC2 39
66 #define CLK_MMC2_SAMPLE 40
67 #define CLK_MMC2_OUTPUT 41
68 #define CLK_MMC3 42
69 #define CLK_MMC3_SAMPLE 43
70 #define CLK_MMC3_OUTPUT 44
71 #define CLK_TS 45
72 #define CLK_SS 46
73 #define CLK_SPI0 47
74 #define CLK_SPI1 48
75 #define CLK_SPI2 49
76 #define CLK_SPI3 50
77 #define CLK_I2S0 51
78 #define CLK_I2S1 52
79 #define CLK_SPDIF 53
80 #define CLK_SDRAM 54
81 #define CLK_DE 55
82 #define CLK_EDP 56
83 #define CLK_MP 57
84 #define CLK_LCD0 58
85 #define CLK_LCD1 59
86 #define CLK_MIPI_DSI0 60
87 #define CLK_MIPI_DSI1 61
88 #define CLK_HDMI 62
89 #define CLK_HDMI_SLOW 63
90 #define CLK_MIPI_CSI 64
91 #define CLK_CSI_ISP 65
92 #define CLK_CSI_MISC 66
93 #define CLK_CSI0_MCLK 67
94 #define CLK_CSI1_MCLK 68
95 #define CLK_FD 69
96 #define CLK_VE 70
97 #define CLK_AVS 71
98 #define CLK_GPU_CORE 72
99 #define CLK_GPU_MEMORY 73
100 #define CLK_GPU_AXI 74
101 #define CLK_SATA 75
102 #define CLK_AC97 76
103 #define CLK_MIPI_HSI 77
104 #define CLK_GPADC 78
105 #define CLK_CIR_TX 79
106
107 #define CLK_BUS_FD 80
108 #define CLK_BUS_VE 81
109 #define CLK_BUS_GPU_CTRL 82
110 #define CLK_BUS_SS 83
111 #define CLK_BUS_MMC 84
112 #define CLK_BUS_NAND0 85
113 #define CLK_BUS_NAND1 86
114 #define CLK_BUS_SDRAM 87
115 #define CLK_BUS_MIPI_HSI 88
116 #define CLK_BUS_SATA 89
117 #define CLK_BUS_TS 90
118 #define CLK_BUS_SPI0 91
119 #define CLK_BUS_SPI1 92
120 #define CLK_BUS_SPI2 93
121 #define CLK_BUS_SPI3 94
122
123 #define CLK_BUS_OTG 95
124 #define CLK_BUS_USB 96
125 #define CLK_BUS_GMAC 97
126 #define CLK_BUS_MSGBOX 98
127 #define CLK_BUS_SPINLOCK 99
128 #define CLK_BUS_HSTIMER 100
129 #define CLK_BUS_DMA 101
130
131 #define CLK_BUS_LCD0 102
132 #define CLK_BUS_LCD1 103
133 #define CLK_BUS_EDP 104
134 #define CLK_BUS_CSI 105
135 #define CLK_BUS_HDMI 106
136 #define CLK_BUS_DE 107
137 #define CLK_BUS_MP 108
138 #define CLK_BUS_MIPI_DSI 109
139
140 #define CLK_BUS_SPDIF 110
141 #define CLK_BUS_PIO 111
142 #define CLK_BUS_AC97 112
143 #define CLK_BUS_I2S0 113
144 #define CLK_BUS_I2S1 114
145 #define CLK_BUS_LRADC 115
146 #define CLK_BUS_GPADC 116
147 #define CLK_BUS_TWD 117
148 #define CLK_BUS_CIR_TX 118
149
150 #define CLK_BUS_I2C0 119
151 #define CLK_BUS_I2C1 120
152 #define CLK_BUS_I2C2 121
153 #define CLK_BUS_I2C3 122
154 #define CLK_BUS_I2C4 123
155 #define CLK_BUS_UART0 124
156 #define CLK_BUS_UART1 125
157 #define CLK_BUS_UART2 126
158 #define CLK_BUS_UART3 127
159 #define CLK_BUS_UART4 128
160 #define CLK_BUS_UART5 129
161
162 #endif