1 /* SPDX-License-Identifier: GPL-2.0 */
2 /** @file */
3
4 #ifndef _MACH_T186_CLK_T186_H
5 #define _MACH_T186_CLK_T186_H
6
7 /**
8 * @defgroup clock_ids Clock Identifiers
9 * @{
10 * @defgroup extern_input external input clocks
11 * @{
12 * @def TEGRA186_CLK_OSC
13 * @def TEGRA186_CLK_CLK_32K
14 * @def TEGRA186_CLK_DTV_INPUT
15 * @def TEGRA186_CLK_SOR0_PAD_CLKOUT
16 * @def TEGRA186_CLK_SOR1_PAD_CLKOUT
17 * @def TEGRA186_CLK_I2S1_SYNC_INPUT
18 * @def TEGRA186_CLK_I2S2_SYNC_INPUT
19 * @def TEGRA186_CLK_I2S3_SYNC_INPUT
20 * @def TEGRA186_CLK_I2S4_SYNC_INPUT
21 * @def TEGRA186_CLK_I2S5_SYNC_INPUT
22 * @def TEGRA186_CLK_I2S6_SYNC_INPUT
23 * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT
24 * @}
25 *
26 * @defgroup extern_output external output clocks
27 * @{
28 * @def TEGRA186_CLK_EXTPERIPH1
29 * @def TEGRA186_CLK_EXTPERIPH2
30 * @def TEGRA186_CLK_EXTPERIPH3
31 * @def TEGRA186_CLK_EXTPERIPH4
32 * @}
33 *
34 * @defgroup display_clks display related clocks
35 * @{
36 * @def TEGRA186_CLK_CEC
37 * @def TEGRA186_CLK_DSIC
38 * @def TEGRA186_CLK_DSIC_LP
39 * @def TEGRA186_CLK_DSID
40 * @def TEGRA186_CLK_DSID_LP
41 * @def TEGRA186_CLK_DPAUX1
42 * @def TEGRA186_CLK_DPAUX
43 * @def TEGRA186_CLK_HDA2HDMICODEC
44 * @def TEGRA186_CLK_NVDISPLAY_DISP
45 * @def TEGRA186_CLK_NVDISPLAY_DSC
46 * @def TEGRA186_CLK_NVDISPLAY_P0
47 * @def TEGRA186_CLK_NVDISPLAY_P1
48 * @def TEGRA186_CLK_NVDISPLAY_P2
49 * @def TEGRA186_CLK_NVDISPLAYHUB
50 * @def TEGRA186_CLK_SOR_SAFE
51 * @def TEGRA186_CLK_SOR0
52 * @def TEGRA186_CLK_SOR0_OUT
53 * @def TEGRA186_CLK_SOR1
54 * @def TEGRA186_CLK_SOR1_OUT
55 * @def TEGRA186_CLK_DSI
56 * @def TEGRA186_CLK_MIPI_CAL
57 * @def TEGRA186_CLK_DSIA_LP
58 * @def TEGRA186_CLK_DSIB
59 * @def TEGRA186_CLK_DSIB_LP
60 * @}
61 *
62 * @defgroup camera_clks camera related clocks
63 * @{
64 * @def TEGRA186_CLK_NVCSI
65 * @def TEGRA186_CLK_NVCSILP
66 * @def TEGRA186_CLK_VI
67 * @}
68 *
69 * @defgroup audio_clks audio related clocks
70 * @{
71 * @def TEGRA186_CLK_ACLK
72 * @def TEGRA186_CLK_ADSP
73 * @def TEGRA186_CLK_ADSPNEON
74 * @def TEGRA186_CLK_AHUB
75 * @def TEGRA186_CLK_APE
76 * @def TEGRA186_CLK_APB2APE
77 * @def TEGRA186_CLK_AUD_MCLK
78 * @def TEGRA186_CLK_DMIC1
79 * @def TEGRA186_CLK_DMIC2
80 * @def TEGRA186_CLK_DMIC3
81 * @def TEGRA186_CLK_DMIC4
82 * @def TEGRA186_CLK_DSPK1
83 * @def TEGRA186_CLK_DSPK2
84 * @def TEGRA186_CLK_HDA
85 * @def TEGRA186_CLK_HDA2CODEC_2X
86 * @def TEGRA186_CLK_I2S1
87 * @def TEGRA186_CLK_I2S2
88 * @def TEGRA186_CLK_I2S3
89 * @def TEGRA186_CLK_I2S4
90 * @def TEGRA186_CLK_I2S5
91 * @def TEGRA186_CLK_I2S6
92 * @def TEGRA186_CLK_MAUD
93 * @def TEGRA186_CLK_PLL_A_OUT0
94 * @def TEGRA186_CLK_SPDIF_DOUBLER
95 * @def TEGRA186_CLK_SPDIF_IN
96 * @def TEGRA186_CLK_SPDIF_OUT
97 * @def TEGRA186_CLK_SYNC_DMIC1
98 * @def TEGRA186_CLK_SYNC_DMIC2
99 * @def TEGRA186_CLK_SYNC_DMIC3
100 * @def TEGRA186_CLK_SYNC_DMIC4
101 * @def TEGRA186_CLK_SYNC_DMIC5
102 * @def TEGRA186_CLK_SYNC_DSPK1
103 * @def TEGRA186_CLK_SYNC_DSPK2
104 * @def TEGRA186_CLK_SYNC_I2S1
105 * @def TEGRA186_CLK_SYNC_I2S2
106 * @def TEGRA186_CLK_SYNC_I2S3
107 * @def TEGRA186_CLK_SYNC_I2S4
108 * @def TEGRA186_CLK_SYNC_I2S5
109 * @def TEGRA186_CLK_SYNC_I2S6
110 * @def TEGRA186_CLK_SYNC_SPDIF
111 * @}
112 *
113 * @defgroup uart_clks UART clocks
114 * @{
115 * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL
116 * @def TEGRA186_CLK_UARTA
117 * @def TEGRA186_CLK_UARTB
118 * @def TEGRA186_CLK_UARTC
119 * @def TEGRA186_CLK_UARTD
120 * @def TEGRA186_CLK_UARTE
121 * @def TEGRA186_CLK_UARTF
122 * @def TEGRA186_CLK_UARTG
123 * @def TEGRA186_CLK_UART_FST_MIPI_CAL
124 * @}
125 *
126 * @defgroup i2c_clks I2C clocks
127 * @{
128 * @def TEGRA186_CLK_AON_I2C_SLOW
129 * @def TEGRA186_CLK_I2C1
130 * @def TEGRA186_CLK_I2C2
131 * @def TEGRA186_CLK_I2C3
132 * @def TEGRA186_CLK_I2C4
133 * @def TEGRA186_CLK_I2C5
134 * @def TEGRA186_CLK_I2C6
135 * @def TEGRA186_CLK_I2C8
136 * @def TEGRA186_CLK_I2C9
137 * @def TEGRA186_CLK_I2C1
138 * @def TEGRA186_CLK_I2C12
139 * @def TEGRA186_CLK_I2C13
140 * @def TEGRA186_CLK_I2C14
141 * @def TEGRA186_CLK_I2C_SLOW
142 * @def TEGRA186_CLK_VI_I2C
143 * @}
144 *
145 * @defgroup spi_clks SPI clocks
146 * @{
147 * @def TEGRA186_CLK_SPI1
148 * @def TEGRA186_CLK_SPI2
149 * @def TEGRA186_CLK_SPI3
150 * @def TEGRA186_CLK_SPI4
151 * @}
152 *
153 * @defgroup storage storage related clocks
154 * @{
155 * @def TEGRA186_CLK_SATA
156 * @def TEGRA186_CLK_SATA_OOB
157 * @def TEGRA186_CLK_SATA_IOBIST
158 * @def TEGRA186_CLK_SDMMC_LEGACY_TM
159 * @def TEGRA186_CLK_SDMMC1
160 * @def TEGRA186_CLK_SDMMC2
161 * @def TEGRA186_CLK_SDMMC3
162 * @def TEGRA186_CLK_SDMMC4
163 * @def TEGRA186_CLK_QSPI
164 * @def TEGRA186_CLK_QSPI_OUT
165 * @def TEGRA186_CLK_UFSDEV_REF
166 * @def TEGRA186_CLK_UFSHC
167 * @}
168 *
169 * @defgroup pwm_clks PWM clocks
170 * @{
171 * @def TEGRA186_CLK_PWM1
172 * @def TEGRA186_CLK_PWM2
173 * @def TEGRA186_CLK_PWM3
174 * @def TEGRA186_CLK_PWM4
175 * @def TEGRA186_CLK_PWM5
176 * @def TEGRA186_CLK_PWM6
177 * @def TEGRA186_CLK_PWM7
178 * @def TEGRA186_CLK_PWM8
179 * @}
180 *
181 * @defgroup plls PLLs and related clocks
182 * @{
183 * @def TEGRA186_CLK_PLLREFE_OUT_GATED
184 * @def TEGRA186_CLK_PLLREFE_OUT1
185 * @def TEGRA186_CLK_PLLD_OUT1
186 * @def TEGRA186_CLK_PLLP_OUT0
187 * @def TEGRA186_CLK_PLLP_OUT5
188 * @def TEGRA186_CLK_PLLA
189 * @def TEGRA186_CLK_PLLE_PWRSEQ
190 * @def TEGRA186_CLK_PLLA_OUT1
191 * @def TEGRA186_CLK_PLLREFE_REF
192 * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ
193 * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ
194 * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
195 * @def TEGRA186_CLK_PLLREFE_PEX
196 * @def TEGRA186_CLK_PLLREFE_IDDQ
197 * @def TEGRA186_CLK_PLLC_OUT_AON
198 * @def TEGRA186_CLK_PLLC_OUT_ISP
199 * @def TEGRA186_CLK_PLLC_OUT_VE
200 * @def TEGRA186_CLK_PLLC4_OUT
201 * @def TEGRA186_CLK_PLLREFE_OUT
202 * @def TEGRA186_CLK_PLLREFE_PLL_REF
203 * @def TEGRA186_CLK_PLLE
204 * @def TEGRA186_CLK_PLLC
205 * @def TEGRA186_CLK_PLLP
206 * @def TEGRA186_CLK_PLLD
207 * @def TEGRA186_CLK_PLLD2
208 * @def TEGRA186_CLK_PLLREFE_VCO
209 * @def TEGRA186_CLK_PLLC2
210 * @def TEGRA186_CLK_PLLC3
211 * @def TEGRA186_CLK_PLLDP
212 * @def TEGRA186_CLK_PLLC4_VCO
213 * @def TEGRA186_CLK_PLLA1
214 * @def TEGRA186_CLK_PLLNVCSI
215 * @def TEGRA186_CLK_PLLDISPHUB
216 * @def TEGRA186_CLK_PLLD3
217 * @def TEGRA186_CLK_PLLBPMPCAM
218 * @def TEGRA186_CLK_PLLAON
219 * @def TEGRA186_CLK_PLLU
220 * @def TEGRA186_CLK_PLLC4_VCO_DIV2
221 * @def TEGRA186_CLK_PLL_REF
222 * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5
223 * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ
224 * @def TEGRA186_CLK_PLL_U_48M
225 * @def TEGRA186_CLK_PLL_U_480M
226 * @def TEGRA186_CLK_PLLC4_OUT0
227 * @def TEGRA186_CLK_PLLC4_OUT1
228 * @def TEGRA186_CLK_PLLC4_OUT2
229 * @def TEGRA186_CLK_PLLC4_OUT_MUX
230 * @def TEGRA186_CLK_DFLLDISP_DIV
231 * @def TEGRA186_CLK_PLLDISPHUB_DIV
232 * @def TEGRA186_CLK_PLLP_DIV8
233 * @}
234 *
235 * @defgroup nafll_clks NAFLL clock sources
236 * @{
237 * @def TEGRA186_CLK_NAFLL_AXI_CBB
238 * @def TEGRA186_CLK_NAFLL_BCPU
239 * @def TEGRA186_CLK_NAFLL_BPMP
240 * @def TEGRA186_CLK_NAFLL_DISP
241 * @def TEGRA186_CLK_NAFLL_GPU
242 * @def TEGRA186_CLK_NAFLL_ISP
243 * @def TEGRA186_CLK_NAFLL_MCPU
244 * @def TEGRA186_CLK_NAFLL_NVDEC
245 * @def TEGRA186_CLK_NAFLL_NVENC
246 * @def TEGRA186_CLK_NAFLL_NVJPG
247 * @def TEGRA186_CLK_NAFLL_SCE
248 * @def TEGRA186_CLK_NAFLL_SE
249 * @def TEGRA186_CLK_NAFLL_TSEC
250 * @def TEGRA186_CLK_NAFLL_TSECB
251 * @def TEGRA186_CLK_NAFLL_VI
252 * @def TEGRA186_CLK_NAFLL_VIC
253 * @}
254 *
255 * @defgroup mphy MPHY related clocks
256 * @{
257 * @def TEGRA186_CLK_MPHY_L0_RX_SYMB
258 * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT
259 * @def TEGRA186_CLK_MPHY_L0_TX_SYMB
260 * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
261 * @def TEGRA186_CLK_MPHY_L0_RX_ANA
262 * @def TEGRA186_CLK_MPHY_L1_RX_ANA
263 * @def TEGRA186_CLK_MPHY_IOBIST
264 * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF
265 * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED
266 * @}
267 *
268 * @defgroup eavb EAVB related clocks
269 * @{
270 * @def TEGRA186_CLK_EQOS_AXI
271 * @def TEGRA186_CLK_EQOS_PTP_REF
272 * @def TEGRA186_CLK_EQOS_RX
273 * @def TEGRA186_CLK_EQOS_RX_INPUT
274 * @def TEGRA186_CLK_EQOS_TX
275 * @}
276 *
277 * @defgroup usb USB related clocks
278 * @{
279 * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT
280 * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT
281 * @def TEGRA186_CLK_HSIC_TRK
282 * @def TEGRA186_CLK_USB2_TRK
283 * @def TEGRA186_CLK_USB2_HSIC_TRK
284 * @def TEGRA186_CLK_XUSB_CORE_SS
285 * @def TEGRA186_CLK_XUSB_CORE_DEV
286 * @def TEGRA186_CLK_XUSB_FALCON
287 * @def TEGRA186_CLK_XUSB_FS
288 * @def TEGRA186_CLK_XUSB
289 * @def TEGRA186_CLK_XUSB_DEV
290 * @def TEGRA186_CLK_XUSB_HOST
291 * @def TEGRA186_CLK_XUSB_SS
292 * @}
293 *
294 * @defgroup bigblock compute block related clocks
295 * @{
296 * @def TEGRA186_CLK_GPCCLK
297 * @def TEGRA186_CLK_GPC2CLK
298 * @def TEGRA186_CLK_GPU
299 * @def TEGRA186_CLK_HOST1X
300 * @def TEGRA186_CLK_ISP
301 * @def TEGRA186_CLK_NVDEC
302 * @def TEGRA186_CLK_NVENC
303 * @def TEGRA186_CLK_NVJPG
304 * @def TEGRA186_CLK_SE
305 * @def TEGRA186_CLK_TSEC
306 * @def TEGRA186_CLK_TSECB
307 * @def TEGRA186_CLK_VIC
308 * @}
309 *
310 * @defgroup can CAN bus related clocks
311 * @{
312 * @def TEGRA186_CLK_CAN1
313 * @def TEGRA186_CLK_CAN1_HOST
314 * @def TEGRA186_CLK_CAN2
315 * @def TEGRA186_CLK_CAN2_HOST
316 * @}
317 *
318 * @defgroup system basic system clocks
319 * @{
320 * @def TEGRA186_CLK_ACTMON
321 * @def TEGRA186_CLK_AON_APB
322 * @def TEGRA186_CLK_AON_CPU_NIC
323 * @def TEGRA186_CLK_AON_NIC
324 * @def TEGRA186_CLK_AXI_CBB
325 * @def TEGRA186_CLK_BPMP_APB
326 * @def TEGRA186_CLK_BPMP_CPU_NIC
327 * @def TEGRA186_CLK_BPMP_NIC_RATE
328 * @def TEGRA186_CLK_CLK_M
329 * @def TEGRA186_CLK_EMC
330 * @def TEGRA186_CLK_MSS_ENCRYPT
331 * @def TEGRA186_CLK_SCE_APB
332 * @def TEGRA186_CLK_SCE_CPU_NIC
333 * @def TEGRA186_CLK_SCE_NIC
334 * @def TEGRA186_CLK_TSC
335 * @}
336 *
337 * @defgroup pcie_clks PCIe related clocks
338 * @{
339 * @def TEGRA186_CLK_AFI
340 * @def TEGRA186_CLK_PCIE
341 * @def TEGRA186_CLK_PCIE2_IOBIST
342 * @def TEGRA186_CLK_PCIERX0
343 * @def TEGRA186_CLK_PCIERX1
344 * @def TEGRA186_CLK_PCIERX2
345 * @def TEGRA186_CLK_PCIERX3
346 * @def TEGRA186_CLK_PCIERX4
347 * @}
348 */
349
350 /** @brief output of gate CLK_ENB_FUSE */
351 #define TEGRA186_CLK_FUSE 0
352 /**
353 * @brief It's not what you think
354 * @details output of gate CLK_ENB_GPU. This output connects to the GPU
355 * pwrclk. @warning: This is almost certainly not the clock you think
356 * it is. If you're looking for the clock of the graphics engine, see
357 * TEGRA186_GPCCLK
358 */
359 #define TEGRA186_CLK_GPU 1
360 /** @brief output of gate CLK_ENB_PCIE */
361 #define TEGRA186_CLK_PCIE 3
362 /** @brief output of the divider IPFS_CLK_DIVISOR */
363 #define TEGRA186_CLK_AFI 4
364 /** @brief output of gate CLK_ENB_PCIE2_IOBIST */
365 #define TEGRA186_CLK_PCIE2_IOBIST 5
366 /** @brief output of gate CLK_ENB_PCIERX0*/
367 #define TEGRA186_CLK_PCIERX0 6
368 /** @brief output of gate CLK_ENB_PCIERX1*/
369 #define TEGRA186_CLK_PCIERX1 7
370 /** @brief output of gate CLK_ENB_PCIERX2*/
371 #define TEGRA186_CLK_PCIERX2 8
372 /** @brief output of gate CLK_ENB_PCIERX3*/
373 #define TEGRA186_CLK_PCIERX3 9
374 /** @brief output of gate CLK_ENB_PCIERX4*/
375 #define TEGRA186_CLK_PCIERX4 10
376 /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
377 #define TEGRA186_CLK_PLLC_OUT_ISP 11
378 /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
379 #define TEGRA186_CLK_PLLC_OUT_VE 12
380 /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
381 #define TEGRA186_CLK_PLLC_OUT_AON 13
382 /** @brief output of gate CLK_ENB_SOR_SAFE */
383 #define TEGRA186_CLK_SOR_SAFE 39
384 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
385 #define TEGRA186_CLK_I2S2 42
386 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
387 #define TEGRA186_CLK_I2S3 43
388 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
389 #define TEGRA186_CLK_SPDIF_IN 44
390 /** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
391 #define TEGRA186_CLK_SPDIF_DOUBLER 45
392 /** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
393 #define TEGRA186_CLK_SPI3 46
394 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
395 #define TEGRA186_CLK_I2C1 47
396 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
397 #define TEGRA186_CLK_I2C5 48
398 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
399 #define TEGRA186_CLK_SPI1 49
400 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
401 #define TEGRA186_CLK_ISP 50
402 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
403 #define TEGRA186_CLK_VI 51
404 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
405 #define TEGRA186_CLK_SDMMC1 52
406 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
407 #define TEGRA186_CLK_SDMMC2 53
408 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
409 #define TEGRA186_CLK_SDMMC4 54
410 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
411 #define TEGRA186_CLK_UARTA 55
412 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
413 #define TEGRA186_CLK_UARTB 56
414 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
415 #define TEGRA186_CLK_HOST1X 57
416 /**
417 * @brief controls the EMC clock frequency.
418 * @details Doing a clk_set_rate on this clock will select the
419 * appropriate clock source, program the source rate and execute a
420 * specific sequence to switch to the new clock source for both memory
421 * controllers. This can be used to control the balance between memory
422 * throughput and memory controller power.
423 */
424 #define TEGRA186_CLK_EMC 58
425 /* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
426 #define TEGRA186_CLK_EXTPERIPH4 73
427 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
428 #define TEGRA186_CLK_SPI4 74
429 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
430 #define TEGRA186_CLK_I2C3 75
431 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
432 #define TEGRA186_CLK_SDMMC3 76
433 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
434 #define TEGRA186_CLK_UARTD 77
435 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
436 #define TEGRA186_CLK_I2S1 79
437 /** output of gate CLK_ENB_DTV */
438 #define TEGRA186_CLK_DTV 80
439 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
440 #define TEGRA186_CLK_TSEC 81
441 /** @brief output of gate CLK_ENB_DP2 */
442 #define TEGRA186_CLK_DP2 82
443 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
444 #define TEGRA186_CLK_I2S4 84
445 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
446 #define TEGRA186_CLK_I2S5 85
447 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
448 #define TEGRA186_CLK_I2C4 86
449 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
450 #define TEGRA186_CLK_AHUB 87
451 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
452 #define TEGRA186_CLK_HDA2CODEC_2X 88
453 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
454 #define TEGRA186_CLK_EXTPERIPH1 89
455 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
456 #define TEGRA186_CLK_EXTPERIPH2 90
457 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
458 #define TEGRA186_CLK_EXTPERIPH3 91
459 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
460 #define TEGRA186_CLK_I2C_SLOW 92
461 /** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
462 #define TEGRA186_CLK_SOR1 93
463 /** @brief output of gate CLK_ENB_CEC */
464 #define TEGRA186_CLK_CEC 94
465 /** @brief output of gate CLK_ENB_DPAUX1 */
466 #define TEGRA186_CLK_DPAUX1 95
467 /** @brief output of gate CLK_ENB_DPAUX */
468 #define TEGRA186_CLK_DPAUX 96
469 /** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
470 #define TEGRA186_CLK_SOR0 97
471 /** @brief output of gate CLK_ENB_HDA2HDMICODEC */
472 #define TEGRA186_CLK_HDA2HDMICODEC 98
473 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
474 #define TEGRA186_CLK_SATA 99
475 /** @brief output of gate CLK_ENB_SATA_OOB */
476 #define TEGRA186_CLK_SATA_OOB 100
477 /** @brief output of gate CLK_ENB_SATA_IOBIST */
478 #define TEGRA186_CLK_SATA_IOBIST 101
479 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
480 #define TEGRA186_CLK_HDA 102
481 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
482 #define TEGRA186_CLK_SE 103
483 /** @brief output of gate CLK_ENB_APB2APE */
484 #define TEGRA186_CLK_APB2APE 104
485 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
486 #define TEGRA186_CLK_APE 105
487 /** @brief output of gate CLK_ENB_IQC1 */
488 #define TEGRA186_CLK_IQC1 106
489 /** @brief output of gate CLK_ENB_IQC2 */
490 #define TEGRA186_CLK_IQC2 107
491 /** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */
492 #define TEGRA186_CLK_PLLREFE_OUT 108
493 /** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
494 #define TEGRA186_CLK_PLLREFE_PLL_REF 109
495 /** @brief output of gate CLK_ENB_PLLC4_OUT */
496 #define TEGRA186_CLK_PLLC4_OUT 110
497 /** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */
498 #define TEGRA186_CLK_XUSB 111
499 /** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */
500 #define TEGRA186_CLK_XUSB_DEV 112
501 /** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */
502 #define TEGRA186_CLK_XUSB_HOST 113
503 /** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */
504 #define TEGRA186_CLK_XUSB_SS 114
505 /** @brief output of gate CLK_ENB_DSI */
506 #define TEGRA186_CLK_DSI 115
507 /** @brief output of gate CLK_ENB_MIPI_CAL */
508 #define TEGRA186_CLK_MIPI_CAL 116
509 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
510 #define TEGRA186_CLK_DSIA_LP 117
511 /** @brief output of gate CLK_ENB_DSIB */
512 #define TEGRA186_CLK_DSIB 118
513 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
514 #define TEGRA186_CLK_DSIB_LP 119
515 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
516 #define TEGRA186_CLK_DMIC1 122
517 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
518 #define TEGRA186_CLK_DMIC2 123
519 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
520 #define TEGRA186_CLK_AUD_MCLK 124
521 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
522 #define TEGRA186_CLK_I2C6 125
523 /**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
524 #define TEGRA186_CLK_UART_FST_MIPI_CAL 126
525 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
526 #define TEGRA186_CLK_VIC 127
527 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
528 #define TEGRA186_CLK_SDMMC_LEGACY_TM 128
529 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
530 #define TEGRA186_CLK_NVDEC 129
531 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
532 #define TEGRA186_CLK_NVJPG 130
533 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
534 #define TEGRA186_CLK_NVENC 131
535 /** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
536 #define TEGRA186_CLK_QSPI 132
537 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
538 #define TEGRA186_CLK_VI_I2C 133
539 /** @brief output of gate CLK_ENB_HSIC_TRK */
540 #define TEGRA186_CLK_HSIC_TRK 134
541 /** @brief output of gate CLK_ENB_USB2_TRK */
542 #define TEGRA186_CLK_USB2_TRK 135
543 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
544 #define TEGRA186_CLK_MAUD 136
545 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
546 #define TEGRA186_CLK_TSECB 137
547 /** @brief output of gate CLK_ENB_ADSP */
548 #define TEGRA186_CLK_ADSP 138
549 /** @brief output of gate CLK_ENB_ADSPNEON */
550 #define TEGRA186_CLK_ADSPNEON 139
551 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
552 #define TEGRA186_CLK_MPHY_L0_RX_SYMB 140
553 /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
554 #define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141
555 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
556 #define TEGRA186_CLK_MPHY_L0_TX_SYMB 142
557 /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
558 #define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143
559 /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
560 #define TEGRA186_CLK_MPHY_L0_RX_ANA 144
561 /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
562 #define TEGRA186_CLK_MPHY_L1_RX_ANA 145
563 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
564 #define TEGRA186_CLK_MPHY_IOBIST 146
565 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
566 #define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147
567 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
568 #define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148
569 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
570 #define TEGRA186_CLK_AXI_CBB 149
571 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
572 #define TEGRA186_CLK_DMIC3 150
573 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
574 #define TEGRA186_CLK_DMIC4 151
575 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
576 #define TEGRA186_CLK_DSPK1 152
577 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
578 #define TEGRA186_CLK_DSPK2 153
579 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
580 #define TEGRA186_CLK_I2S6 154
581 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
582 #define TEGRA186_CLK_NVDISPLAY_P0 155
583 /** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */
584 #define TEGRA186_CLK_NVDISPLAY_DISP 156
585 /** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
586 #define TEGRA186_CLK_NVDISPLAY_DSC 157
587 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
588 #define TEGRA186_CLK_NVDISPLAYHUB 158
589 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
590 #define TEGRA186_CLK_NVDISPLAY_P1 159
591 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
592 #define TEGRA186_CLK_NVDISPLAY_P2 160
593 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
594 #define TEGRA186_CLK_TACH 166
595 /** @brief output of gate CLK_ENB_EQOS */
596 #define TEGRA186_CLK_EQOS_AXI 167
597 /** @brief output of gate CLK_ENB_EQOS_RX */
598 #define TEGRA186_CLK_EQOS_RX 168
599 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
600 #define TEGRA186_CLK_UFSHC 178
601 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
602 #define TEGRA186_CLK_UFSDEV_REF 179
603 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
604 #define TEGRA186_CLK_NVCSI 180
605 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
606 #define TEGRA186_CLK_NVCSILP 181
607 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
608 #define TEGRA186_CLK_I2C7 182
609 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
610 #define TEGRA186_CLK_I2C9 183
611 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
612 #define TEGRA186_CLK_I2C12 184
613 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
614 #define TEGRA186_CLK_I2C13 185
615 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
616 #define TEGRA186_CLK_I2C14 186
617 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
618 #define TEGRA186_CLK_PWM1 187
619 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
620 #define TEGRA186_CLK_PWM2 188
621 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
622 #define TEGRA186_CLK_PWM3 189
623 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
624 #define TEGRA186_CLK_PWM5 190
625 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
626 #define TEGRA186_CLK_PWM6 191
627 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
628 #define TEGRA186_CLK_PWM7 192
629 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
630 #define TEGRA186_CLK_PWM8 193
631 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
632 #define TEGRA186_CLK_UARTE 194
633 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
634 #define TEGRA186_CLK_UARTF 195
635 /** @deprecated */
636 #define TEGRA186_CLK_DBGAPB 196
637 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
638 #define TEGRA186_CLK_BPMP_CPU_NIC 197
639 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
640 #define TEGRA186_CLK_BPMP_APB 199
641 /** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
642 #define TEGRA186_CLK_ACTMON 201
643 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
644 #define TEGRA186_CLK_AON_CPU_NIC 208
645 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
646 #define TEGRA186_CLK_CAN1 210
647 /** @brief output of gate CLK_ENB_CAN1_HOST */
648 #define TEGRA186_CLK_CAN1_HOST 211
649 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
650 #define TEGRA186_CLK_CAN2 212
651 /** @brief output of gate CLK_ENB_CAN2_HOST */
652 #define TEGRA186_CLK_CAN2_HOST 213
653 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
654 #define TEGRA186_CLK_AON_APB 214
655 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
656 #define TEGRA186_CLK_UARTC 215
657 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
658 #define TEGRA186_CLK_UARTG 216
659 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
660 #define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217
661 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
662 #define TEGRA186_CLK_I2C2 218
663 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
664 #define TEGRA186_CLK_I2C8 219
665 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
666 #define TEGRA186_CLK_I2C10 220
667 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
668 #define TEGRA186_CLK_AON_I2C_SLOW 221
669 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
670 #define TEGRA186_CLK_SPI2 222
671 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
672 #define TEGRA186_CLK_DMIC5 223
673 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
674 #define TEGRA186_CLK_AON_TOUCH 224
675 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
676 #define TEGRA186_CLK_PWM4 225
677 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */
678 #define TEGRA186_CLK_TSC 226
679 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
680 #define TEGRA186_CLK_MSS_ENCRYPT 227
681 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
682 #define TEGRA186_CLK_SCE_CPU_NIC 228
683 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
684 #define TEGRA186_CLK_SCE_APB 230
685 /** @brief output of gate CLK_ENB_DSIC */
686 #define TEGRA186_CLK_DSIC 231
687 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
688 #define TEGRA186_CLK_DSIC_LP 232
689 /** @brief output of gate CLK_ENB_DSID */
690 #define TEGRA186_CLK_DSID 233
691 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
692 #define TEGRA186_CLK_DSID_LP 234
693 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
694 #define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236
695 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
696 #define TEGRA186_CLK_SPDIF_OUT 238
697 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
698 #define TEGRA186_CLK_EQOS_PTP_REF 239
699 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
700 #define TEGRA186_CLK_EQOS_TX 240
701 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
702 #define TEGRA186_CLK_USB2_HSIC_TRK 241
703 /** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */
704 #define TEGRA186_CLK_XUSB_CORE_SS 242
705 /** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */
706 #define TEGRA186_CLK_XUSB_CORE_DEV 243
707 /** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */
708 #define TEGRA186_CLK_XUSB_FALCON 244
709 /** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */
710 #define TEGRA186_CLK_XUSB_FS 245
711 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
712 #define TEGRA186_CLK_PLL_A_OUT0 246
713 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
714 #define TEGRA186_CLK_SYNC_I2S1 247
715 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
716 #define TEGRA186_CLK_SYNC_I2S2 248
717 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
718 #define TEGRA186_CLK_SYNC_I2S3 249
719 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
720 #define TEGRA186_CLK_SYNC_I2S4 250
721 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
722 #define TEGRA186_CLK_SYNC_I2S5 251
723 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
724 #define TEGRA186_CLK_SYNC_I2S6 252
725 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
726 #define TEGRA186_CLK_SYNC_DSPK1 253
727 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
728 #define TEGRA186_CLK_SYNC_DSPK2 254
729 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
730 #define TEGRA186_CLK_SYNC_DMIC1 255
731 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
732 #define TEGRA186_CLK_SYNC_DMIC2 256
733 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
734 #define TEGRA186_CLK_SYNC_DMIC3 257
735 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
736 #define TEGRA186_CLK_SYNC_DMIC4 259
737 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
738 #define TEGRA186_CLK_SYNC_SPDIF 260
739 /** @brief output of gate CLK_ENB_PLLREFE_OUT */
740 #define TEGRA186_CLK_PLLREFE_OUT_GATED 261
741 /** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs:
742 * * VCO/pdiv defined by this clock object
743 * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT
744 */
745 #define TEGRA186_CLK_PLLREFE_OUT1 262
746 #define TEGRA186_CLK_PLLD_OUT1 267
747 /** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
748 #define TEGRA186_CLK_PLLP_OUT0 269
749 /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
750 #define TEGRA186_CLK_PLLP_OUT5 270
751 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
752 #define TEGRA186_CLK_PLLA 271
753 /** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */
754 #define TEGRA186_CLK_ACLK 273
755 /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
756 #define TEGRA186_CLK_PLL_U_48M 274
757 /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
758 #define TEGRA186_CLK_PLL_U_480M 275
759 /** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */
760 #define TEGRA186_CLK_PLLC4_OUT0 276
761 /** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
762 #define TEGRA186_CLK_PLLC4_OUT1 277
763 /** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
764 #define TEGRA186_CLK_PLLC4_OUT2 278
765 /** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
766 #define TEGRA186_CLK_PLLC4_OUT_MUX 279
767 /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
768 #define TEGRA186_CLK_DFLLDISP_DIV 284
769 /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
770 #define TEGRA186_CLK_PLLDISPHUB_DIV 285
771 /** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */
772 #define TEGRA186_CLK_PLLP_DIV8 286
773 /** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
774 #define TEGRA186_CLK_BPMP_NIC 287
775 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
776 #define TEGRA186_CLK_PLL_A_OUT1 288
777 /** @deprecated */
778 #define TEGRA186_CLK_GPC2CLK 289
779 /** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */
780 #define TEGRA186_CLK_KFUSE 293
781 /**
782 * @brief controls the PLLE hardware sequencer.
783 * @details This clock only has enable and disable methods. When the
784 * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by
785 * hw based on the control signals from the PCIe, SATA and XUSB
786 * clocks. When the PLLE hw sequencer is disabled, the state of PLLE
787 * is controlled by sw using clk_enable/clk_disable on
788 * TEGRA186_CLK_PLLE.
789 */
790 #define TEGRA186_CLK_PLLE_PWRSEQ 294
791 /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
792 #define TEGRA186_CLK_PLLREFE_REF 295
793 /** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
794 #define TEGRA186_CLK_SOR0_OUT 296
795 /** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
796 #define TEGRA186_CLK_SOR1_OUT 297
797 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
798 #define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298
799 /** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */
800 #define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301
801 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
802 #define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302
803 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
804 #define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303
805 /** @brief controls the UPHY_PLL0 hardware sqeuencer */
806 #define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304
807 /** @brief controls the UPHY_PLL1 hardware sqeuencer */
808 #define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305
809 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
810 #define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306
811 /** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */
812 #define TEGRA186_CLK_PLLREFE_PEX 307
813 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */
814 #define TEGRA186_CLK_PLLREFE_IDDQ 308
815 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
816 #define TEGRA186_CLK_QSPI_OUT 309
817 /**
818 * @brief GPC2CLK-div-2
819 * @details fixed /2 divider. Output frequency is
820 * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
821 * frequency at which the GPU graphics engine runs. */
822 #define TEGRA186_CLK_GPCCLK 310
823 /** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
824 #define TEGRA186_CLK_AON_NIC 450
825 /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
826 #define TEGRA186_CLK_SCE_NIC 451
827 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
828 #define TEGRA186_CLK_PLLE 512
829 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
830 #define TEGRA186_CLK_PLLC 513
831 /** Fixed 408MHz PLL for use by peripheral clocks */
832 #define TEGRA186_CLK_PLLP 516
833 /** @deprecated */
834 #define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP
835 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
836 #define TEGRA186_CLK_PLLD 518
837 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
838 #define TEGRA186_CLK_PLLD2 519
839 /**
840 * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
841 * @details Note that this clock only controls the VCO output, before
842 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
843 * information.
844 */
845 #define TEGRA186_CLK_PLLREFE_VCO 520
846 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
847 #define TEGRA186_CLK_PLLC2 521
848 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
849 #define TEGRA186_CLK_PLLC3 522
850 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
851 #define TEGRA186_CLK_PLLDP 523
852 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
853 #define TEGRA186_CLK_PLLC4_VCO 524
854 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
855 #define TEGRA186_CLK_PLLA1 525
856 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
857 #define TEGRA186_CLK_PLLNVCSI 526
858 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
859 #define TEGRA186_CLK_PLLDISPHUB 527
860 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
861 #define TEGRA186_CLK_PLLD3 528
862 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
863 #define TEGRA186_CLK_PLLBPMPCAM 531
864 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
865 #define TEGRA186_CLK_PLLAON 532
866 /** Fixed frequency 960MHz PLL for USB and EAVB */
867 #define TEGRA186_CLK_PLLU 533
868 /** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
869 #define TEGRA186_CLK_PLLC4_VCO_DIV2 535
870 /** @brief NAFLL clock source for AXI_CBB */
871 #define TEGRA186_CLK_NAFLL_AXI_CBB 564
872 /** @brief NAFLL clock source for BPMP */
873 #define TEGRA186_CLK_NAFLL_BPMP 565
874 /** @brief NAFLL clock source for ISP */
875 #define TEGRA186_CLK_NAFLL_ISP 566
876 /** @brief NAFLL clock source for NVDEC */
877 #define TEGRA186_CLK_NAFLL_NVDEC 567
878 /** @brief NAFLL clock source for NVENC */
879 #define TEGRA186_CLK_NAFLL_NVENC 568
880 /** @brief NAFLL clock source for NVJPG */
881 #define TEGRA186_CLK_NAFLL_NVJPG 569
882 /** @brief NAFLL clock source for SCE */
883 #define TEGRA186_CLK_NAFLL_SCE 570
884 /** @brief NAFLL clock source for SE */
885 #define TEGRA186_CLK_NAFLL_SE 571
886 /** @brief NAFLL clock source for TSEC */
887 #define TEGRA186_CLK_NAFLL_TSEC 572
888 /** @brief NAFLL clock source for TSECB */
889 #define TEGRA186_CLK_NAFLL_TSECB 573
890 /** @brief NAFLL clock source for VI */
891 #define TEGRA186_CLK_NAFLL_VI 574
892 /** @brief NAFLL clock source for VIC */
893 #define TEGRA186_CLK_NAFLL_VIC 575
894 /** @brief NAFLL clock source for DISP */
895 #define TEGRA186_CLK_NAFLL_DISP 576
896 /** @brief NAFLL clock source for GPU */
897 #define TEGRA186_CLK_NAFLL_GPU 577
898 /** @brief NAFLL clock source for M-CPU cluster */
899 #define TEGRA186_CLK_NAFLL_MCPU 578
900 /** @brief NAFLL clock source for B-CPU cluster */
901 #define TEGRA186_CLK_NAFLL_BCPU 579
902 /** @brief input from Tegra's CLK_32K_IN pad */
903 #define TEGRA186_CLK_CLK_32K 608
904 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
905 #define TEGRA186_CLK_CLK_M 609
906 /** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
907 #define TEGRA186_CLK_PLL_REF 610
908 /** @brief input from Tegra's XTAL_IN */
909 #define TEGRA186_CLK_OSC 612
910 /** @brief clock recovered from EAVB input */
911 #define TEGRA186_CLK_EQOS_RX_INPUT 613
912 /** @brief clock recovered from DTV input */
913 #define TEGRA186_CLK_DTV_INPUT 614
914 /** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/
915 #define TEGRA186_CLK_SOR0_PAD_CLKOUT 615
916 /** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/
917 #define TEGRA186_CLK_SOR1_PAD_CLKOUT 616
918 /** @brief clock recovered from I2S1 input */
919 #define TEGRA186_CLK_I2S1_SYNC_INPUT 617
920 /** @brief clock recovered from I2S2 input */
921 #define TEGRA186_CLK_I2S2_SYNC_INPUT 618
922 /** @brief clock recovered from I2S3 input */
923 #define TEGRA186_CLK_I2S3_SYNC_INPUT 619
924 /** @brief clock recovered from I2S4 input */
925 #define TEGRA186_CLK_I2S4_SYNC_INPUT 620
926 /** @brief clock recovered from I2S5 input */
927 #define TEGRA186_CLK_I2S5_SYNC_INPUT 621
928 /** @brief clock recovered from I2S6 input */
929 #define TEGRA186_CLK_I2S6_SYNC_INPUT 622
930 /** @brief clock recovered from SPDIFIN input */
931 #define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623
932
933 /**
934 * @brief subject to change
935 * @details maximum clock identifier value plus one.
936 */
937 #define TEGRA186_CLK_CLK_MAX 624
938
939 /** @} */
940
941 #endif