1 /*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2000-2001 Toshiba Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32 #include <linux/init.h>
33 #include <linux/types.h>
34 #include <linux/interrupt.h>
35 #include <linux/irq.h>
36
37 #include <asm/io.h>
38 #include <asm/mipsregs.h>
39 #include <asm/txx9/generic.h>
40 #include <asm/txx9/jmr3927.h>
41
42 #if JMR3927_IRQ_END > NR_IRQS
43 #error JMR3927_IRQ_END > NR_IRQS
44 #endif
45
46 /*
47 * CP0_STATUS is a thread's resource (saved/restored on context switch).
48 * So disable_irq/enable_irq MUST handle IOC/IRC registers.
49 */
50 static void mask_irq_ioc(struct irq_data *d)
51 {
52 /* 0: mask */
53 unsigned int irq_nr = d->irq - JMR3927_IRQ_IOC;
54 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
55 unsigned int bit = 1 << irq_nr;
56 jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
57 /* flush write buffer */
58 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
59 }
60 static void unmask_irq_ioc(struct irq_data *d)
61 {
62 /* 0: mask */
63 unsigned int irq_nr = d->irq - JMR3927_IRQ_IOC;
64 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
65 unsigned int bit = 1 << irq_nr;
66 jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
67 /* flush write buffer */
68 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
69 }
70
71 static int jmr3927_ioc_irqroute(void)
72 {
73 unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
74 int i;
75
76 for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
77 if (istat & (1 << i))
78 return JMR3927_IRQ_IOC + i;
79 }
80 return -1;
81 }
82
83 static int jmr3927_irq_dispatch(int pending)
84 {
85 int irq;
86
87 if ((pending & CAUSEF_IP7) == 0)
88 return -1;
89 irq = (pending >> CAUSEB_IP2) & 0x0f;
90 irq += JMR3927_IRQ_IRC;
91 if (irq == JMR3927_IRQ_IOCINT)
92 irq = jmr3927_ioc_irqroute();
93 return irq;
94 }
95
96 static struct irq_chip jmr3927_irq_ioc = {
97 .name = "jmr3927_ioc",
98 .irq_mask = mask_irq_ioc,
99 .irq_unmask = unmask_irq_ioc,
100 };
101
102 void __init jmr3927_irq_setup(void)
103 {
104 int i;
105
106 txx9_irq_dispatch = jmr3927_irq_dispatch;
107 /* Now, interrupt control disabled, */
108 /* all IRC interrupts are masked, */
109 /* all IRC interrupt mode are Low Active. */
110
111 /* mask all IOC interrupts */
112 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
113 /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
114 jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
115
116 /* clear PCI Soft interrupts */
117 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
118 /* clear PCI Reset interrupts */
119 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
120
121 tx3927_irq_init();
122 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
123 irq_set_chip_and_handler(i, &jmr3927_irq_ioc,
124 handle_level_irq);
125
126 /* setup IOC interrupt 1 (PCI, MODEM) */
127 irq_set_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
128 }