root/scripts/dtc/include-prefixes/dt-bindings/clock/omap5.h

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INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright 2017 Texas Instruments, Inc.
   4  */
   5 #ifndef __DT_BINDINGS_CLK_OMAP5_H
   6 #define __DT_BINDINGS_CLK_OMAP5_H
   7 
   8 #define OMAP5_CLKCTRL_OFFSET    0x20
   9 #define OMAP5_CLKCTRL_INDEX(offset)     ((offset) - OMAP5_CLKCTRL_OFFSET)
  10 
  11 /* mpu clocks */
  12 #define OMAP5_MPU_CLKCTRL       OMAP5_CLKCTRL_INDEX(0x20)
  13 
  14 /* dsp clocks */
  15 #define OMAP5_MMU_DSP_CLKCTRL   OMAP5_CLKCTRL_INDEX(0x20)
  16 
  17 /* abe clocks */
  18 #define OMAP5_L4_ABE_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x20)
  19 #define OMAP5_MCPDM_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x30)
  20 #define OMAP5_DMIC_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x38)
  21 #define OMAP5_MCBSP1_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x48)
  22 #define OMAP5_MCBSP2_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x50)
  23 #define OMAP5_MCBSP3_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x58)
  24 #define OMAP5_TIMER5_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x68)
  25 #define OMAP5_TIMER6_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x70)
  26 #define OMAP5_TIMER7_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x78)
  27 #define OMAP5_TIMER8_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x80)
  28 
  29 /* l3main1 clocks */
  30 #define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  31 
  32 /* l3main2 clocks */
  33 #define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  34 
  35 /* ipu clocks */
  36 #define OMAP5_MMU_IPU_CLKCTRL   OMAP5_CLKCTRL_INDEX(0x20)
  37 
  38 /* dma clocks */
  39 #define OMAP5_DMA_SYSTEM_CLKCTRL        OMAP5_CLKCTRL_INDEX(0x20)
  40 
  41 /* emif clocks */
  42 #define OMAP5_DMM_CLKCTRL       OMAP5_CLKCTRL_INDEX(0x20)
  43 #define OMAP5_EMIF1_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x30)
  44 #define OMAP5_EMIF2_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x38)
  45 
  46 /* l4cfg clocks */
  47 #define OMAP5_L4_CFG_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x20)
  48 #define OMAP5_SPINLOCK_CLKCTRL  OMAP5_CLKCTRL_INDEX(0x28)
  49 #define OMAP5_MAILBOX_CLKCTRL   OMAP5_CLKCTRL_INDEX(0x30)
  50 
  51 /* l3instr clocks */
  52 #define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  53 #define OMAP5_L3_INSTR_CLKCTRL  OMAP5_CLKCTRL_INDEX(0x28)
  54 
  55 /* l4per clocks */
  56 #define OMAP5_TIMER10_CLKCTRL   OMAP5_CLKCTRL_INDEX(0x28)
  57 #define OMAP5_TIMER11_CLKCTRL   OMAP5_CLKCTRL_INDEX(0x30)
  58 #define OMAP5_TIMER2_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x38)
  59 #define OMAP5_TIMER3_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x40)
  60 #define OMAP5_TIMER4_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x48)
  61 #define OMAP5_TIMER9_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x50)
  62 #define OMAP5_GPIO2_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x60)
  63 #define OMAP5_GPIO3_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x68)
  64 #define OMAP5_GPIO4_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x70)
  65 #define OMAP5_GPIO5_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x78)
  66 #define OMAP5_GPIO6_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x80)
  67 #define OMAP5_I2C1_CLKCTRL      OMAP5_CLKCTRL_INDEX(0xa0)
  68 #define OMAP5_I2C2_CLKCTRL      OMAP5_CLKCTRL_INDEX(0xa8)
  69 #define OMAP5_I2C3_CLKCTRL      OMAP5_CLKCTRL_INDEX(0xb0)
  70 #define OMAP5_I2C4_CLKCTRL      OMAP5_CLKCTRL_INDEX(0xb8)
  71 #define OMAP5_L4_PER_CLKCTRL    OMAP5_CLKCTRL_INDEX(0xc0)
  72 #define OMAP5_MCSPI1_CLKCTRL    OMAP5_CLKCTRL_INDEX(0xf0)
  73 #define OMAP5_MCSPI2_CLKCTRL    OMAP5_CLKCTRL_INDEX(0xf8)
  74 #define OMAP5_MCSPI3_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x100)
  75 #define OMAP5_MCSPI4_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x108)
  76 #define OMAP5_GPIO7_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x110)
  77 #define OMAP5_GPIO8_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x118)
  78 #define OMAP5_MMC3_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x120)
  79 #define OMAP5_MMC4_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x128)
  80 #define OMAP5_UART1_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x140)
  81 #define OMAP5_UART2_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x148)
  82 #define OMAP5_UART3_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x150)
  83 #define OMAP5_UART4_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x158)
  84 #define OMAP5_MMC5_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x160)
  85 #define OMAP5_I2C5_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x168)
  86 #define OMAP5_UART5_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x170)
  87 #define OMAP5_UART6_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x178)
  88 
  89 /* dss clocks */
  90 #define OMAP5_DSS_CORE_CLKCTRL  OMAP5_CLKCTRL_INDEX(0x20)
  91 
  92 /* gpu clocks */
  93 #define OMAP5_GPU_CLKCTRL       OMAP5_CLKCTRL_INDEX(0x20)
  94 
  95 /* l3init clocks */
  96 #define OMAP5_MMC1_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x28)
  97 #define OMAP5_MMC2_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x30)
  98 #define OMAP5_USB_HOST_HS_CLKCTRL       OMAP5_CLKCTRL_INDEX(0x58)
  99 #define OMAP5_USB_TLL_HS_CLKCTRL        OMAP5_CLKCTRL_INDEX(0x68)
 100 #define OMAP5_SATA_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x88)
 101 #define OMAP5_OCP2SCP1_CLKCTRL  OMAP5_CLKCTRL_INDEX(0xe0)
 102 #define OMAP5_OCP2SCP3_CLKCTRL  OMAP5_CLKCTRL_INDEX(0xe8)
 103 #define OMAP5_USB_OTG_SS_CLKCTRL        OMAP5_CLKCTRL_INDEX(0xf0)
 104 
 105 /* wkupaon clocks */
 106 #define OMAP5_L4_WKUP_CLKCTRL   OMAP5_CLKCTRL_INDEX(0x20)
 107 #define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
 108 #define OMAP5_GPIO1_CLKCTRL     OMAP5_CLKCTRL_INDEX(0x38)
 109 #define OMAP5_TIMER1_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x40)
 110 #define OMAP5_COUNTER_32K_CLKCTRL       OMAP5_CLKCTRL_INDEX(0x50)
 111 #define OMAP5_KBD_CLKCTRL       OMAP5_CLKCTRL_INDEX(0x78)
 112 
 113 #endif
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