root/scripts/dtc/include-prefixes/dt-bindings/clock/tegra124-car-common.h

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INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * This header provides constants for binding nvidia,tegra124-car or
   4  * nvidia,tegra132-car.
   5  *
   6  * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
   7  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
   8  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
   9  * this case, those clocks are assigned IDs above 185 in order to highlight
  10  * this issue. Implementations that interpret these clock IDs as bit values
  11  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
  12  * explicitly handle these special cases.
  13  *
  14  * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
  15  * above.
  16  */
  17 
  18 #ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
  19 #define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
  20 
  21 /* 0 */
  22 /* 1 */
  23 /* 2 */
  24 #define TEGRA124_CLK_ISPB 3
  25 #define TEGRA124_CLK_RTC 4
  26 #define TEGRA124_CLK_TIMER 5
  27 #define TEGRA124_CLK_UARTA 6
  28 /* 7 (register bit affects uartb and vfir) */
  29 /* 8 */
  30 #define TEGRA124_CLK_SDMMC2 9
  31 /* 10 (register bit affects spdif_in and spdif_out) */
  32 #define TEGRA124_CLK_I2S1 11
  33 #define TEGRA124_CLK_I2C1 12
  34 /* 13 */
  35 #define TEGRA124_CLK_SDMMC1 14
  36 #define TEGRA124_CLK_SDMMC4 15
  37 /* 16 */
  38 #define TEGRA124_CLK_PWM 17
  39 #define TEGRA124_CLK_I2S2 18
  40 /* 20 (register bit affects vi and vi_sensor) */
  41 /* 21 */
  42 #define TEGRA124_CLK_USBD 22
  43 #define TEGRA124_CLK_ISP 23
  44 /* 26 */
  45 /* 25 */
  46 #define TEGRA124_CLK_DISP2 26
  47 #define TEGRA124_CLK_DISP1 27
  48 #define TEGRA124_CLK_HOST1X 28
  49 #define TEGRA124_CLK_VCP 29
  50 #define TEGRA124_CLK_I2S0 30
  51 /* 31 */
  52 
  53 #define TEGRA124_CLK_MC 32
  54 /* 33 */
  55 #define TEGRA124_CLK_APBDMA 34
  56 /* 35 */
  57 #define TEGRA124_CLK_KBC 36
  58 /* 37 */
  59 /* 38 */
  60 /* 39 (register bit affects fuse and fuse_burn) */
  61 #define TEGRA124_CLK_KFUSE 40
  62 #define TEGRA124_CLK_SBC1 41
  63 #define TEGRA124_CLK_NOR 42
  64 /* 43 */
  65 #define TEGRA124_CLK_SBC2 44
  66 /* 45 */
  67 #define TEGRA124_CLK_SBC3 46
  68 #define TEGRA124_CLK_I2C5 47
  69 #define TEGRA124_CLK_DSIA 48
  70 /* 49 */
  71 #define TEGRA124_CLK_MIPI 50
  72 #define TEGRA124_CLK_HDMI 51
  73 #define TEGRA124_CLK_CSI 52
  74 /* 53 */
  75 #define TEGRA124_CLK_I2C2 54
  76 #define TEGRA124_CLK_UARTC 55
  77 #define TEGRA124_CLK_MIPI_CAL 56
  78 #define TEGRA124_CLK_EMC 57
  79 #define TEGRA124_CLK_USB2 58
  80 #define TEGRA124_CLK_USB3 59
  81 /* 60 */
  82 #define TEGRA124_CLK_VDE 61
  83 #define TEGRA124_CLK_BSEA 62
  84 #define TEGRA124_CLK_BSEV 63
  85 
  86 /* 64 */
  87 #define TEGRA124_CLK_UARTD 65
  88 /* 66 */
  89 #define TEGRA124_CLK_I2C3 67
  90 #define TEGRA124_CLK_SBC4 68
  91 #define TEGRA124_CLK_SDMMC3 69
  92 #define TEGRA124_CLK_PCIE 70
  93 #define TEGRA124_CLK_OWR 71
  94 #define TEGRA124_CLK_AFI 72
  95 #define TEGRA124_CLK_CSITE 73
  96 /* 74 */
  97 /* 75 */
  98 #define TEGRA124_CLK_LA 76
  99 #define TEGRA124_CLK_TRACE 77
 100 #define TEGRA124_CLK_SOC_THERM 78
 101 #define TEGRA124_CLK_DTV 79
 102 /* 80 */
 103 #define TEGRA124_CLK_I2CSLOW 81
 104 #define TEGRA124_CLK_DSIB 82
 105 #define TEGRA124_CLK_TSEC 83
 106 /* 84 */
 107 /* 85 */
 108 /* 86 */
 109 /* 87 */
 110 /* 88 */
 111 #define TEGRA124_CLK_XUSB_HOST 89
 112 /* 90 */
 113 #define TEGRA124_CLK_MSENC 91
 114 #define TEGRA124_CLK_CSUS 92
 115 /* 93 */
 116 /* 94 */
 117 /* 95 (bit affects xusb_dev and xusb_dev_src) */
 118 
 119 /* 96 */
 120 /* 97 */
 121 /* 98 */
 122 #define TEGRA124_CLK_MSELECT 99
 123 #define TEGRA124_CLK_TSENSOR 100
 124 #define TEGRA124_CLK_I2S3 101
 125 #define TEGRA124_CLK_I2S4 102
 126 #define TEGRA124_CLK_I2C4 103
 127 #define TEGRA124_CLK_SBC5 104
 128 #define TEGRA124_CLK_SBC6 105
 129 #define TEGRA124_CLK_D_AUDIO 106
 130 #define TEGRA124_CLK_APBIF 107
 131 #define TEGRA124_CLK_DAM0 108
 132 #define TEGRA124_CLK_DAM1 109
 133 #define TEGRA124_CLK_DAM2 110
 134 #define TEGRA124_CLK_HDA2CODEC_2X 111
 135 /* 112 */
 136 #define TEGRA124_CLK_AUDIO0_2X 113
 137 #define TEGRA124_CLK_AUDIO1_2X 114
 138 #define TEGRA124_CLK_AUDIO2_2X 115
 139 #define TEGRA124_CLK_AUDIO3_2X 116
 140 #define TEGRA124_CLK_AUDIO4_2X 117
 141 #define TEGRA124_CLK_SPDIF_2X 118
 142 #define TEGRA124_CLK_ACTMON 119
 143 #define TEGRA124_CLK_EXTERN1 120
 144 #define TEGRA124_CLK_EXTERN2 121
 145 #define TEGRA124_CLK_EXTERN3 122
 146 #define TEGRA124_CLK_SATA_OOB 123
 147 #define TEGRA124_CLK_SATA 124
 148 #define TEGRA124_CLK_HDA 125
 149 /* 126 */
 150 #define TEGRA124_CLK_SE 127
 151 
 152 #define TEGRA124_CLK_HDA2HDMI 128
 153 #define TEGRA124_CLK_SATA_COLD 129
 154 /* 130 */
 155 /* 131 */
 156 /* 132 */
 157 /* 133 */
 158 /* 134 */
 159 /* 135 */
 160 #define TEGRA124_CLK_CEC 136
 161 /* 137 */
 162 /* 138 */
 163 /* 139 */
 164 /* 140 */
 165 /* 141 */
 166 /* 142 */
 167 /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
 168 /*      xusb_host_src and xusb_ss_src) */
 169 #define TEGRA124_CLK_CILAB 144
 170 #define TEGRA124_CLK_CILCD 145
 171 #define TEGRA124_CLK_CILE 146
 172 #define TEGRA124_CLK_DSIALP 147
 173 #define TEGRA124_CLK_DSIBLP 148
 174 #define TEGRA124_CLK_ENTROPY 149
 175 #define TEGRA124_CLK_DDS 150
 176 /* 151 */
 177 #define TEGRA124_CLK_DP2 152
 178 #define TEGRA124_CLK_AMX 153
 179 #define TEGRA124_CLK_ADX 154
 180 /* 155 (bit affects dfll_ref and dfll_soc) */
 181 #define TEGRA124_CLK_XUSB_SS 156
 182 /* 157 */
 183 /* 158 */
 184 /* 159 */
 185 
 186 /* 160 */
 187 /* 161 */
 188 /* 162 */
 189 /* 163 */
 190 /* 164 */
 191 /* 165 */
 192 #define TEGRA124_CLK_I2C6 166
 193 /* 167 */
 194 /* 168 */
 195 /* 169 */
 196 /* 170 */
 197 #define TEGRA124_CLK_VIM2_CLK 171
 198 /* 172 */
 199 /* 173 */
 200 /* 174 */
 201 /* 175 */
 202 #define TEGRA124_CLK_HDMI_AUDIO 176
 203 #define TEGRA124_CLK_CLK72MHZ 177
 204 #define TEGRA124_CLK_VIC03 178
 205 /* 179 */
 206 #define TEGRA124_CLK_ADX1 180
 207 #define TEGRA124_CLK_DPAUX 181
 208 #define TEGRA124_CLK_SOR0 182
 209 /* 183 */
 210 #define TEGRA124_CLK_GPU 184
 211 #define TEGRA124_CLK_AMX1 185
 212 /* 186 */
 213 /* 187 */
 214 /* 188 */
 215 /* 189 */
 216 /* 190 */
 217 /* 191 */
 218 #define TEGRA124_CLK_UARTB 192
 219 #define TEGRA124_CLK_VFIR 193
 220 #define TEGRA124_CLK_SPDIF_IN 194
 221 #define TEGRA124_CLK_SPDIF_OUT 195
 222 #define TEGRA124_CLK_VI 196
 223 #define TEGRA124_CLK_VI_SENSOR 197
 224 #define TEGRA124_CLK_FUSE 198
 225 #define TEGRA124_CLK_FUSE_BURN 199
 226 #define TEGRA124_CLK_CLK_32K 200
 227 #define TEGRA124_CLK_CLK_M 201
 228 #define TEGRA124_CLK_CLK_M_DIV2 202
 229 #define TEGRA124_CLK_CLK_M_DIV4 203
 230 #define TEGRA124_CLK_PLL_REF 204
 231 #define TEGRA124_CLK_PLL_C 205
 232 #define TEGRA124_CLK_PLL_C_OUT1 206
 233 #define TEGRA124_CLK_PLL_C2 207
 234 #define TEGRA124_CLK_PLL_C3 208
 235 #define TEGRA124_CLK_PLL_M 209
 236 #define TEGRA124_CLK_PLL_M_OUT1 210
 237 #define TEGRA124_CLK_PLL_P 211
 238 #define TEGRA124_CLK_PLL_P_OUT1 212
 239 #define TEGRA124_CLK_PLL_P_OUT2 213
 240 #define TEGRA124_CLK_PLL_P_OUT3 214
 241 #define TEGRA124_CLK_PLL_P_OUT4 215
 242 #define TEGRA124_CLK_PLL_A 216
 243 #define TEGRA124_CLK_PLL_A_OUT0 217
 244 #define TEGRA124_CLK_PLL_D 218
 245 #define TEGRA124_CLK_PLL_D_OUT0 219
 246 #define TEGRA124_CLK_PLL_D2 220
 247 #define TEGRA124_CLK_PLL_D2_OUT0 221
 248 #define TEGRA124_CLK_PLL_U 222
 249 #define TEGRA124_CLK_PLL_U_480M 223
 250 
 251 #define TEGRA124_CLK_PLL_U_60M 224
 252 #define TEGRA124_CLK_PLL_U_48M 225
 253 #define TEGRA124_CLK_PLL_U_12M 226
 254 /* 227 */
 255 /* 228 */
 256 #define TEGRA124_CLK_PLL_RE_VCO 229
 257 #define TEGRA124_CLK_PLL_RE_OUT 230
 258 #define TEGRA124_CLK_PLL_E 231
 259 #define TEGRA124_CLK_SPDIF_IN_SYNC 232
 260 #define TEGRA124_CLK_I2S0_SYNC 233
 261 #define TEGRA124_CLK_I2S1_SYNC 234
 262 #define TEGRA124_CLK_I2S2_SYNC 235
 263 #define TEGRA124_CLK_I2S3_SYNC 236
 264 #define TEGRA124_CLK_I2S4_SYNC 237
 265 #define TEGRA124_CLK_VIMCLK_SYNC 238
 266 #define TEGRA124_CLK_AUDIO0 239
 267 #define TEGRA124_CLK_AUDIO1 240
 268 #define TEGRA124_CLK_AUDIO2 241
 269 #define TEGRA124_CLK_AUDIO3 242
 270 #define TEGRA124_CLK_AUDIO4 243
 271 #define TEGRA124_CLK_SPDIF 244
 272 #define TEGRA124_CLK_CLK_OUT_1 245
 273 #define TEGRA124_CLK_CLK_OUT_2 246
 274 #define TEGRA124_CLK_CLK_OUT_3 247
 275 #define TEGRA124_CLK_BLINK 248
 276 /* 249 */
 277 /* 250 */
 278 /* 251 */
 279 #define TEGRA124_CLK_XUSB_HOST_SRC 252
 280 #define TEGRA124_CLK_XUSB_FALCON_SRC 253
 281 #define TEGRA124_CLK_XUSB_FS_SRC 254
 282 #define TEGRA124_CLK_XUSB_SS_SRC 255
 283 
 284 #define TEGRA124_CLK_XUSB_DEV_SRC 256
 285 #define TEGRA124_CLK_XUSB_DEV 257
 286 #define TEGRA124_CLK_XUSB_HS_SRC 258
 287 #define TEGRA124_CLK_SCLK 259
 288 #define TEGRA124_CLK_HCLK 260
 289 #define TEGRA124_CLK_PCLK 261
 290 /* 262 */
 291 /* 263 */
 292 #define TEGRA124_CLK_DFLL_REF 264
 293 #define TEGRA124_CLK_DFLL_SOC 265
 294 #define TEGRA124_CLK_VI_SENSOR2 266
 295 #define TEGRA124_CLK_PLL_P_OUT5 267
 296 #define TEGRA124_CLK_CML0 268
 297 #define TEGRA124_CLK_CML1 269
 298 #define TEGRA124_CLK_PLL_C4 270
 299 #define TEGRA124_CLK_PLL_DP 271
 300 #define TEGRA124_CLK_PLL_E_MUX 272
 301 #define TEGRA124_CLK_PLL_D_DSI_OUT 273
 302 /* 274 */
 303 /* 275 */
 304 /* 276 */
 305 /* 277 */
 306 /* 278 */
 307 /* 279 */
 308 /* 280 */
 309 /* 281 */
 310 /* 282 */
 311 /* 283 */
 312 /* 284 */
 313 /* 285 */
 314 /* 286 */
 315 /* 287 */
 316 
 317 /* 288 */
 318 /* 289 */
 319 /* 290 */
 320 /* 291 */
 321 /* 292 */
 322 /* 293 */
 323 /* 294 */
 324 /* 295 */
 325 /* 296 */
 326 /* 297 */
 327 /* 298 */
 328 /* 299 */
 329 #define TEGRA124_CLK_AUDIO0_MUX 300
 330 #define TEGRA124_CLK_AUDIO1_MUX 301
 331 #define TEGRA124_CLK_AUDIO2_MUX 302
 332 #define TEGRA124_CLK_AUDIO3_MUX 303
 333 #define TEGRA124_CLK_AUDIO4_MUX 304
 334 #define TEGRA124_CLK_SPDIF_MUX 305
 335 #define TEGRA124_CLK_CLK_OUT_1_MUX 306
 336 #define TEGRA124_CLK_CLK_OUT_2_MUX 307
 337 #define TEGRA124_CLK_CLK_OUT_3_MUX 308
 338 /* 309 */
 339 /* 310 */
 340 #define TEGRA124_CLK_SOR0_LVDS 311
 341 #define TEGRA124_CLK_XUSB_SS_DIV2 312
 342 
 343 #define TEGRA124_CLK_PLL_M_UD 313
 344 #define TEGRA124_CLK_PLL_C_UD 314
 345 
 346 #endif  /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */
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