root/scripts/dtc/include-prefixes/dt-bindings/clock/rk3308-cru.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
   4  * Author: Finley Xiao <finley.xiao@rock-chips.com>
   5  */
   6 
   7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
   8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
   9 
  10 /* core clocks */
  11 #define PLL_APLL                1
  12 #define PLL_DPLL                2
  13 #define PLL_VPLL0               3
  14 #define PLL_VPLL1               4
  15 #define ARMCLK                  5
  16 
  17 /* sclk (special clocks) */
  18 #define USB480M                 14
  19 #define SCLK_RTC32K             15
  20 #define SCLK_PVTM_CORE          16
  21 #define SCLK_UART0              17
  22 #define SCLK_UART1              18
  23 #define SCLK_UART2              19
  24 #define SCLK_UART3              20
  25 #define SCLK_UART4              21
  26 #define SCLK_I2C0               22
  27 #define SCLK_I2C1               23
  28 #define SCLK_I2C2               24
  29 #define SCLK_I2C3               25
  30 #define SCLK_PWM0               26
  31 #define SCLK_SPI0               27
  32 #define SCLK_SPI1               28
  33 #define SCLK_SPI2               29
  34 #define SCLK_TIMER0             30
  35 #define SCLK_TIMER1             31
  36 #define SCLK_TIMER2             32
  37 #define SCLK_TIMER3             33
  38 #define SCLK_TIMER4             34
  39 #define SCLK_TIMER5             35
  40 #define SCLK_TSADC              36
  41 #define SCLK_SARADC             37
  42 #define SCLK_OTP                38
  43 #define SCLK_OTP_USR            39
  44 #define SCLK_CPU_BOOST          40
  45 #define SCLK_CRYPTO             41
  46 #define SCLK_CRYPTO_APK         42
  47 #define SCLK_NANDC_DIV          43
  48 #define SCLK_NANDC_DIV50        44
  49 #define SCLK_NANDC              45
  50 #define SCLK_SDMMC_DIV          46
  51 #define SCLK_SDMMC_DIV50        47
  52 #define SCLK_SDMMC              48
  53 #define SCLK_SDMMC_DRV          49
  54 #define SCLK_SDMMC_SAMPLE       50
  55 #define SCLK_SDIO_DIV           51
  56 #define SCLK_SDIO_DIV50         52
  57 #define SCLK_SDIO               53
  58 #define SCLK_SDIO_DRV           54
  59 #define SCLK_SDIO_SAMPLE        55
  60 #define SCLK_EMMC_DIV           56
  61 #define SCLK_EMMC_DIV50         57
  62 #define SCLK_EMMC               58
  63 #define SCLK_EMMC_DRV           59
  64 #define SCLK_EMMC_SAMPLE        60
  65 #define SCLK_SFC                61
  66 #define SCLK_OTG_ADP            62
  67 #define SCLK_MAC_SRC            63
  68 #define SCLK_MAC                64
  69 #define SCLK_MAC_REF            65
  70 #define SCLK_MAC_RX_TX          66
  71 #define SCLK_MAC_RMII           67
  72 #define SCLK_DDR_MON_TIMER      68
  73 #define SCLK_DDR_MON            69
  74 #define SCLK_DDRCLK             70
  75 #define SCLK_PMU                71
  76 #define SCLK_USBPHY_REF         72
  77 #define SCLK_WIFI               73
  78 #define SCLK_PVTM_PMU           74
  79 #define SCLK_PDM                75
  80 #define SCLK_I2S0_8CH_TX        76
  81 #define SCLK_I2S0_8CH_TX_OUT    77
  82 #define SCLK_I2S0_8CH_RX        78
  83 #define SCLK_I2S0_8CH_RX_OUT    79
  84 #define SCLK_I2S1_8CH_TX        80
  85 #define SCLK_I2S1_8CH_TX_OUT    81
  86 #define SCLK_I2S1_8CH_RX        82
  87 #define SCLK_I2S1_8CH_RX_OUT    83
  88 #define SCLK_I2S2_8CH_TX        84
  89 #define SCLK_I2S2_8CH_TX_OUT    85
  90 #define SCLK_I2S2_8CH_RX        86
  91 #define SCLK_I2S2_8CH_RX_OUT    87
  92 #define SCLK_I2S3_8CH_TX        88
  93 #define SCLK_I2S3_8CH_TX_OUT    89
  94 #define SCLK_I2S3_8CH_RX        90
  95 #define SCLK_I2S3_8CH_RX_OUT    91
  96 #define SCLK_I2S0_2CH           92
  97 #define SCLK_I2S0_2CH_OUT       93
  98 #define SCLK_I2S1_2CH           94
  99 #define SCLK_I2S1_2CH_OUT       95
 100 #define SCLK_SPDIF_TX_DIV       96
 101 #define SCLK_SPDIF_TX_DIV50     97
 102 #define SCLK_SPDIF_TX           98
 103 #define SCLK_SPDIF_RX_DIV       99
 104 #define SCLK_SPDIF_RX_DIV50     100
 105 #define SCLK_SPDIF_RX           101
 106 #define SCLK_I2S0_8CH_TX_MUX    102
 107 #define SCLK_I2S0_8CH_RX_MUX    103
 108 #define SCLK_I2S1_8CH_TX_MUX    104
 109 #define SCLK_I2S1_8CH_RX_MUX    105
 110 #define SCLK_I2S2_8CH_TX_MUX    106
 111 #define SCLK_I2S2_8CH_RX_MUX    107
 112 #define SCLK_I2S3_8CH_TX_MUX    108
 113 #define SCLK_I2S3_8CH_RX_MUX    109
 114 #define SCLK_I2S0_8CH_TX_SRC    110
 115 #define SCLK_I2S0_8CH_RX_SRC    111
 116 #define SCLK_I2S1_8CH_TX_SRC    112
 117 #define SCLK_I2S1_8CH_RX_SRC    113
 118 #define SCLK_I2S2_8CH_TX_SRC    114
 119 #define SCLK_I2S2_8CH_RX_SRC    115
 120 #define SCLK_I2S3_8CH_TX_SRC    116
 121 #define SCLK_I2S3_8CH_RX_SRC    117
 122 #define SCLK_I2S0_2CH_SRC       118
 123 #define SCLK_I2S1_2CH_SRC       119
 124 #define SCLK_PWM1               120
 125 #define SCLK_PWM2               121
 126 #define SCLK_OWIRE              122
 127 
 128 /* dclk */
 129 #define DCLK_VOP                125
 130 
 131 /* aclk */
 132 #define ACLK_BUS_SRC            130
 133 #define ACLK_BUS                131
 134 #define ACLK_PERI_SRC           132
 135 #define ACLK_PERI               133
 136 #define ACLK_MAC                134
 137 #define ACLK_CRYPTO             135
 138 #define ACLK_VOP                136
 139 #define ACLK_GIC                137
 140 #define ACLK_DMAC0              138
 141 #define ACLK_DMAC1              139
 142 
 143 /* hclk */
 144 #define HCLK_BUS                150
 145 #define HCLK_PERI               151
 146 #define HCLK_AUDIO              152
 147 #define HCLK_NANDC              153
 148 #define HCLK_SDMMC              154
 149 #define HCLK_SDIO               155
 150 #define HCLK_EMMC               156
 151 #define HCLK_SFC                157
 152 #define HCLK_OTG                158
 153 #define HCLK_HOST               159
 154 #define HCLK_HOST_ARB           160
 155 #define HCLK_PDM                161
 156 #define HCLK_SPDIFTX            162
 157 #define HCLK_SPDIFRX            163
 158 #define HCLK_I2S0_8CH           164
 159 #define HCLK_I2S1_8CH           165
 160 #define HCLK_I2S2_8CH           166
 161 #define HCLK_I2S3_8CH           167
 162 #define HCLK_I2S0_2CH           168
 163 #define HCLK_I2S1_2CH           169
 164 #define HCLK_VAD                170
 165 #define HCLK_CRYPTO             171
 166 #define HCLK_VOP                172
 167 
 168 /* pclk */
 169 #define PCLK_BUS                190
 170 #define PCLK_DDR                191
 171 #define PCLK_PERI               192
 172 #define PCLK_PMU                193
 173 #define PCLK_AUDIO              194
 174 #define PCLK_MAC                195
 175 #define PCLK_ACODEC             196
 176 #define PCLK_UART0              197
 177 #define PCLK_UART1              198
 178 #define PCLK_UART2              199
 179 #define PCLK_UART3              200
 180 #define PCLK_UART4              201
 181 #define PCLK_I2C0               202
 182 #define PCLK_I2C1               203
 183 #define PCLK_I2C2               204
 184 #define PCLK_I2C3               205
 185 #define PCLK_PWM0               206
 186 #define PCLK_SPI0               207
 187 #define PCLK_SPI1               208
 188 #define PCLK_SPI2               209
 189 #define PCLK_SARADC             210
 190 #define PCLK_TSADC              211
 191 #define PCLK_TIMER              212
 192 #define PCLK_OTP_NS             213
 193 #define PCLK_WDT                214
 194 #define PCLK_GPIO0              215
 195 #define PCLK_GPIO1              216
 196 #define PCLK_GPIO2              217
 197 #define PCLK_GPIO3              218
 198 #define PCLK_GPIO4              219
 199 #define PCLK_SGRF               220
 200 #define PCLK_GRF                221
 201 #define PCLK_USBSD_DET          222
 202 #define PCLK_DDR_UPCTL          223
 203 #define PCLK_DDR_MON            224
 204 #define PCLK_DDRPHY             225
 205 #define PCLK_DDR_STDBY          226
 206 #define PCLK_USB_GRF            227
 207 #define PCLK_CRU                228
 208 #define PCLK_OTP_PHY            229
 209 #define PCLK_CPU_BOOST          230
 210 #define PCLK_PWM1               231
 211 #define PCLK_PWM2               232
 212 #define PCLK_CAN                233
 213 #define PCLK_OWIRE              234
 214 
 215 #define CLK_NR_CLKS             (PCLK_OWIRE + 1)
 216 
 217 /* soft-reset indices */
 218 
 219 /* cru_softrst_con0 */
 220 #define SRST_CORE0_PO           0
 221 #define SRST_CORE1_PO           1
 222 #define SRST_CORE2_PO           2
 223 #define SRST_CORE3_PO           3
 224 #define SRST_CORE0              4
 225 #define SRST_CORE1              5
 226 #define SRST_CORE2              6
 227 #define SRST_CORE3              7
 228 #define SRST_CORE0_DBG          8
 229 #define SRST_CORE1_DBG          9
 230 #define SRST_CORE2_DBG          10
 231 #define SRST_CORE3_DBG          11
 232 #define SRST_TOPDBG             12
 233 #define SRST_CORE_NOC           13
 234 #define SRST_STRC_A             14
 235 #define SRST_L2C                15
 236 
 237 /* cru_softrst_con1 */
 238 #define SRST_DAP                16
 239 #define SRST_CORE_PVTM          17
 240 #define SRST_CORE_PRF           18
 241 #define SRST_CORE_GRF           19
 242 #define SRST_DDRUPCTL           20
 243 #define SRST_DDRUPCTL_P         22
 244 #define SRST_MSCH               23
 245 #define SRST_DDRMON_P           25
 246 #define SRST_DDRSTDBY_P         26
 247 #define SRST_DDRSTDBY           27
 248 #define SRST_DDRPHY             28
 249 #define SRST_DDRPHY_DIV         29
 250 #define SRST_DDRPHY_P           30
 251 
 252 /* cru_softrst_con2 */
 253 #define SRST_BUS_NIU_H          32
 254 #define SRST_USB_NIU_P          33
 255 #define SRST_CRYPTO_A           34
 256 #define SRST_CRYPTO_H           35
 257 #define SRST_CRYPTO             36
 258 #define SRST_CRYPTO_APK         37
 259 #define SRST_VOP_A              38
 260 #define SRST_VOP_H              39
 261 #define SRST_VOP_D              40
 262 #define SRST_INTMEM_A           41
 263 #define SRST_ROM_H              42
 264 #define SRST_GIC_A              43
 265 #define SRST_UART0_P            44
 266 #define SRST_UART0              45
 267 #define SRST_UART1_P            46
 268 #define SRST_UART1              47
 269 
 270 /* cru_softrst_con3 */
 271 #define SRST_UART2_P            48
 272 #define SRST_UART2              49
 273 #define SRST_UART3_P            50
 274 #define SRST_UART3              51
 275 #define SRST_UART4_P            52
 276 #define SRST_UART4              53
 277 #define SRST_I2C0_P             54
 278 #define SRST_I2C0               55
 279 #define SRST_I2C1_P             56
 280 #define SRST_I2C1               57
 281 #define SRST_I2C2_P             58
 282 #define SRST_I2C2               59
 283 #define SRST_I2C3_P             60
 284 #define SRST_I2C3               61
 285 #define SRST_PWM0_P             62
 286 #define SRST_PWM0               63
 287 
 288 /* cru_softrst_con4 */
 289 #define SRST_SPI0_P             64
 290 #define SRST_SPI0               65
 291 #define SRST_SPI1_P             66
 292 #define SRST_SPI1               67
 293 #define SRST_SPI2_P             68
 294 #define SRST_SPI2               69
 295 #define SRST_SARADC_P           70
 296 #define SRST_TSADC_P            71
 297 #define SRST_TSADC              72
 298 #define SRST_TIMER0_P           73
 299 #define SRST_TIMER0             74
 300 #define SRST_TIMER1             75
 301 #define SRST_TIMER2             76
 302 #define SRST_TIMER3             77
 303 #define SRST_TIMER4             78
 304 #define SRST_TIMER5             79
 305 
 306 /* cru_softrst_con5 */
 307 #define SRST_OTP_NS_P           80
 308 #define SRST_OTP_NS_SBPI        81
 309 #define SRST_OTP_NS_USR         82
 310 #define SRST_OTP_PHY_P          83
 311 #define SRST_OTP_PHY            84
 312 #define SRST_GPIO0_P            86
 313 #define SRST_GPIO1_P            87
 314 #define SRST_GPIO2_P            88
 315 #define SRST_GPIO3_P            89
 316 #define SRST_GPIO4_P            90
 317 #define SRST_GRF_P              91
 318 #define SRST_USBSD_DET_P        92
 319 #define SRST_PMU                93
 320 #define SRST_PMU_PVTM           94
 321 #define SRST_USB_GRF_P          95
 322 
 323 /* cru_softrst_con6 */
 324 #define SRST_CPU_BOOST          96
 325 #define SRST_CPU_BOOST_P        97
 326 #define SRST_PWM1_P             98
 327 #define SRST_PWM1               99
 328 #define SRST_PWM2_P             100
 329 #define SRST_PWM2               101
 330 #define SRST_PERI_NIU_A         104
 331 #define SRST_PERI_NIU_H         105
 332 #define SRST_PERI_NIU_p         106
 333 #define SRST_USB2OTG_H          107
 334 #define SRST_USB2OTG            108
 335 #define SRST_USB2OTG_ADP        109
 336 #define SRST_USB2HOST_H         110
 337 #define SRST_USB2HOST_ARB_H     111
 338 
 339 /* cru_softrst_con7 */
 340 #define SRST_USB2HOST_AUX_H     112
 341 #define SRST_USB2HOST_EHCI      113
 342 #define SRST_USB2HOST           114
 343 #define SRST_USBPHYPOR          115
 344 #define SRST_UTMI0              116
 345 #define SRST_UTMI1              117
 346 #define SRST_SDIO_H             118
 347 #define SRST_EMMC_H             119
 348 #define SRST_SFC_H              120
 349 #define SRST_SFC                121
 350 #define SRST_SD_H               122
 351 #define SRST_NANDC_H            123
 352 #define SRST_NANDC_N            124
 353 #define SRST_MAC_A              125
 354 #define SRST_CAN_P              126
 355 #define SRST_OWIRE_P            127
 356 
 357 /* cru_softrst_con8 */
 358 #define SRST_AUDIO_NIU_H        128
 359 #define SRST_AUDIO_NIU_P        129
 360 #define SRST_PDM_H              130
 361 #define SRST_PDM_M              131
 362 #define SRST_SPDIFTX_H          132
 363 #define SRST_SPDIFTX_M          133
 364 #define SRST_SPDIFRX_H          134
 365 #define SRST_SPDIFRX_M          135
 366 #define SRST_I2S0_8CH_H         136
 367 #define SRST_I2S0_8CH_TX_M      137
 368 #define SRST_I2S0_8CH_RX_M      138
 369 #define SRST_I2S1_8CH_H         139
 370 #define SRST_I2S1_8CH_TX_M      140
 371 #define SRST_I2S1_8CH_RX_M      141
 372 #define SRST_I2S2_8CH_H         142
 373 #define SRST_I2S2_8CH_TX_M      143
 374 
 375 /* cru_softrst_con9 */
 376 #define SRST_I2S2_8CH_RX_M      144
 377 #define SRST_I2S3_8CH_H         145
 378 #define SRST_I2S3_8CH_TX_M      146
 379 #define SRST_I2S3_8CH_RX_M      147
 380 #define SRST_I2S0_2CH_H         148
 381 #define SRST_I2S0_2CH_M         149
 382 #define SRST_I2S1_2CH_H         150
 383 #define SRST_I2S1_2CH_M         151
 384 #define SRST_VAD_H              152
 385 #define SRST_ACODEC_P           153
 386 
 387 #endif