root/scripts/dtc/include-prefixes/dt-bindings/clock/r8a7794-clock.h

   1 /* SPDX-License-Identifier: GPL-2.0+
   2  *
   3  * Copyright (C) 2014 Renesas Electronics Corporation
   4  * Copyright 2013 Ideas On Board SPRL
   5  */
   6 
   7 #ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
   8 #define __DT_BINDINGS_CLOCK_R8A7794_H__
   9 
  10 /* CPG */
  11 #define R8A7794_CLK_MAIN                0
  12 #define R8A7794_CLK_PLL0                1
  13 #define R8A7794_CLK_PLL1                2
  14 #define R8A7794_CLK_PLL3                3
  15 #define R8A7794_CLK_LB                  4
  16 #define R8A7794_CLK_QSPI                5
  17 #define R8A7794_CLK_SDH                 6
  18 #define R8A7794_CLK_SD0                 7
  19 #define R8A7794_CLK_RCAN                8
  20 
  21 /* MSTP0 */
  22 #define R8A7794_CLK_MSIOF0              0
  23 
  24 /* MSTP1 */
  25 #define R8A7794_CLK_VCP0                1
  26 #define R8A7794_CLK_VPC0                3
  27 #define R8A7794_CLK_TMU1                11
  28 #define R8A7794_CLK_3DG                 12
  29 #define R8A7794_CLK_2DDMAC              15
  30 #define R8A7794_CLK_FDP1_0              19
  31 #define R8A7794_CLK_TMU3                21
  32 #define R8A7794_CLK_TMU2                22
  33 #define R8A7794_CLK_CMT0                24
  34 #define R8A7794_CLK_TMU0                25
  35 #define R8A7794_CLK_VSP1_DU0            28
  36 #define R8A7794_CLK_VSP1_S              31
  37 
  38 /* MSTP2 */
  39 #define R8A7794_CLK_SCIFA2              2
  40 #define R8A7794_CLK_SCIFA1              3
  41 #define R8A7794_CLK_SCIFA0              4
  42 #define R8A7794_CLK_MSIOF2              5
  43 #define R8A7794_CLK_SCIFB0              6
  44 #define R8A7794_CLK_SCIFB1              7
  45 #define R8A7794_CLK_MSIOF1              8
  46 #define R8A7794_CLK_SCIFB2              16
  47 #define R8A7794_CLK_SYS_DMAC1           18
  48 #define R8A7794_CLK_SYS_DMAC0           19
  49 
  50 /* MSTP3 */
  51 #define R8A7794_CLK_SDHI2               11
  52 #define R8A7794_CLK_SDHI1               12
  53 #define R8A7794_CLK_SDHI0               14
  54 #define R8A7794_CLK_MMCIF0              15
  55 #define R8A7794_CLK_IIC0                18
  56 #define R8A7794_CLK_IIC1                23
  57 #define R8A7794_CLK_CMT1                29
  58 #define R8A7794_CLK_USBDMAC0            30
  59 #define R8A7794_CLK_USBDMAC1            31
  60 
  61 /* MSTP4 */
  62 #define R8A7794_CLK_IRQC                7
  63 #define R8A7794_CLK_INTC_SYS            8
  64 
  65 /* MSTP5 */
  66 #define R8A7794_CLK_AUDIO_DMAC0         2
  67 #define R8A7794_CLK_PWM                 23
  68 
  69 /* MSTP7 */
  70 #define R8A7794_CLK_EHCI                3
  71 #define R8A7794_CLK_HSUSB               4
  72 #define R8A7794_CLK_HSCIF2              13
  73 #define R8A7794_CLK_SCIF5               14
  74 #define R8A7794_CLK_SCIF4               15
  75 #define R8A7794_CLK_HSCIF1              16
  76 #define R8A7794_CLK_HSCIF0              17
  77 #define R8A7794_CLK_SCIF3               18
  78 #define R8A7794_CLK_SCIF2               19
  79 #define R8A7794_CLK_SCIF1               20
  80 #define R8A7794_CLK_SCIF0               21
  81 #define R8A7794_CLK_DU1                 23
  82 #define R8A7794_CLK_DU0                 24
  83 
  84 /* MSTP8 */
  85 #define R8A7794_CLK_VIN1                10
  86 #define R8A7794_CLK_VIN0                11
  87 #define R8A7794_CLK_ETHERAVB            12
  88 #define R8A7794_CLK_ETHER               13
  89 
  90 /* MSTP9 */
  91 #define R8A7794_CLK_GPIO6               5
  92 #define R8A7794_CLK_GPIO5               7
  93 #define R8A7794_CLK_GPIO4               8
  94 #define R8A7794_CLK_GPIO3               9
  95 #define R8A7794_CLK_GPIO2               10
  96 #define R8A7794_CLK_GPIO1               11
  97 #define R8A7794_CLK_GPIO0               12
  98 #define R8A7794_CLK_RCAN1               15
  99 #define R8A7794_CLK_RCAN0               16
 100 #define R8A7794_CLK_QSPI_MOD            17
 101 #define R8A7794_CLK_I2C5                25
 102 #define R8A7794_CLK_I2C4                27
 103 #define R8A7794_CLK_I2C3                28
 104 #define R8A7794_CLK_I2C2                29
 105 #define R8A7794_CLK_I2C1                30
 106 #define R8A7794_CLK_I2C0                31
 107 
 108 /* MSTP10 */
 109 #define R8A7794_CLK_SSI_ALL             5
 110 #define R8A7794_CLK_SSI9                6
 111 #define R8A7794_CLK_SSI8                7
 112 #define R8A7794_CLK_SSI7                8
 113 #define R8A7794_CLK_SSI6                9
 114 #define R8A7794_CLK_SSI5                10
 115 #define R8A7794_CLK_SSI4                11
 116 #define R8A7794_CLK_SSI3                12
 117 #define R8A7794_CLK_SSI2                13
 118 #define R8A7794_CLK_SSI1                14
 119 #define R8A7794_CLK_SSI0                15
 120 #define R8A7794_CLK_SCU_ALL             17
 121 #define R8A7794_CLK_SCU_DVC1            18
 122 #define R8A7794_CLK_SCU_DVC0            19
 123 #define R8A7794_CLK_SCU_CTU1_MIX1       20
 124 #define R8A7794_CLK_SCU_CTU0_MIX0       21
 125 #define R8A7794_CLK_SCU_SRC6            25
 126 #define R8A7794_CLK_SCU_SRC5            26
 127 #define R8A7794_CLK_SCU_SRC4            27
 128 #define R8A7794_CLK_SCU_SRC3            28
 129 #define R8A7794_CLK_SCU_SRC2            29
 130 #define R8A7794_CLK_SCU_SRC1            30
 131 
 132 /* MSTP11 */
 133 #define R8A7794_CLK_SCIFA3              6
 134 #define R8A7794_CLK_SCIFA4              7
 135 #define R8A7794_CLK_SCIFA5              8
 136 
 137 #endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */