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6 #ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H
7 #define _DT_BINDINGS_CLK_APQ_MMCC_8084_H
8
9 #define MMSS_AHB_CLK_SRC 0
10 #define MMSS_AXI_CLK_SRC 1
11 #define MMPLL0 2
12 #define MMPLL0_VOTE 3
13 #define MMPLL1 4
14 #define MMPLL1_VOTE 5
15 #define MMPLL2 6
16 #define MMPLL3 7
17 #define MMPLL4 8
18 #define CSI0_CLK_SRC 9
19 #define CSI1_CLK_SRC 10
20 #define CSI2_CLK_SRC 11
21 #define CSI3_CLK_SRC 12
22 #define VCODEC0_CLK_SRC 13
23 #define VFE0_CLK_SRC 14
24 #define VFE1_CLK_SRC 15
25 #define MDP_CLK_SRC 16
26 #define PCLK0_CLK_SRC 17
27 #define PCLK1_CLK_SRC 18
28 #define OCMEMNOC_CLK_SRC 19
29 #define GFX3D_CLK_SRC 20
30 #define JPEG0_CLK_SRC 21
31 #define JPEG1_CLK_SRC 22
32 #define JPEG2_CLK_SRC 23
33 #define EDPPIXEL_CLK_SRC 24
34 #define EXTPCLK_CLK_SRC 25
35 #define VP_CLK_SRC 26
36 #define CCI_CLK_SRC 27
37 #define CAMSS_GP0_CLK_SRC 28
38 #define CAMSS_GP1_CLK_SRC 29
39 #define MCLK0_CLK_SRC 30
40 #define MCLK1_CLK_SRC 31
41 #define MCLK2_CLK_SRC 32
42 #define MCLK3_CLK_SRC 33
43 #define CSI0PHYTIMER_CLK_SRC 34
44 #define CSI1PHYTIMER_CLK_SRC 35
45 #define CSI2PHYTIMER_CLK_SRC 36
46 #define CPP_CLK_SRC 37
47 #define BYTE0_CLK_SRC 38
48 #define BYTE1_CLK_SRC 39
49 #define EDPAUX_CLK_SRC 40
50 #define EDPLINK_CLK_SRC 41
51 #define ESC0_CLK_SRC 42
52 #define ESC1_CLK_SRC 43
53 #define HDMI_CLK_SRC 44
54 #define VSYNC_CLK_SRC 45
55 #define MMSS_RBCPR_CLK_SRC 46
56 #define RBBMTIMER_CLK_SRC 47
57 #define MAPLE_CLK_SRC 48
58 #define VDP_CLK_SRC 49
59 #define VPU_BUS_CLK_SRC 50
60 #define MMSS_CXO_CLK 51
61 #define MMSS_SLEEPCLK_CLK 52
62 #define AVSYNC_AHB_CLK 53
63 #define AVSYNC_EDPPIXEL_CLK 54
64 #define AVSYNC_EXTPCLK_CLK 55
65 #define AVSYNC_PCLK0_CLK 56
66 #define AVSYNC_PCLK1_CLK 57
67 #define AVSYNC_VP_CLK 58
68 #define CAMSS_AHB_CLK 59
69 #define CAMSS_CCI_CCI_AHB_CLK 60
70 #define CAMSS_CCI_CCI_CLK 61
71 #define CAMSS_CSI0_AHB_CLK 62
72 #define CAMSS_CSI0_CLK 63
73 #define CAMSS_CSI0PHY_CLK 64
74 #define CAMSS_CSI0PIX_CLK 65
75 #define CAMSS_CSI0RDI_CLK 66
76 #define CAMSS_CSI1_AHB_CLK 67
77 #define CAMSS_CSI1_CLK 68
78 #define CAMSS_CSI1PHY_CLK 69
79 #define CAMSS_CSI1PIX_CLK 70
80 #define CAMSS_CSI1RDI_CLK 71
81 #define CAMSS_CSI2_AHB_CLK 72
82 #define CAMSS_CSI2_CLK 73
83 #define CAMSS_CSI2PHY_CLK 74
84 #define CAMSS_CSI2PIX_CLK 75
85 #define CAMSS_CSI2RDI_CLK 76
86 #define CAMSS_CSI3_AHB_CLK 77
87 #define CAMSS_CSI3_CLK 78
88 #define CAMSS_CSI3PHY_CLK 79
89 #define CAMSS_CSI3PIX_CLK 80
90 #define CAMSS_CSI3RDI_CLK 81
91 #define CAMSS_CSI_VFE0_CLK 82
92 #define CAMSS_CSI_VFE1_CLK 83
93 #define CAMSS_GP0_CLK 84
94 #define CAMSS_GP1_CLK 85
95 #define CAMSS_ISPIF_AHB_CLK 86
96 #define CAMSS_JPEG_JPEG0_CLK 87
97 #define CAMSS_JPEG_JPEG1_CLK 88
98 #define CAMSS_JPEG_JPEG2_CLK 89
99 #define CAMSS_JPEG_JPEG_AHB_CLK 90
100 #define CAMSS_JPEG_JPEG_AXI_CLK 91
101 #define CAMSS_MCLK0_CLK 92
102 #define CAMSS_MCLK1_CLK 93
103 #define CAMSS_MCLK2_CLK 94
104 #define CAMSS_MCLK3_CLK 95
105 #define CAMSS_MICRO_AHB_CLK 96
106 #define CAMSS_PHY0_CSI0PHYTIMER_CLK 97
107 #define CAMSS_PHY1_CSI1PHYTIMER_CLK 98
108 #define CAMSS_PHY2_CSI2PHYTIMER_CLK 99
109 #define CAMSS_TOP_AHB_CLK 100
110 #define CAMSS_VFE_CPP_AHB_CLK 101
111 #define CAMSS_VFE_CPP_CLK 102
112 #define CAMSS_VFE_VFE0_CLK 103
113 #define CAMSS_VFE_VFE1_CLK 104
114 #define CAMSS_VFE_VFE_AHB_CLK 105
115 #define CAMSS_VFE_VFE_AXI_CLK 106
116 #define MDSS_AHB_CLK 107
117 #define MDSS_AXI_CLK 108
118 #define MDSS_BYTE0_CLK 109
119 #define MDSS_BYTE1_CLK 110
120 #define MDSS_EDPAUX_CLK 111
121 #define MDSS_EDPLINK_CLK 112
122 #define MDSS_EDPPIXEL_CLK 113
123 #define MDSS_ESC0_CLK 114
124 #define MDSS_ESC1_CLK 115
125 #define MDSS_EXTPCLK_CLK 116
126 #define MDSS_HDMI_AHB_CLK 117
127 #define MDSS_HDMI_CLK 118
128 #define MDSS_MDP_CLK 119
129 #define MDSS_MDP_LUT_CLK 120
130 #define MDSS_PCLK0_CLK 121
131 #define MDSS_PCLK1_CLK 122
132 #define MDSS_VSYNC_CLK 123
133 #define MMSS_RBCPR_AHB_CLK 124
134 #define MMSS_RBCPR_CLK 125
135 #define MMSS_SPDM_AHB_CLK 126
136 #define MMSS_SPDM_AXI_CLK 127
137 #define MMSS_SPDM_CSI0_CLK 128
138 #define MMSS_SPDM_GFX3D_CLK 129
139 #define MMSS_SPDM_JPEG0_CLK 130
140 #define MMSS_SPDM_JPEG1_CLK 131
141 #define MMSS_SPDM_JPEG2_CLK 132
142 #define MMSS_SPDM_MDP_CLK 133
143 #define MMSS_SPDM_PCLK0_CLK 134
144 #define MMSS_SPDM_PCLK1_CLK 135
145 #define MMSS_SPDM_VCODEC0_CLK 136
146 #define MMSS_SPDM_VFE0_CLK 137
147 #define MMSS_SPDM_VFE1_CLK 138
148 #define MMSS_SPDM_RM_AXI_CLK 139
149 #define MMSS_SPDM_RM_OCMEMNOC_CLK 140
150 #define MMSS_MISC_AHB_CLK 141
151 #define MMSS_MMSSNOC_AHB_CLK 142
152 #define MMSS_MMSSNOC_BTO_AHB_CLK 143
153 #define MMSS_MMSSNOC_AXI_CLK 144
154 #define MMSS_S0_AXI_CLK 145
155 #define OCMEMCX_AHB_CLK 146
156 #define OCMEMCX_OCMEMNOC_CLK 147
157 #define OXILI_OCMEMGX_CLK 148
158 #define OXILI_GFX3D_CLK 149
159 #define OXILI_RBBMTIMER_CLK 150
160 #define OXILICX_AHB_CLK 151
161 #define VENUS0_AHB_CLK 152
162 #define VENUS0_AXI_CLK 153
163 #define VENUS0_CORE0_VCODEC_CLK 154
164 #define VENUS0_CORE1_VCODEC_CLK 155
165 #define VENUS0_OCMEMNOC_CLK 156
166 #define VENUS0_VCODEC0_CLK 157
167 #define VPU_AHB_CLK 158
168 #define VPU_AXI_CLK 159
169 #define VPU_BUS_CLK 160
170 #define VPU_CXO_CLK 161
171 #define VPU_MAPLE_CLK 162
172 #define VPU_SLEEP_CLK 163
173 #define VPU_VDP_CLK 164
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175
176 #define VENUS0_GDSC 0
177 #define VENUS0_CORE0_GDSC 1
178 #define VENUS0_CORE1_GDSC 2
179 #define MDSS_GDSC 3
180 #define CAMSS_JPEG_GDSC 4
181 #define CAMSS_VFE_GDSC 5
182 #define OXILI_GDSC 6
183 #define OXILICX_GDSC 7
184
185 #endif