root/scripts/dtc/include-prefixes/dt-bindings/clock/sun50i-h6-ccu.h

INCLUDED FROM

   1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
   2 /*
   3  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
   4  */
   5 
   6 #ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
   7 #define _DT_BINDINGS_CLK_SUN50I_H6_H_
   8 
   9 #define CLK_PLL_PERIPH0         3
  10 
  11 #define CLK_CPUX                21
  12 
  13 #define CLK_APB1                26
  14 
  15 #define CLK_DE                  29
  16 #define CLK_BUS_DE              30
  17 #define CLK_DEINTERLACE         31
  18 #define CLK_BUS_DEINTERLACE     32
  19 #define CLK_GPU                 33
  20 #define CLK_BUS_GPU             34
  21 #define CLK_CE                  35
  22 #define CLK_BUS_CE              36
  23 #define CLK_VE                  37
  24 #define CLK_BUS_VE              38
  25 #define CLK_EMCE                39
  26 #define CLK_BUS_EMCE            40
  27 #define CLK_VP9                 41
  28 #define CLK_BUS_VP9             42
  29 #define CLK_BUS_DMA             43
  30 #define CLK_BUS_MSGBOX          44
  31 #define CLK_BUS_SPINLOCK        45
  32 #define CLK_BUS_HSTIMER         46
  33 #define CLK_AVS                 47
  34 #define CLK_BUS_DBG             48
  35 #define CLK_BUS_PSI             49
  36 #define CLK_BUS_PWM             50
  37 #define CLK_BUS_IOMMU           51
  38 
  39 #define CLK_MBUS_DMA            53
  40 #define CLK_MBUS_VE             54
  41 #define CLK_MBUS_CE             55
  42 #define CLK_MBUS_TS             56
  43 #define CLK_MBUS_NAND           57
  44 #define CLK_MBUS_CSI            58
  45 #define CLK_MBUS_DEINTERLACE    59
  46 
  47 #define CLK_NAND0               61
  48 #define CLK_NAND1               62
  49 #define CLK_BUS_NAND            63
  50 #define CLK_MMC0                64
  51 #define CLK_MMC1                65
  52 #define CLK_MMC2                66
  53 #define CLK_BUS_MMC0            67
  54 #define CLK_BUS_MMC1            68
  55 #define CLK_BUS_MMC2            69
  56 #define CLK_BUS_UART0           70
  57 #define CLK_BUS_UART1           71
  58 #define CLK_BUS_UART2           72
  59 #define CLK_BUS_UART3           73
  60 #define CLK_BUS_I2C0            74
  61 #define CLK_BUS_I2C1            75
  62 #define CLK_BUS_I2C2            76
  63 #define CLK_BUS_I2C3            77
  64 #define CLK_BUS_SCR0            78
  65 #define CLK_BUS_SCR1            79
  66 #define CLK_SPI0                80
  67 #define CLK_SPI1                81
  68 #define CLK_BUS_SPI0            82
  69 #define CLK_BUS_SPI1            83
  70 #define CLK_BUS_EMAC            84
  71 #define CLK_TS                  85
  72 #define CLK_BUS_TS              86
  73 #define CLK_IR_TX               87
  74 #define CLK_BUS_IR_TX           88
  75 #define CLK_BUS_THS             89
  76 #define CLK_I2S3                90
  77 #define CLK_I2S0                91
  78 #define CLK_I2S1                92
  79 #define CLK_I2S2                93
  80 #define CLK_BUS_I2S0            94
  81 #define CLK_BUS_I2S1            95
  82 #define CLK_BUS_I2S2            96
  83 #define CLK_BUS_I2S3            97
  84 #define CLK_SPDIF               98
  85 #define CLK_BUS_SPDIF           99
  86 #define CLK_DMIC                100
  87 #define CLK_BUS_DMIC            101
  88 #define CLK_AUDIO_HUB           102
  89 #define CLK_BUS_AUDIO_HUB       103
  90 #define CLK_USB_OHCI0           104
  91 #define CLK_USB_PHY0            105
  92 #define CLK_USB_PHY1            106
  93 #define CLK_USB_OHCI3           107
  94 #define CLK_USB_PHY3            108
  95 #define CLK_USB_HSIC_12M        109
  96 #define CLK_USB_HSIC            110
  97 #define CLK_BUS_OHCI0           111
  98 #define CLK_BUS_OHCI3           112
  99 #define CLK_BUS_EHCI0           113
 100 #define CLK_BUS_XHCI            114
 101 #define CLK_BUS_EHCI3           115
 102 #define CLK_BUS_OTG             116
 103 #define CLK_PCIE_REF_100M       117
 104 #define CLK_PCIE_REF            118
 105 #define CLK_PCIE_REF_OUT        119
 106 #define CLK_PCIE_MAXI           120
 107 #define CLK_PCIE_AUX            121
 108 #define CLK_BUS_PCIE            122
 109 #define CLK_HDMI                123
 110 #define CLK_HDMI_SLOW           124
 111 #define CLK_HDMI_CEC            125
 112 #define CLK_BUS_HDMI            126
 113 #define CLK_BUS_TCON_TOP        127
 114 #define CLK_TCON_LCD0           128
 115 #define CLK_BUS_TCON_LCD0       129
 116 #define CLK_TCON_TV0            130
 117 #define CLK_BUS_TCON_TV0        131
 118 #define CLK_CSI_CCI             132
 119 #define CLK_CSI_TOP             133
 120 #define CLK_CSI_MCLK            134
 121 #define CLK_BUS_CSI             135
 122 #define CLK_HDCP                136
 123 #define CLK_BUS_HDCP            137
 124 
 125 #endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */