root/arch/mips/dec/kn02xa-berr.c

DEFINITIONS

1. dec_kn02xa_be_ack
2. dec_kn02xa_be_backend
3. dec_kn02xa_be_handler
4. dec_kn02xa_be_interrupt
5. dec_kn02xa_be_init

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *      Bus error event handling code for 5000-series systems equipped
   4  *      with parity error detection logic, i.e. DECstation/DECsystem
   5  *      5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal
   6  *      DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50
   7  *      (KN04-CA) systems.
   8  *
   9  *      Copyright (c) 2005  Maciej W. Rozycki
  10  */
  11 
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 
  17 #include <asm/addrspace.h>
  18 #include <asm/cpu-type.h>
  19 #include <asm/irq_regs.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/traps.h>
  22 
  23 #include <asm/dec/kn02ca.h>
  24 #include <asm/dec/kn02xa.h>
  25 #include <asm/dec/kn05.h>
  26 
  27 static inline void dec_kn02xa_be_ack(void)
  28 {
  29         volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);
  30         volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);
  31 
  32         *mer = KN02CA_MER_INTR;         /* Clear errors; keep the ARC IRQ. */
  33         *mem_intr = 0;                  /* Any write clears the bus IRQ. */
  34         iob();
  35 }
  36 
  37 static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup,
  38                                  int invoker)
  39 {
  40         volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);
  41         volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);
  42 
  43         static const char excstr[] = "exception";
  44         static const char intstr[] = "interrupt";
  45         static const char cpustr[] = "CPU";
  46         static const char mreadstr[] = "memory read";
  47         static const char readstr[] = "read";
  48         static const char writestr[] = "write";
  49         static const char timestr[] = "timeout";
  50         static const char paritystr[] = "parity error";
  51         static const char lanestat[][4] = { " OK", "BAD" };
  52 
  53         const char *kind, *agent, *cycle, *event;
  54         unsigned long address;
  55 
  56         u32 mer = *kn02xa_mer;
  57         u32 ear = *kn02xa_ear;
  58         int action = MIPS_BE_FATAL;
  59 
  60         /* Ack ASAP, so that any subsequent errors get caught. */
  61         dec_kn02xa_be_ack();
  62 
  63         kind = invoker ? intstr : excstr;
  64 
  65         /* No DMA errors? */
  66         agent = cpustr;
  67 
  68         address = ear & KN02XA_EAR_ADDRESS;
  69 
  70         /* Low 256MB is decoded as memory, high -- as TC. */
  71         if (address < 0x10000000) {
  72                 cycle = mreadstr;
  73                 event = paritystr;
  74         } else {
  75                 cycle = invoker ? writestr : readstr;
  76                 event = timestr;
  77         }
  78 
  79         if (is_fixup)
  80                 action = MIPS_BE_FIXUP;
  81 
  82         if (action != MIPS_BE_FIXUP)
  83                 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
  84                         kind, agent, cycle, event, address);
  85 
  86         if (action != MIPS_BE_FIXUP && address < 0x10000000)
  87                 printk(KERN_ALERT "  Byte lane status %#3x -- "
  88                        "#3: %s, #2: %s, #1: %s, #0: %s\n",
  89                        (mer & KN02XA_MER_BYTERR) >> 8,
  90                        lanestat[(mer & KN02XA_MER_BYTERR_3) != 0],
  91                        lanestat[(mer & KN02XA_MER_BYTERR_2) != 0],
  92                        lanestat[(mer & KN02XA_MER_BYTERR_1) != 0],
  93                        lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]);
  94 
  95         return action;
  96 }
  97 
  98 int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup)
  99 {
 100         return dec_kn02xa_be_backend(regs, is_fixup, 0);
 101 }
 102 
 103 irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id)
 104 {
 105         struct pt_regs *regs = get_irq_regs();
 106         int action = dec_kn02xa_be_backend(regs, 0, 1);
 107 
 108         if (action == MIPS_BE_DISCARD)
 109                 return IRQ_HANDLED;
 110 
 111         /*
 112          * FIXME: Find the affected processes and kill them, otherwise
 113          * we must die.
 114          *
 115          * The interrupt is asynchronously delivered thus EPC and RA
 116          * may be irrelevant, but are printed for a reference.
 117          */
 118         printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
 119                regs->cp0_epc, regs->regs[31]);
 120         die("Unrecoverable bus error", regs);
 121 }
 122 
 123 
 124 void __init dec_kn02xa_be_init(void)
 125 {
 126         volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
 127 
 128         /* For KN04 we need to make sure EE (?) is enabled in the MB.  */
 129         if (current_cpu_type() == CPU_R4000SC)
 130                 *mbcs |= KN4K_MB_CSR_EE;
 131         fast_iob();
 132 
 133         /* Clear any leftover errors from the firmware. */
 134         dec_kn02xa_be_ack();
 135 }