root/arch/mips/dec/kn02-irq.c

DEFINITIONS

1. unmask_kn02_irq
2. mask_kn02_irq
3. ack_kn02_irq
4. init_kn02_irqs

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *      DECstation 5000/200 (KN02) Control and Status Register
   4  *      interrupts.
   5  *
   6  *      Copyright (c) 2002, 2003, 2005  Maciej W. Rozycki
   7  */
   8 
   9 #include <linux/init.h>
  10 #include <linux/irq.h>
  11 #include <linux/types.h>
  12 
  13 #include <asm/dec/kn02.h>
  14 
  15 
  16 /*
  17  * Bits 7:0 of the Control Register are write-only -- the
  18  * corresponding bits of the Status Register have a different
  19  * meaning.  Hence we use a cache.  It speeds up things a bit
  20  * as well.
  21  *
  22  * There is no default value -- it has to be initialized.
  23  */
  24 u32 cached_kn02_csr;
  25 
  26 static int kn02_irq_base;
  27 
  28 static void unmask_kn02_irq(struct irq_data *d)
  29 {
  30         volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
  31                                                        KN02_CSR);
  32 
  33         cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16));
  34         *csr = cached_kn02_csr;
  35 }
  36 
  37 static void mask_kn02_irq(struct irq_data *d)
  38 {
  39         volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
  40                                                        KN02_CSR);
  41 
  42         cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16));
  43         *csr = cached_kn02_csr;
  44 }
  45 
  46 static void ack_kn02_irq(struct irq_data *d)
  47 {
  48         mask_kn02_irq(d);
  49         iob();
  50 }
  51 
  52 static struct irq_chip kn02_irq_type = {
  53         .name = "KN02-CSR",
  54         .irq_ack = ack_kn02_irq,
  55         .irq_mask = mask_kn02_irq,
  56         .irq_mask_ack = ack_kn02_irq,
  57         .irq_unmask = unmask_kn02_irq,
  58 };
  59 
  60 void __init init_kn02_irqs(int base)
  61 {
  62         volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
  63                                                        KN02_CSR);
  64         int i;
  65 
  66         /* Mask interrupts. */
  67         cached_kn02_csr &= ~KN02_CSR_IOINTEN;
  68         *csr = cached_kn02_csr;
  69         iob();
  70 
  71         for (i = base; i < base + KN02_IRQ_LINES; i++)
  72                 irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
  73 
  74         kn02_irq_base = base;
  75 }