1
2 #ifndef _MVME147HW_H_
3 #define _MVME147HW_H_
4
5 #include <asm/irq.h>
6
7 typedef struct {
8 unsigned char
9 ctrl,
10 bcd_sec,
11 bcd_min,
12 bcd_hr,
13 bcd_dow,
14 bcd_dom,
15 bcd_mth,
16 bcd_year;
17 } MK48T02;
18
19 #define RTC_WRITE 0x80
20 #define RTC_READ 0x40
21 #define RTC_STOP 0x20
22
23 #define m147_rtc ((MK48T02 * volatile)0xfffe07f8)
24
25
26 struct pcc_regs {
27 volatile u_long dma_tadr;
28 volatile u_long dma_dadr;
29 volatile u_long dma_bcr;
30 volatile u_long dma_hr;
31 volatile u_short t1_preload;
32 volatile u_short t1_count;
33 volatile u_short t2_preload;
34 volatile u_short t2_count;
35 volatile u_char t1_int_cntrl;
36 volatile u_char t1_cntrl;
37 volatile u_char t2_int_cntrl;
38 volatile u_char t2_cntrl;
39 volatile u_char ac_fail;
40 volatile u_char watchdog;
41 volatile u_char lpt_intr;
42 volatile u_char lpt_cntrl;
43 volatile u_char dma_intr;
44 volatile u_char dma_cntrl;
45 volatile u_char bus_error;
46 volatile u_char dma_status;
47 volatile u_char abort;
48 volatile u_char ta_fnctl;
49 volatile u_char serial_cntrl;
50 volatile u_char general_cntrl;
51 volatile u_char lan_cntrl;
52 volatile u_char general_status;
53 volatile u_char scsi_interrupt;
54 volatile u_char slave;
55 volatile u_char soft1_cntrl;
56 volatile u_char int_base;
57 volatile u_char soft2_cntrl;
58 volatile u_char revision_level;
59 volatile u_char lpt_data;
60 volatile u_char lpt_status;
61 };
62
63 #define m147_pcc ((struct pcc_regs * volatile)0xfffe1000)
64
65
66 #define PCC_INT_ENAB 0x08
67
68 #define PCC_TIMER_INT_CLR 0x80
69 #define PCC_TIMER_CLR_OVF 0x04
70
71 #define PCC_LEVEL_ABORT 0x07
72 #define PCC_LEVEL_SERIAL 0x04
73 #define PCC_LEVEL_ETH 0x04
74 #define PCC_LEVEL_TIMER1 0x04
75 #define PCC_LEVEL_SCSI_PORT 0x04
76 #define PCC_LEVEL_SCSI_DMA 0x04
77
78 #define PCC_IRQ_AC_FAIL (IRQ_USER+0)
79 #define PCC_IRQ_BERR (IRQ_USER+1)
80 #define PCC_IRQ_ABORT (IRQ_USER+2)
81
82 #define PCC_IRQ_PRINTER (IRQ_USER+7)
83 #define PCC_IRQ_TIMER1 (IRQ_USER+8)
84 #define PCC_IRQ_TIMER2 (IRQ_USER+9)
85 #define PCC_IRQ_SOFTWARE1 (IRQ_USER+10)
86 #define PCC_IRQ_SOFTWARE2 (IRQ_USER+11)
87
88
89 #define M147_SCC_A_ADDR 0xfffe3002
90 #define M147_SCC_B_ADDR 0xfffe3000
91 #define M147_SCC_PCLK 5000000
92
93 #define MVME147_IRQ_SCSI_PORT (IRQ_USER+0x45)
94 #define MVME147_IRQ_SCSI_DMA (IRQ_USER+0x46)
95
96
97
98 #define MVME147_IRQ_TYPE_PRIO 0
99 #define MVME147_IRQ_SCC_BASE (IRQ_USER+32)
100 #define MVME147_IRQ_SCCB_TX (IRQ_USER+32)
101 #define MVME147_IRQ_SCCB_STAT (IRQ_USER+34)
102 #define MVME147_IRQ_SCCB_RX (IRQ_USER+36)
103 #define MVME147_IRQ_SCCB_SPCOND (IRQ_USER+38)
104 #define MVME147_IRQ_SCCA_TX (IRQ_USER+40)
105 #define MVME147_IRQ_SCCA_STAT (IRQ_USER+42)
106 #define MVME147_IRQ_SCCA_RX (IRQ_USER+44)
107 #define MVME147_IRQ_SCCA_SPCOND (IRQ_USER+46)
108
109 #define MVME147_LANCE_BASE 0xfffe1800
110 #define MVME147_LANCE_IRQ (IRQ_USER+4)
111
112 #define ETHERNET_ADDRESS 0xfffe0778
113
114 #endif