root/arch/m68k/include/asm/dvma.h

INCLUDED FROM

DEFINITIONS

1. dvma_map_cpu

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * include/asm-m68k/dma.h
   4  *
   5  * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
   6  *
   7  * Hacked to fit Sun3x needs by Thomas Bogendoerfer
   8  */
   9 
  10 #ifndef __M68K_DVMA_H
  11 #define __M68K_DVMA_H
  12 
  13 
  14 #define DVMA_PAGE_SHIFT 13
  15 #define DVMA_PAGE_SIZE  (1UL << DVMA_PAGE_SHIFT)
  16 #define DVMA_PAGE_MASK  (~(DVMA_PAGE_SIZE-1))
  17 #define DVMA_PAGE_ALIGN(addr)   ALIGN(addr, DVMA_PAGE_SIZE)
  18 
  19 extern void dvma_init(void);
  20 extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
  21                           int len);
  22 
  23 #define dvma_malloc(x) dvma_malloc_align(x, 0)
  24 #define dvma_map(x, y) dvma_map_align(x, y, 0)
  25 #define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
  26 #define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
  27 extern unsigned long dvma_map_align(unsigned long kaddr, int len,
  28                             int align);
  29 extern void *dvma_malloc_align(unsigned long len, unsigned long align);
  30 
  31 extern void dvma_unmap(void *baddr);
  32 extern void dvma_free(void *vaddr);
  33 
  34 
  35 #ifdef CONFIG_SUN3
  36 /* sun3 dvma page support */
  37 
  38 /* memory and pmegs potentially reserved for dvma */
  39 #define DVMA_PMEG_START 10
  40 #define DVMA_PMEG_END 16
  41 #define DVMA_START 0xf00000
  42 #define DVMA_END 0xfe0000
  43 #define DVMA_SIZE (DVMA_END-DVMA_START)
  44 #define IOMMU_TOTAL_ENTRIES 128
  45 #define IOMMU_ENTRIES 120
  46 
  47 /* empirical kludge -- dvma regions only seem to work right on 0x10000
  48    byte boundaries */
  49 #define DVMA_REGION_SIZE 0x10000
  50 #define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
  51                          ~(DVMA_REGION_SIZE-1))
  52 
  53 /* virt <-> phys conversions */
  54 #define dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
  55 #define dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
  56 #define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff)
  57 #define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000)
  58 #define dvma_vtob(x) dvma_vtop(x)
  59 #define dvma_btov(x) dvma_ptov(x)
  60 
  61 static inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr,
  62                                int len)
  63 {
  64         return 0;
  65 }
  66 
  67 #else /* Sun3x */
  68 
  69 /* sun3x dvma page support */
  70 
  71 #define DVMA_START 0x0
  72 #define DVMA_END 0xf00000
  73 #define DVMA_SIZE (DVMA_END-DVMA_START)
  74 #define IOMMU_TOTAL_ENTRIES        2048
  75 /* the prom takes the top meg */
  76 #define IOMMU_ENTRIES              (IOMMU_TOTAL_ENTRIES - 0x80)
  77 
  78 #define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff)
  79 #define dvma_btov(x) ((unsigned long)(x) | 0xff000000)
  80 
  81 extern int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len);
  82 
  83 
  84 
  85 /* everything below this line is specific to dma used for the onboard
  86    ESP scsi on sun3x */
  87 
  88 /* Structure to describe the current status of DMA registers on the Sparc */
  89 struct sparc_dma_registers {
  90   __volatile__ unsigned long cond_reg;  /* DMA condition register */
  91   __volatile__ unsigned long st_addr;   /* Start address of this transfer */
  92   __volatile__ unsigned long  cnt;      /* How many bytes to transfer */
  93   __volatile__ unsigned long dma_test;  /* DMA test register */
  94 };
  95 
  96 /* DVMA chip revisions */
  97 enum dvma_rev {
  98         dvmarev0,
  99         dvmaesc1,
 100         dvmarev1,
 101         dvmarev2,
 102         dvmarev3,
 103         dvmarevplus,
 104         dvmahme
 105 };
 106 
 107 #define DMA_HASCOUNT(rev)  ((rev)==dvmaesc1)
 108 
 109 /* Linux DMA information structure, filled during probe. */
 110 struct Linux_SBus_DMA {
 111         struct Linux_SBus_DMA *next;
 112         struct linux_sbus_device *SBus_dev;
 113         struct sparc_dma_registers *regs;
 114 
 115         /* Status, misc info */
 116         int node;                /* Prom node for this DMA device */
 117         int running;             /* Are we doing DMA now? */
 118         int allocated;           /* Are we "owned" by anyone yet? */
 119 
 120         /* Transfer information. */
 121         unsigned long addr;      /* Start address of current transfer */
 122         int nbytes;              /* Size of current transfer */
 123         int realbytes;           /* For splitting up large transfers, etc. */
 124 
 125         /* DMA revision */
 126         enum dvma_rev revision;
 127 };
 128 
 129 extern struct Linux_SBus_DMA *dma_chain;
 130 
 131 /* Broken hardware... */
 132 #define DMA_ISBROKEN(dma)    ((dma)->revision == dvmarev1)
 133 #define DMA_ISESC1(dma)      ((dma)->revision == dvmaesc1)
 134 
 135 /* Fields in the cond_reg register */
 136 /* First, the version identification bits */
 137 #define DMA_DEVICE_ID    0xf0000000        /* Device identification bits */
 138 #define DMA_VERS0        0x00000000        /* Sunray DMA version */
 139 #define DMA_ESCV1        0x40000000        /* DMA ESC Version 1 */
 140 #define DMA_VERS1        0x80000000        /* DMA rev 1 */
 141 #define DMA_VERS2        0xa0000000        /* DMA rev 2 */
 142 #define DMA_VERHME       0xb0000000        /* DMA hme gate array */
 143 #define DMA_VERSPLUS     0x90000000        /* DMA rev 1 PLUS */
 144 
 145 #define DMA_HNDL_INTR    0x00000001        /* An IRQ needs to be handled */
 146 #define DMA_HNDL_ERROR   0x00000002        /* We need to take an error */
 147 #define DMA_FIFO_ISDRAIN 0x0000000c        /* The DMA FIFO is draining */
 148 #define DMA_INT_ENAB     0x00000010        /* Turn on interrupts */
 149 #define DMA_FIFO_INV     0x00000020        /* Invalidate the FIFO */
 150 #define DMA_ACC_SZ_ERR   0x00000040        /* The access size was bad */
 151 #define DMA_FIFO_STDRAIN 0x00000040        /* DMA_VERS1 Drain the FIFO */
 152 #define DMA_RST_SCSI     0x00000080        /* Reset the SCSI controller */
 153 #define DMA_RST_ENET     DMA_RST_SCSI      /* Reset the ENET controller */
 154 #define DMA_ST_WRITE     0x00000100        /* write from device to memory */
 155 #define DMA_ENABLE       0x00000200        /* Fire up DMA, handle requests */
 156 #define DMA_PEND_READ    0x00000400        /* DMA_VERS1/0/PLUS Pending Read */
 157 #define DMA_ESC_BURST    0x00000800        /* 1=16byte 0=32byte */
 158 #define DMA_READ_AHEAD   0x00001800        /* DMA read ahead partial longword */
 159 #define DMA_DSBL_RD_DRN  0x00001000        /* No EC drain on slave reads */
 160 #define DMA_BCNT_ENAB    0x00002000        /* If on, use the byte counter */
 161 #define DMA_TERM_CNTR    0x00004000        /* Terminal counter */
 162 #define DMA_CSR_DISAB    0x00010000        /* No FIFO drains during csr */
 163 #define DMA_SCSI_DISAB   0x00020000        /* No FIFO drains during reg */
 164 #define DMA_DSBL_WR_INV  0x00020000        /* No EC inval. on slave writes */
 165 #define DMA_ADD_ENABLE   0x00040000        /* Special ESC DVMA optimization */
 166 #define DMA_E_BURST8     0x00040000        /* ENET: SBUS r/w burst size */
 167 #define DMA_BRST_SZ      0x000c0000        /* SCSI: SBUS r/w burst size */
 168 #define DMA_BRST64       0x00080000        /* SCSI: 64byte bursts (HME on UltraSparc only) */
 169 #define DMA_BRST32       0x00040000        /* SCSI: 32byte bursts */
 170 #define DMA_BRST16       0x00000000        /* SCSI: 16byte bursts */
 171 #define DMA_BRST0        0x00080000        /* SCSI: no bursts (non-HME gate arrays) */
 172 #define DMA_ADDR_DISAB   0x00100000        /* No FIFO drains during addr */
 173 #define DMA_2CLKS        0x00200000        /* Each transfer = 2 clock ticks */
 174 #define DMA_3CLKS        0x00400000        /* Each transfer = 3 clock ticks */
 175 #define DMA_EN_ENETAUI   DMA_3CLKS         /* Put lance into AUI-cable mode */
 176 #define DMA_CNTR_DISAB   0x00800000        /* No IRQ when DMA_TERM_CNTR set */
 177 #define DMA_AUTO_NADDR   0x01000000        /* Use "auto nxt addr" feature */
 178 #define DMA_SCSI_ON      0x02000000        /* Enable SCSI dma */
 179 #define DMA_PARITY_OFF   0x02000000        /* HME: disable parity checking */
 180 #define DMA_LOADED_ADDR  0x04000000        /* Address has been loaded */
 181 #define DMA_LOADED_NADDR 0x08000000        /* Next address has been loaded */
 182 
 183 /* Values describing the burst-size property from the PROM */
 184 #define DMA_BURST1       0x01
 185 #define DMA_BURST2       0x02
 186 #define DMA_BURST4       0x04
 187 #define DMA_BURST8       0x08
 188 #define DMA_BURST16      0x10
 189 #define DMA_BURST32      0x20
 190 #define DMA_BURST64      0x40
 191 #define DMA_BURSTBITS    0x7f
 192 
 193 /* Determine highest possible final transfer address given a base */
 194 #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
 195 
 196 /* Yes, I hack a lot of elisp in my spare time... */
 197 #define DMA_ERROR_P(regs)  ((((regs)->cond_reg) & DMA_HNDL_ERROR))
 198 #define DMA_IRQ_P(regs)    ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
 199 #define DMA_WRITE_P(regs)  ((((regs)->cond_reg) & DMA_ST_WRITE))
 200 #define DMA_OFF(regs)      ((((regs)->cond_reg) &= (~DMA_ENABLE)))
 201 #define DMA_INTSOFF(regs)  ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
 202 #define DMA_INTSON(regs)   ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
 203 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
 204 #define DMA_SETSTART(regs, addr)  ((((regs)->st_addr) = (char *) addr))
 205 #define DMA_BEGINDMA_W(regs) \
 206         ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
 207 #define DMA_BEGINDMA_R(regs) \
 208         ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
 209 
 210 /* For certain DMA chips, we need to disable ints upon irq entry
 211  * and turn them back on when we are done.  So in any ESP interrupt
 212  * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
 213  * when leaving the handler.  You have been warned...
 214  */
 215 #define DMA_IRQ_ENTRY(dma, dregs) do { \
 216         if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
 217    } while (0)
 218 
 219 #define DMA_IRQ_EXIT(dma, dregs) do { \
 220         if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
 221    } while(0)
 222 
 223 /* Reset the friggin' thing... */
 224 #define DMA_RESET(dma) do { \
 225         struct sparc_dma_registers *regs = dma->regs;                      \
 226         /* Let the current FIFO drain itself */                            \
 227         sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN));                         \
 228         /* Reset the logic */                                              \
 229         regs->cond_reg |= (DMA_RST_SCSI);     /* assert */                 \
 230         __delay(400);                         /* let the bits set ;) */    \
 231         regs->cond_reg &= ~(DMA_RST_SCSI);    /* de-assert */              \
 232         sparc_dma_enable_interrupts(regs);    /* Re-enable interrupts */   \
 233         /* Enable FAST transfers if available */                           \
 234         if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS;            \
 235         dma->running = 0;                                                  \
 236 } while(0)
 237 
 238 
 239 #endif /* !CONFIG_SUN3 */
 240 
 241 #endif /* !(__M68K_DVMA_H) */