This source file includes following definitions.
- Copyright
1 |
2 | fpsp.h 3.3 3.3
3 |
4
5 | Copyright (C) Motorola, Inc. 1990
6 | All Rights Reserved
7 |
8 | For details on the license for this file, please see the
9 | file, README, in this same directory.
10
11 | fpsp.h --- stack frame offsets during FPSP exception handling
12 |
13 | These equates are used to access the exception frame, the fsave
14 | frame and any local variables needed by the FPSP package.
15 |
16 | All FPSP handlers begin by executing:
17 |
18 | link a6,#-LOCAL_SIZE
19 | fsave -(a7)
20 | movem.l d0-d1/a0-a1,USER_DA(a6)
21 | fmovem.x fp0-fp3,USER_FP0(a6)
22 | fmove.l fpsr/fpcr/fpiar,USER_FPSR(a6)
23 |
24 | After initialization, the stack looks like this:
25 |
26 | A7 ---> +-------------------------------+
27 | | |
28 | | FPU fsave area |
29 | | |
30 | +-------------------------------+
31 | | |
32 | | FPSP Local Variables |
33 | | including |
34 | | saved registers |
35 | | |
36 | +-------------------------------+
37 | A6 ---> | Saved A6 |
38 | +-------------------------------+
39 | | |
40 | | Exception Frame |
41 | | |
42 | | |
43 |
44 | Positive offsets from A6 refer to the exception frame. Negative
45 | offsets refer to the Local Variable area and the fsave area.
46 | The fsave frame is also accessible from the top via A7.
47 |
48 | On exit, the handlers execute:
49 |
50 | movem.l USER_DA(a6),d0-d1/a0-a1
51 | fmovem.x USER_FP0(a6),fp0-fp3
52 | fmove.l USER_FPSR(a6),fpsr/fpcr/fpiar
53 | frestore (a7)+
54 | unlk a6
55 |
56 | and then either "bra fpsp_done" if the exception was completely
57 | handled by the package, or "bra real_xxxx" which is an external
58 | label to a routine that will process a real exception of the
59 | type that was generated. Some handlers may omit the "frestore"
60 | if the FPU state after the exception is idle.
61 |
62 | Sometimes the exception handler will transform the fsave area
63 | because it needs to report an exception back to the user. This
64 | can happen if the package is entered for an unimplemented float
65 | instruction that generates (say) an underflow. Alternatively,
66 | a second fsave frame can be pushed onto the stack and the
67 | handler exit code will reload the new frame and discard the old.
68 |
69 | The registers d0, d1, a0, a1 and fp0-fp3 are always saved and
70 | restored from the "local variable" area and can be used as
71 | temporaries. If a routine needs to change any
72 | of these registers, it should modify the saved copy and let
73 | the handler exit code restore the value.
74 |
75 |----------------------------------------------------------------------
76 |
77 | Local Variables on the stack
78 |
79 .set LOCAL_SIZE,192 | bytes needed for local variables
80 .set LV,-LOCAL_SIZE | convenient base value
81 |
82 .set USER_DA,LV+0 | save space for D0-D1,A0-A1
83 .set USER_D0,LV+0 | saved user D0
84 .set USER_D1,LV+4 | saved user D1
85 .set USER_A0,LV+8 | saved user A0
86 .set USER_A1,LV+12 | saved user A1
87 .set USER_FP0,LV+16 | saved user FP0
88 .set USER_FP1,LV+28 | saved user FP1
89 .set USER_FP2,LV+40 | saved user FP2
90 .set USER_FP3,LV+52 | saved user FP3
91 .set USER_FPCR,LV+64 | saved user FPCR
92 .set FPCR_ENABLE,USER_FPCR+2 | FPCR exception enable
93 .set FPCR_MODE,USER_FPCR+3 | FPCR rounding mode control
94 .set USER_FPSR,LV+68 | saved user FPSR
95 .set FPSR_CC,USER_FPSR+0 | FPSR condition code
96 .set FPSR_QBYTE,USER_FPSR+1 | FPSR quotient
97 .set FPSR_EXCEPT,USER_FPSR+2 | FPSR exception
98 .set FPSR_AEXCEPT,USER_FPSR+3 | FPSR accrued exception
99 .set USER_FPIAR,LV+72 | saved user FPIAR
100 .set FP_SCR1,LV+76 | room for a temporary float value
101 .set FP_SCR2,LV+92 | room for a temporary float value
102 .set L_SCR1,LV+108 | room for a temporary long value
103 .set L_SCR2,LV+112 | room for a temporary long value
104 .set STORE_FLG,LV+116
105 .set BINDEC_FLG,LV+117 | used in bindec
106 .set DNRM_FLG,LV+118 | used in res_func
107 .set RES_FLG,LV+119 | used in res_func
108 .set DY_MO_FLG,LV+120 | dyadic/monadic flag
109 .set UFLG_TMP,LV+121 | temporary for uflag errata
110 .set CU_ONLY,LV+122 | cu-only flag
111 .set VER_TMP,LV+123 | temp holding for version number
112 .set L_SCR3,LV+124 | room for a temporary long value
113 .set FP_SCR3,LV+128 | room for a temporary float value
114 .set FP_SCR4,LV+144 | room for a temporary float value
115 .set FP_SCR5,LV+160 | room for a temporary float value
116 .set FP_SCR6,LV+176
117 |
118 |NEXT equ LV+192 ;need to increase LOCAL_SIZE
119 |
120 |--------------------------------------------------------------------------
121 |
122 | fsave offsets and bit definitions
123 |
124 | Offsets are defined from the end of an fsave because the last 10
125 | words of a busy frame are the same as the unimplemented frame.
126 |
127 .set CU_SAVEPC,LV-92 | micro-pc for CU (1 byte)
128 .set FPR_DIRTY_BITS,LV-91 | fpr dirty bits
129 |
130 .set WBTEMP,LV-76 | write back temp (12 bytes)
131 .set WBTEMP_EX,WBTEMP | wbtemp sign and exponent (2 bytes)
132 .set WBTEMP_HI,WBTEMP+4 | wbtemp mantissa [63:32] (4 bytes)
133 .set WBTEMP_LO,WBTEMP+8 | wbtemp mantissa [31:00] (4 bytes)
134 |
135 .set WBTEMP_SGN,WBTEMP+2 | used to store sign
136 |
137 .set FPSR_SHADOW,LV-64 | fpsr shadow reg
138 |
139 .set FPIARCU,LV-60 | Instr. addr. reg. for CU (4 bytes)
140 |
141 .set CMDREG2B,LV-52 | cmd reg for machine 2
142 .set CMDREG3B,LV-48 | cmd reg for E3 exceptions (2 bytes)
143 |
144 .set NMNEXC,LV-44 | NMNEXC (unsup,snan bits only)
145 .set nmn_unsup_bit,1 |
146 .set nmn_snan_bit,0 |
147 |
148 .set NMCEXC,LV-43 | NMNEXC & NMCEXC
149 .set nmn_operr_bit,7
150 .set nmn_ovfl_bit,6
151 .set nmn_unfl_bit,5
152 .set nmc_unsup_bit,4
153 .set nmc_snan_bit,3
154 .set nmc_operr_bit,2
155 .set nmc_ovfl_bit,1
156 .set nmc_unfl_bit,0
157 |
158 .set STAG,LV-40 | source tag (1 byte)
159 .set WBTEMP_GRS,LV-40 | alias wbtemp guard, round, sticky
160 .set guard_bit,1 | guard bit is bit number 1
161 .set round_bit,0 | round bit is bit number 0
162 .set stag_mask,0xE0 | upper 3 bits are source tag type
163 .set denorm_bit,7 | bit determines if denorm or unnorm
164 .set etemp15_bit,4 | etemp exponent bit #15
165 .set wbtemp66_bit,2 | wbtemp mantissa bit #66
166 .set wbtemp1_bit,1 | wbtemp mantissa bit #1
167 .set wbtemp0_bit,0 | wbtemp mantissa bit #0
168 |
169 .set STICKY,LV-39 | holds sticky bit
170 .set sticky_bit,7
171 |
172 .set CMDREG1B,LV-36 | cmd reg for E1 exceptions (2 bytes)
173 .set kfact_bit,12 | distinguishes static/dynamic k-factor
174 | ;on packed move outs. NOTE: this
175 | ;equate only works when CMDREG1B is in
176 | ;a register.
177 |
178 .set CMDWORD,LV-35 | command word in cmd1b
179 .set direction_bit,5 | bit 0 in opclass
180 .set size_bit2,12 | bit 2 in size field
181 |
182 .set DTAG,LV-32 | dest tag (1 byte)
183 .set dtag_mask,0xE0 | upper 3 bits are dest type tag
184 .set fptemp15_bit,4 | fptemp exponent bit #15
185 |
186 .set WB_BYTE,LV-31 | holds WBTE15 bit (1 byte)
187 .set wbtemp15_bit,4 | wbtemp exponent bit #15
188 |
189 .set E_BYTE,LV-28 | holds E1 and E3 bits (1 byte)
190 .set E1,2 | which bit is E1 flag
191 .set E3,1 | which bit is E3 flag
192 .set SFLAG,0 | which bit is S flag
193 |
194 .set T_BYTE,LV-27 | holds T and U bits (1 byte)
195 .set XFLAG,7 | which bit is X flag
196 .set UFLAG,5 | which bit is U flag
197 .set TFLAG,4 | which bit is T flag
198 |
199 .set FPTEMP,LV-24 | fptemp (12 bytes)
200 .set FPTEMP_EX,FPTEMP | fptemp sign and exponent (2 bytes)
201 .set FPTEMP_HI,FPTEMP+4 | fptemp mantissa [63:32] (4 bytes)
202 .set FPTEMP_LO,FPTEMP+8 | fptemp mantissa [31:00] (4 bytes)
203 |
204 .set FPTEMP_SGN,FPTEMP+2 | used to store sign
205 |
206 .set ETEMP,LV-12 | etemp (12 bytes)
207 .set ETEMP_EX,ETEMP | etemp sign and exponent (2 bytes)
208 .set ETEMP_HI,ETEMP+4 | etemp mantissa [63:32] (4 bytes)
209 .set ETEMP_LO,ETEMP+8 | etemp mantissa [31:00] (4 bytes)
210 |
211 .set ETEMP_SGN,ETEMP+2 | used to store sign
212 |
213 .set EXC_SR,4 | exception frame status register
214 .set EXC_PC,6 | exception frame program counter
215 .set EXC_VEC,10 | exception frame vector (format+vector#)
216 .set EXC_EA,12 | exception frame effective address
217 |
218 |--------------------------------------------------------------------------
219 |
220 | FPSR/FPCR bits
221 |
222 .set neg_bit,3 | negative result
223 .set z_bit,2 | zero result
224 .set inf_bit,1 | infinity result
225 .set nan_bit,0 | not-a-number result
226 |
227 .set q_sn_bit,7 | sign bit of quotient byte
228 |
229 .set bsun_bit,7 | branch on unordered
230 .set snan_bit,6 | signalling nan
231 .set operr_bit,5 | operand error
232 .set ovfl_bit,4 | overflow
233 .set unfl_bit,3 | underflow
234 .set dz_bit,2 | divide by zero
235 .set inex2_bit,1 | inexact result 2
236 .set inex1_bit,0 | inexact result 1
237 |
238 .set aiop_bit,7 | accrued illegal operation
239 .set aovfl_bit,6 | accrued overflow
240 .set aunfl_bit,5 | accrued underflow
241 .set adz_bit,4 | accrued divide by zero
242 .set ainex_bit,3 | accrued inexact
243 |
244 | FPSR individual bit masks
245 |
246 .set neg_mask,0x08000000
247 .set z_mask,0x04000000
248 .set inf_mask,0x02000000
249 .set nan_mask,0x01000000
250 |
251 .set bsun_mask,0x00008000 |
252 .set snan_mask,0x00004000
253 .set operr_mask,0x00002000
254 .set ovfl_mask,0x00001000
255 .set unfl_mask,0x00000800
256 .set dz_mask,0x00000400
257 .set inex2_mask,0x00000200
258 .set inex1_mask,0x00000100
259 |
260 .set aiop_mask,0x00000080 | accrued illegal operation
261 .set aovfl_mask,0x00000040 | accrued overflow
262 .set aunfl_mask,0x00000020 | accrued underflow
263 .set adz_mask,0x00000010 | accrued divide by zero
264 .set ainex_mask,0x00000008 | accrued inexact
265 |
266 | FPSR combinations used in the FPSP
267 |
268 .set dzinf_mask,inf_mask+dz_mask+adz_mask
269 .set opnan_mask,nan_mask+operr_mask+aiop_mask
270 .set nzi_mask,0x01ffffff | clears N, Z, and I
271 .set unfinx_mask,unfl_mask+inex2_mask+aunfl_mask+ainex_mask
272 .set unf2inx_mask,unfl_mask+inex2_mask+ainex_mask
273 .set ovfinx_mask,ovfl_mask+inex2_mask+aovfl_mask+ainex_mask
274 .set inx1a_mask,inex1_mask+ainex_mask
275 .set inx2a_mask,inex2_mask+ainex_mask
276 .set snaniop_mask,nan_mask+snan_mask+aiop_mask
277 .set naniop_mask,nan_mask+aiop_mask
278 .set neginf_mask,neg_mask+inf_mask
279 .set infaiop_mask,inf_mask+aiop_mask
280 .set negz_mask,neg_mask+z_mask
281 .set opaop_mask,operr_mask+aiop_mask
282 .set unfl_inx_mask,unfl_mask+aunfl_mask+ainex_mask
283 .set ovfl_inx_mask,ovfl_mask+aovfl_mask+ainex_mask
284 |
285 |--------------------------------------------------------------------------
286 |
287 | FPCR rounding modes
288 |
289 .set x_mode,0x00 | round to extended
290 .set s_mode,0x40 | round to single
291 .set d_mode,0x80 | round to double
292 |
293 .set rn_mode,0x00 | round nearest
294 .set rz_mode,0x10 | round to zero
295 .set rm_mode,0x20 | round to minus infinity
296 .set rp_mode,0x30 | round to plus infinity
297 |
298 |--------------------------------------------------------------------------
299 |
300 | Miscellaneous equates
301 |
302 .set signan_bit,6 | signalling nan bit in mantissa
303 .set sign_bit,7
304 |
305 .set rnd_stky_bit,29 | round/sticky bit of mantissa
306 | this can only be used if in a data register
307 .set sx_mask,0x01800000 | set s and x bits in word $48
308 |
309 .set LOCAL_EX,0
310 .set LOCAL_SGN,2
311 .set LOCAL_HI,4
312 .set LOCAL_LO,8
313 .set LOCAL_GRS,12 | valid ONLY for FP_SCR1, FP_SCR2
314 |
315 |
316 .set norm_tag,0x00 | tag bits in {7:5} position
317 .set zero_tag,0x20
318 .set inf_tag,0x40
319 .set nan_tag,0x60
320 .set dnrm_tag,0x80
321 |
322 | fsave sizes and formats
323 |
324 .set VER_4,0x40 | fpsp compatible version numbers
325 | are in the $40s {$40-$4f}
326 .set VER_40,0x40 | original version number
327 .set VER_41,0x41 | revision version number
328 |
329 .set BUSY_SIZE,100 | size of busy frame
330 .set BUSY_FRAME,LV-BUSY_SIZE | start of busy frame
331 |
332 .set UNIMP_40_SIZE,44 | size of orig unimp frame
333 .set UNIMP_41_SIZE,52 | size of rev unimp frame
334 |
335 .set IDLE_SIZE,4 | size of idle frame
336 .set IDLE_FRAME,LV-IDLE_SIZE | start of idle frame
337 |
338 | exception vectors
339 |
340 .set TRACE_VEC,0x2024 | trace trap
341 .set FLINE_VEC,0x002C | real F-line
342 .set UNIMP_VEC,0x202C | unimplemented
343 .set INEX_VEC,0x00C4
344 |
345 .set dbl_thresh,0x3C01
346 .set sgl_thresh,0x3F81
347 |