root/arch/unicore32/mm/proc-macros.S

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * linux/arch/unicore32/mm/proc-macros.S
   4  *
   5  * Code specific to PKUnity SoC and UniCore ISA
   6  *
   7  * Copyright (C) 2001-2010 GUAN Xue-tao
   8  *
   9  * We need constants.h for:
  10  *  VMA_VM_MM
  11  *  VMA_VM_FLAGS
  12  *  VM_EXEC
  13  */
  14 #include <generated/asm-offsets.h>
  15 #include <asm/thread_info.h>
  16 #include <asm/memory.h>
  17 
  18 /*
  19  * the cache line sizes of the I and D cache are the same
  20  */
  21 #define CACHE_LINESIZE  32
  22 
  23 /*
  24  * This is the maximum size of an area which will be invalidated
  25  * using the single invalidate entry instructions.  Anything larger
  26  * than this, and we go for the whole cache.
  27  *
  28  * This value should be chosen such that we choose the cheapest
  29  * alternative.
  30  */
  31 #ifdef CONFIG_CPU_UCV2
  32 #define MAX_AREA_SIZE   0x800           /* 64 cache line */
  33 #endif
  34 
  35 /*
  36  * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
  37  */
  38         .macro  vma_vm_mm, rd, rn
  39         ldw     \rd, [\rn+], #VMA_VM_MM
  40         .endm
  41 
  42 /*
  43  * vma_vm_flags - get vma->vm_flags
  44  */
  45         .macro  vma_vm_flags, rd, rn
  46         ldw     \rd, [\rn+], #VMA_VM_FLAGS
  47         .endm
  48 
  49         .macro  tsk_mm, rd, rn
  50         ldw     \rd, [\rn+], #TI_TASK
  51         ldw     \rd, [\rd+], #TSK_ACTIVE_MM
  52         .endm
  53 
  54 /*
  55  * act_mm - get current->active_mm
  56  */
  57         .macro  act_mm, rd
  58         andn    \rd, sp, #8128
  59         andn    \rd, \rd, #63
  60         ldw     \rd, [\rd+], #TI_TASK
  61         ldw     \rd, [\rd+], #TSK_ACTIVE_MM
  62         .endm
  63 
  64 /*
  65  * mmid - get context id from mm pointer (mm->context.id)
  66  */
  67         .macro  mmid, rd, rn
  68         ldw     \rd, [\rn+], #MM_CONTEXT_ID
  69         .endm
  70 
  71 /*
  72  * mask_asid - mask the ASID from the context ID
  73  */
  74         .macro  asid, rd, rn
  75         and     \rd, \rn, #255
  76         .endm
  77 
  78         .macro  crval, clear, mmuset, ucset
  79         .word   \clear
  80         .word   \mmuset
  81         .endm
  82 
  83 #ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
  84 /*
  85  * va2pa va, pa, tbl, msk, off, err
  86  *      This macro is used to translate virtual address to its physical address.
  87  *
  88  *      va: virtual address
  89  *      pa: physical address, result is stored in this register
  90  *      tbl, msk, off:  temp registers, will be destroyed
  91  *      err: jump to error label if the physical address not exist
  92  * NOTE: all regs must be different
  93  */
  94         .macro  va2pa, va, pa, tbl, msk, off, err=990f
  95         movc    \pa, p0.c2, #0
  96         mov     \off, \va >> #22                @ off <- index of 1st page table
  97         adr     \tbl, 910f                      @ tbl <- table of 1st page table
  98 900:                                            @ ---- handle 1, 2 page table
  99         add     \pa, \pa, #PAGE_OFFSET          @ pa <- virt addr of page table
 100         ldw     \pa, [\pa+], \off << #2         @ pa <- the content of pt
 101         cand.a  \pa, #4                         @ test exist bit
 102         beq     \err                            @ if not exist
 103         and     \off, \pa, #3                   @ off <- the last 2 bits
 104         add     \tbl, \tbl, \off << #3          @ cmove table pointer
 105         ldw     \msk, [\tbl+], #0               @ get the mask
 106         ldw     pc, [\tbl+], #4
 107 930:                                            @ ---- handle 2nd page table
 108         and     \pa, \pa, \msk                  @ pa <- phys addr of 2nd pt
 109         mov     \off, \va << #10
 110         cntlo   \tbl, \msk                      @ use tbl as temp reg
 111         mov     \off, \off >> \tbl
 112         mov     \off, \off >> #2                @ off <- index of 2nd pt
 113         adr     \tbl, 920f                      @ tbl <- table of 2nd pt
 114         b       900b
 115 910:                                            @ 1st level page table
 116         .word   0xfffff000, 930b                @ second level page table
 117         .word   0xfffffc00, 930b                @ second level large page table
 118         .word   0x00000000, \err                @ invalid
 119         .word   0xffc00000, 980f                @ super page
 120 
 121 920:                                            @ 2nd level page table
 122         .word   0xfffff000, 980f                @ page
 123         .word   0xffffc000, 980f                @ middle page
 124         .word   0xffff0000, 980f                @ large page
 125         .word   0x00000000, \err                @ invalid
 126 980:
 127         andn    \tbl, \va, \msk
 128         and     \pa, \pa, \msk
 129         or      \pa, \pa, \tbl
 130 990:
 131         .endm
 132 #endif
 133 
 134         .macro dcacheline_flush, addr, t1, t2
 135         mov     \t1, \addr << #20
 136         ldw     \t2, =_stext                    @ _stext must ALIGN(4096)
 137         add     \t2, \t2, \t1 >> #20
 138         ldw     \t1, [\t2+], #0x0000
 139         ldw     \t1, [\t2+], #0x1000
 140         ldw     \t1, [\t2+], #0x2000
 141         ldw     \t1, [\t2+], #0x3000
 142         .endm