root/arch/unicore32/include/mach/regs-umal.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * PKUnity Ultra Media Access Layer (UMAL) Ethernet MAC Registers
   4  */
   5 
   6 /* MAC module of UMAL */
   7 /* UMAL's MAC module includes G/MII interface, several additional PHY
   8  * interfaces, and MAC control sub-layer, which provides support for control
   9  * frames (e.g. PAUSE frames).
  10  */
  11 /*
  12  * TX/RX reset and control UMAL_CFG1
  13  */
  14 #define UMAL_CFG1               (PKUNITY_UMAL_BASE + 0x0000)
  15 /*
  16  * MAC interface mode control UMAL_CFG2
  17  */
  18 #define UMAL_CFG2               (PKUNITY_UMAL_BASE + 0x0004)
  19 /*
  20  * Inter Packet/Frame Gap UMAL_IPGIFG
  21  */
  22 #define UMAL_IPGIFG             (PKUNITY_UMAL_BASE + 0x0008)
  23 /*
  24  * Collision retry or backoff UMAL_HALFDUPLEX
  25  */
  26 #define UMAL_HALFDUPLEX         (PKUNITY_UMAL_BASE + 0x000c)
  27 /*
  28  * Maximum Frame Length UMAL_MAXFRAME
  29  */
  30 #define UMAL_MAXFRAME           (PKUNITY_UMAL_BASE + 0x0010)
  31 /*
  32  * Test Regsiter UMAL_TESTREG
  33  */
  34 #define UMAL_TESTREG            (PKUNITY_UMAL_BASE + 0x001c)
  35 /*
  36  * MII Management Configure UMAL_MIICFG
  37  */
  38 #define UMAL_MIICFG             (PKUNITY_UMAL_BASE + 0x0020)
  39 /*
  40  * MII Management Command UMAL_MIICMD
  41  */
  42 #define UMAL_MIICMD             (PKUNITY_UMAL_BASE + 0x0024)
  43 /*
  44  * MII Management Address UMAL_MIIADDR
  45  */
  46 #define UMAL_MIIADDR            (PKUNITY_UMAL_BASE + 0x0028)
  47 /*
  48  * MII Management Control UMAL_MIICTRL
  49  */
  50 #define UMAL_MIICTRL            (PKUNITY_UMAL_BASE + 0x002c)
  51 /*
  52  * MII Management Status UMAL_MIISTATUS
  53  */
  54 #define UMAL_MIISTATUS          (PKUNITY_UMAL_BASE + 0x0030)
  55 /*
  56  * MII Management Indicator UMAL_MIIIDCT
  57  */
  58 #define UMAL_MIIIDCT            (PKUNITY_UMAL_BASE + 0x0034)
  59 /*
  60  * Interface Control UMAL_IFCTRL
  61  */
  62 #define UMAL_IFCTRL             (PKUNITY_UMAL_BASE + 0x0038)
  63 /*
  64  * Interface Status UMAL_IFSTATUS
  65  */
  66 #define UMAL_IFSTATUS           (PKUNITY_UMAL_BASE + 0x003c)
  67 /*
  68  * MAC address (high 4 bytes) UMAL_STADDR1
  69  */
  70 #define UMAL_STADDR1            (PKUNITY_UMAL_BASE + 0x0040)
  71 /*
  72  * MAC address (low 2 bytes) UMAL_STADDR2
  73  */
  74 #define UMAL_STADDR2            (PKUNITY_UMAL_BASE + 0x0044)
  75 
  76 /* FIFO MODULE OF UMAL */
  77 /* UMAL's FIFO module provides data queuing for increased system level
  78  * throughput
  79  */
  80 #define UMAL_FIFOCFG0           (PKUNITY_UMAL_BASE + 0x0048)
  81 #define UMAL_FIFOCFG1           (PKUNITY_UMAL_BASE + 0x004c)
  82 #define UMAL_FIFOCFG2           (PKUNITY_UMAL_BASE + 0x0050)
  83 #define UMAL_FIFOCFG3           (PKUNITY_UMAL_BASE + 0x0054)
  84 #define UMAL_FIFOCFG4           (PKUNITY_UMAL_BASE + 0x0058)
  85 #define UMAL_FIFOCFG5           (PKUNITY_UMAL_BASE + 0x005c)
  86 #define UMAL_FIFORAM0           (PKUNITY_UMAL_BASE + 0x0060)
  87 #define UMAL_FIFORAM1           (PKUNITY_UMAL_BASE + 0x0064)
  88 #define UMAL_FIFORAM2           (PKUNITY_UMAL_BASE + 0x0068)
  89 #define UMAL_FIFORAM3           (PKUNITY_UMAL_BASE + 0x006c)
  90 #define UMAL_FIFORAM4           (PKUNITY_UMAL_BASE + 0x0070)
  91 #define UMAL_FIFORAM5           (PKUNITY_UMAL_BASE + 0x0074)
  92 #define UMAL_FIFORAM6           (PKUNITY_UMAL_BASE + 0x0078)
  93 #define UMAL_FIFORAM7           (PKUNITY_UMAL_BASE + 0x007c)
  94 
  95 /* MAHBE MODULE OF UMAL */
  96 /* UMAL's MAHBE module interfaces to the host system through 32-bit AHB Master
  97  * and Slave ports.Registers within the M-AHBE provide Control and Status
  98  * information concerning these transfers.
  99  */
 100 /*
 101  * Transmit Control UMAL_DMATxCtrl
 102  */
 103 #define UMAL_DMATxCtrl          (PKUNITY_UMAL_BASE + 0x0180)
 104 /*
 105  * Pointer to TX Descripter UMAL_DMATxDescriptor
 106  */
 107 #define UMAL_DMATxDescriptor    (PKUNITY_UMAL_BASE + 0x0184)
 108 /*
 109  * Status of Tx Packet Transfers UMAL_DMATxStatus
 110  */
 111 #define UMAL_DMATxStatus        (PKUNITY_UMAL_BASE + 0x0188)
 112 /*
 113  * Receive Control UMAL_DMARxCtrl
 114  */
 115 #define UMAL_DMARxCtrl          (PKUNITY_UMAL_BASE + 0x018c)
 116 /*
 117  * Pointer to Rx Descriptor UMAL_DMARxDescriptor
 118  */
 119 #define UMAL_DMARxDescriptor    (PKUNITY_UMAL_BASE + 0x0190)
 120 /*
 121  * Status of Rx Packet Transfers UMAL_DMARxStatus
 122  */
 123 #define UMAL_DMARxStatus        (PKUNITY_UMAL_BASE + 0x0194)
 124 /*
 125  * Interrupt Mask UMAL_DMAIntrMask
 126  */
 127 #define UMAL_DMAIntrMask        (PKUNITY_UMAL_BASE + 0x0198)
 128 /*
 129  * Interrupts, read only UMAL_DMAInterrupt
 130  */
 131 #define UMAL_DMAInterrupt       (PKUNITY_UMAL_BASE + 0x019c)
 132 
 133 /*
 134  * Commands for UMAL_CFG1 register
 135  */
 136 #define UMAL_CFG1_TXENABLE      FIELD(1, 1, 0)
 137 #define UMAL_CFG1_RXENABLE      FIELD(1, 1, 2)
 138 #define UMAL_CFG1_TXFLOWCTL     FIELD(1, 1, 4)
 139 #define UMAL_CFG1_RXFLOWCTL     FIELD(1, 1, 5)
 140 #define UMAL_CFG1_CONFLPBK      FIELD(1, 1, 8)
 141 #define UMAL_CFG1_RESET         FIELD(1, 1, 31)
 142 #define UMAL_CFG1_CONFFLCTL     (MAC_TX_FLOW_CTL | MAC_RX_FLOW_CTL)
 143 
 144 /*
 145  * Commands for UMAL_CFG2 register
 146  */
 147 #define UMAL_CFG2_FULLDUPLEX    FIELD(1, 1, 0)
 148 #define UMAL_CFG2_CRCENABLE     FIELD(1, 1, 1)
 149 #define UMAL_CFG2_PADCRC        FIELD(1, 1, 2)
 150 #define UMAL_CFG2_LENGTHCHECK   FIELD(1, 1, 4)
 151 #define UMAL_CFG2_MODEMASK      FMASK(2, 8)
 152 #define UMAL_CFG2_NIBBLEMODE    FIELD(1, 2, 8)
 153 #define UMAL_CFG2_BYTEMODE      FIELD(2, 2, 8)
 154 #define UMAL_CFG2_PREAMBLENMASK FMASK(4, 12)
 155 #define UMAL_CFG2_DEFPREAMBLEN  FIELD(7, 4, 12)
 156 #define UMAL_CFG2_FD100         (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_NIBBLEMODE \
 157                                 | UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \
 158                                 | UMAL_CFG2_CRCENABLE | UMAL_CFG2_FULLDUPLEX)
 159 #define UMAL_CFG2_FD1000        (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_BYTEMODE \
 160                                 | UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \
 161                                 | UMAL_CFG2_CRCENABLE | UMAL_CFG2_FULLDUPLEX)
 162 #define UMAL_CFG2_HD100         (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_NIBBLEMODE \
 163                                 | UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \
 164                                 | UMAL_CFG2_CRCENABLE)
 165 
 166 /*
 167  * Command for UMAL_IFCTRL register
 168  */
 169 #define UMAL_IFCTRL_RESET       FIELD(1, 1, 31)
 170 
 171 /*
 172  * Command for UMAL_MIICFG register
 173  */
 174 #define UMAL_MIICFG_RESET       FIELD(1, 1, 31)
 175 
 176 /*
 177  * Command for UMAL_MIICMD register
 178  */
 179 #define UMAL_MIICMD_READ        FIELD(1, 1, 0)
 180 
 181 /*
 182  * Command for UMAL_MIIIDCT register
 183  */
 184 #define UMAL_MIIIDCT_BUSY       FIELD(1, 1, 0)
 185 #define UMAL_MIIIDCT_NOTVALID   FIELD(1, 1, 2)
 186 
 187 /*
 188  * Commands for DMATxCtrl regesters
 189  */
 190 #define UMAL_DMA_Enable         FIELD(1, 1, 0)
 191 
 192 /*
 193  * Commands for DMARxCtrl regesters
 194  */
 195 #define UMAL_DMAIntrMask_ENABLEHALFWORD FIELD(1, 1, 16)
 196 
 197 /*
 198  * Command for DMARxStatus
 199  */
 200 #define CLR_RX_BUS_ERR          FIELD(1, 1, 3)
 201 #define CLR_RX_OVERFLOW         FIELD(1, 1, 2)
 202 #define CLR_RX_PKT              FIELD(1, 1, 0)
 203 
 204 /*
 205  * Command for DMATxStatus
 206  */
 207 #define CLR_TX_BUS_ERR          FIELD(1, 1, 3)
 208 #define CLR_TX_UNDERRUN         FIELD(1, 1, 1)
 209 #define CLR_TX_PKT              FIELD(1, 1, 0)
 210 
 211 /*
 212  * Commands for DMAIntrMask and DMAInterrupt register
 213  */
 214 #define INT_RX_MASK             FIELD(0xd, 4, 4)
 215 #define INT_TX_MASK             FIELD(0xb, 4, 0)
 216 
 217 #define INT_RX_BUS_ERR          FIELD(1, 1, 7)
 218 #define INT_RX_OVERFLOW         FIELD(1, 1, 6)
 219 #define INT_RX_PKT              FIELD(1, 1, 4)
 220 #define INT_TX_BUS_ERR          FIELD(1, 1, 3)
 221 #define INT_TX_UNDERRUN         FIELD(1, 1, 1)
 222 #define INT_TX_PKT              FIELD(1, 1, 0)
 223 
 224 /*
 225  * MARCOS of UMAL's descriptors
 226  */
 227 #define UMAL_DESC_PACKETSIZE_EMPTY      FIELD(1, 1, 31)
 228 #define UMAL_DESC_PACKETSIZE_NONEMPTY   FIELD(0, 1, 31)
 229 #define UMAL_DESC_PACKETSIZE_SIZEMASK   FMASK(12, 0)
 230