root/arch/unicore32/include/mach/regs-pci.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * PKUnity AHB-PCI Bridge Registers
   4  */
   5 
   6 /*
   7  * AHB/PCI fixed physical address for pci addess configuration
   8  */
   9 /*
  10  * PCICFG Bridge Base Reg.
  11  */
  12 #define PCICFG_BRIBASE          (PKUNITY_PCICFG_BASE + 0x0000)
  13 /*
  14  * PCICFG Address Reg.
  15  */
  16 #define PCICFG_ADDR             (PKUNITY_PCICFG_BASE + 0x0004)
  17 /*
  18  * PCICFG Address Reg.
  19  */
  20 #define PCICFG_DATA             (PKUNITY_PCICFG_BASE + 0x0008)
  21 
  22 /*
  23  * PCI Bridge configuration space
  24  */
  25 #define PCIBRI_ID               (PKUNITY_PCIBRI_BASE + 0x0000)
  26 #define PCIBRI_CMD              (PKUNITY_PCIBRI_BASE + 0x0004)
  27 #define PCIBRI_CLASS            (PKUNITY_PCIBRI_BASE + 0x0008)
  28 #define PCIBRI_LTR              (PKUNITY_PCIBRI_BASE + 0x000C)
  29 #define PCIBRI_BAR0             (PKUNITY_PCIBRI_BASE + 0x0010)
  30 #define PCIBRI_BAR1             (PKUNITY_PCIBRI_BASE + 0x0014)
  31 #define PCIBRI_BAR2             (PKUNITY_PCIBRI_BASE + 0x0018)
  32 #define PCIBRI_BAR3             (PKUNITY_PCIBRI_BASE + 0x001C)
  33 #define PCIBRI_BAR4             (PKUNITY_PCIBRI_BASE + 0x0020)
  34 #define PCIBRI_BAR5             (PKUNITY_PCIBRI_BASE + 0x0024)
  35 
  36 #define PCIBRI_PCICTL0          (PKUNITY_PCIBRI_BASE + 0x0100)
  37 #define PCIBRI_PCIBAR0          (PKUNITY_PCIBRI_BASE + 0x0104)
  38 #define PCIBRI_PCIAMR0          (PKUNITY_PCIBRI_BASE + 0x0108)
  39 #define PCIBRI_PCITAR0          (PKUNITY_PCIBRI_BASE + 0x010C)
  40 #define PCIBRI_PCICTL1          (PKUNITY_PCIBRI_BASE + 0x0110)
  41 #define PCIBRI_PCIBAR1          (PKUNITY_PCIBRI_BASE + 0x0114)
  42 #define PCIBRI_PCIAMR1          (PKUNITY_PCIBRI_BASE + 0x0118)
  43 #define PCIBRI_PCITAR1          (PKUNITY_PCIBRI_BASE + 0x011C)
  44 #define PCIBRI_PCICTL2          (PKUNITY_PCIBRI_BASE + 0x0120)
  45 #define PCIBRI_PCIBAR2          (PKUNITY_PCIBRI_BASE + 0x0124)
  46 #define PCIBRI_PCIAMR2          (PKUNITY_PCIBRI_BASE + 0x0128)
  47 #define PCIBRI_PCITAR2          (PKUNITY_PCIBRI_BASE + 0x012C)
  48 #define PCIBRI_PCICTL3          (PKUNITY_PCIBRI_BASE + 0x0130)
  49 #define PCIBRI_PCIBAR3          (PKUNITY_PCIBRI_BASE + 0x0134)
  50 #define PCIBRI_PCIAMR3          (PKUNITY_PCIBRI_BASE + 0x0138)
  51 #define PCIBRI_PCITAR3          (PKUNITY_PCIBRI_BASE + 0x013C)
  52 #define PCIBRI_PCICTL4          (PKUNITY_PCIBRI_BASE + 0x0140)
  53 #define PCIBRI_PCIBAR4          (PKUNITY_PCIBRI_BASE + 0x0144)
  54 #define PCIBRI_PCIAMR4          (PKUNITY_PCIBRI_BASE + 0x0148)
  55 #define PCIBRI_PCITAR4          (PKUNITY_PCIBRI_BASE + 0x014C)
  56 #define PCIBRI_PCICTL5          (PKUNITY_PCIBRI_BASE + 0x0150)
  57 #define PCIBRI_PCIBAR5          (PKUNITY_PCIBRI_BASE + 0x0154)
  58 #define PCIBRI_PCIAMR5          (PKUNITY_PCIBRI_BASE + 0x0158)
  59 #define PCIBRI_PCITAR5          (PKUNITY_PCIBRI_BASE + 0x015C)
  60 
  61 #define PCIBRI_AHBCTL0          (PKUNITY_PCIBRI_BASE + 0x0180)
  62 #define PCIBRI_AHBBAR0          (PKUNITY_PCIBRI_BASE + 0x0184)
  63 #define PCIBRI_AHBAMR0          (PKUNITY_PCIBRI_BASE + 0x0188)
  64 #define PCIBRI_AHBTAR0          (PKUNITY_PCIBRI_BASE + 0x018C)
  65 #define PCIBRI_AHBCTL1          (PKUNITY_PCIBRI_BASE + 0x0190)
  66 #define PCIBRI_AHBBAR1          (PKUNITY_PCIBRI_BASE + 0x0194)
  67 #define PCIBRI_AHBAMR1          (PKUNITY_PCIBRI_BASE + 0x0198)
  68 #define PCIBRI_AHBTAR1          (PKUNITY_PCIBRI_BASE + 0x019C)
  69 #define PCIBRI_AHBCTL2          (PKUNITY_PCIBRI_BASE + 0x01A0)
  70 #define PCIBRI_AHBBAR2          (PKUNITY_PCIBRI_BASE + 0x01A4)
  71 #define PCIBRI_AHBAMR2          (PKUNITY_PCIBRI_BASE + 0x01A8)
  72 #define PCIBRI_AHBTAR2          (PKUNITY_PCIBRI_BASE + 0x01AC)
  73 #define PCIBRI_AHBCTL3          (PKUNITY_PCIBRI_BASE + 0x01B0)
  74 #define PCIBRI_AHBBAR3          (PKUNITY_PCIBRI_BASE + 0x01B4)
  75 #define PCIBRI_AHBAMR3          (PKUNITY_PCIBRI_BASE + 0x01B8)
  76 #define PCIBRI_AHBTAR3          (PKUNITY_PCIBRI_BASE + 0x01BC)
  77 #define PCIBRI_AHBCTL4          (PKUNITY_PCIBRI_BASE + 0x01C0)
  78 #define PCIBRI_AHBBAR4          (PKUNITY_PCIBRI_BASE + 0x01C4)
  79 #define PCIBRI_AHBAMR4          (PKUNITY_PCIBRI_BASE + 0x01C8)
  80 #define PCIBRI_AHBTAR4          (PKUNITY_PCIBRI_BASE + 0x01CC)
  81 #define PCIBRI_AHBCTL5          (PKUNITY_PCIBRI_BASE + 0x01D0)
  82 #define PCIBRI_AHBBAR5          (PKUNITY_PCIBRI_BASE + 0x01D4)
  83 #define PCIBRI_AHBAMR5          (PKUNITY_PCIBRI_BASE + 0x01D8)
  84 #define PCIBRI_AHBTAR5          (PKUNITY_PCIBRI_BASE + 0x01DC)
  85 
  86 #define PCIBRI_CTLx_AT          FIELD(1, 1, 2)
  87 #define PCIBRI_CTLx_PREF        FIELD(1, 1, 1)
  88 #define PCIBRI_CTLx_MRL         FIELD(1, 1, 0)
  89 
  90 #define PCIBRI_BARx_ADDR        FIELD(0xFFFFFFFC, 30, 2)
  91 #define PCIBRI_BARx_IO          FIELD(1, 1, 0)
  92 #define PCIBRI_BARx_MEM         FIELD(0, 1, 0)
  93 
  94 #define PCIBRI_CMD_IO           FIELD(1, 1, 0)
  95 #define PCIBRI_CMD_MEM          FIELD(1, 1, 1)