This source file includes following definitions.
- snd_gf1_dma_ack
- snd_gf1_dma_program
- snd_gf1_dma_next_block
- snd_gf1_dma_interrupt
- snd_gf1_dma_init
- snd_gf1_dma_done
- snd_gf1_dma_transfer_block
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7 #include <asm/dma.h>
8 #include <linux/slab.h>
9 #include <sound/core.h>
10 #include <sound/gus.h>
11
12 static void snd_gf1_dma_ack(struct snd_gus_card * gus)
13 {
14 unsigned long flags;
15
16 spin_lock_irqsave(&gus->reg_lock, flags);
17 snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, 0x00);
18 snd_gf1_look8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL);
19 spin_unlock_irqrestore(&gus->reg_lock, flags);
20 }
21
22 static void snd_gf1_dma_program(struct snd_gus_card * gus,
23 unsigned int addr,
24 unsigned long buf_addr,
25 unsigned int count,
26 unsigned int cmd)
27 {
28 unsigned long flags;
29 unsigned int address;
30 unsigned char dma_cmd;
31 unsigned int address_high;
32
33 snd_printdd("dma_transfer: addr=0x%x, buf=0x%lx, count=0x%x\n",
34 addr, buf_addr, count);
35
36 if (gus->gf1.dma1 > 3) {
37 if (gus->gf1.enh_mode) {
38 address = addr >> 1;
39 } else {
40 if (addr & 0x1f) {
41 snd_printd("snd_gf1_dma_transfer: unaligned address (0x%x)?\n", addr);
42 return;
43 }
44 address = (addr & 0x000c0000) | ((addr & 0x0003ffff) >> 1);
45 }
46 } else {
47 address = addr;
48 }
49
50 dma_cmd = SNDRV_GF1_DMA_ENABLE | (unsigned short) cmd;
51 #if 0
52 dma_cmd |= 0x08;
53 #endif
54 if (dma_cmd & SNDRV_GF1_DMA_16BIT) {
55 count++;
56 count &= ~1;
57 }
58 if (gus->gf1.dma1 > 3) {
59 dma_cmd |= SNDRV_GF1_DMA_WIDTH16;
60 count++;
61 count &= ~1;
62 }
63 snd_gf1_dma_ack(gus);
64 snd_dma_program(gus->gf1.dma1, buf_addr, count, dma_cmd & SNDRV_GF1_DMA_READ ? DMA_MODE_READ : DMA_MODE_WRITE);
65 #if 0
66 snd_printk(KERN_DEBUG "address = 0x%x, count = 0x%x, dma_cmd = 0x%x\n",
67 address << 1, count, dma_cmd);
68 #endif
69 spin_lock_irqsave(&gus->reg_lock, flags);
70 if (gus->gf1.enh_mode) {
71 address_high = ((address >> 16) & 0x000000f0) | (address & 0x0000000f);
72 snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
73 snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_HIGH, (unsigned char) address_high);
74 } else
75 snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
76 snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, dma_cmd);
77 spin_unlock_irqrestore(&gus->reg_lock, flags);
78 }
79
80 static struct snd_gf1_dma_block *snd_gf1_dma_next_block(struct snd_gus_card * gus)
81 {
82 struct snd_gf1_dma_block *block;
83
84
85 if (gus->gf1.dma_data_pcm) {
86 block = gus->gf1.dma_data_pcm;
87 if (gus->gf1.dma_data_pcm_last == block) {
88 gus->gf1.dma_data_pcm =
89 gus->gf1.dma_data_pcm_last = NULL;
90 } else {
91 gus->gf1.dma_data_pcm = block->next;
92 }
93 } else if (gus->gf1.dma_data_synth) {
94 block = gus->gf1.dma_data_synth;
95 if (gus->gf1.dma_data_synth_last == block) {
96 gus->gf1.dma_data_synth =
97 gus->gf1.dma_data_synth_last = NULL;
98 } else {
99 gus->gf1.dma_data_synth = block->next;
100 }
101 } else {
102 block = NULL;
103 }
104 if (block) {
105 gus->gf1.dma_ack = block->ack;
106 gus->gf1.dma_private_data = block->private_data;
107 }
108 return block;
109 }
110
111
112 static void snd_gf1_dma_interrupt(struct snd_gus_card * gus)
113 {
114 struct snd_gf1_dma_block *block;
115
116 snd_gf1_dma_ack(gus);
117 if (gus->gf1.dma_ack)
118 gus->gf1.dma_ack(gus, gus->gf1.dma_private_data);
119 spin_lock(&gus->dma_lock);
120 if (gus->gf1.dma_data_pcm == NULL &&
121 gus->gf1.dma_data_synth == NULL) {
122 gus->gf1.dma_ack = NULL;
123 gus->gf1.dma_flags &= ~SNDRV_GF1_DMA_TRIGGER;
124 spin_unlock(&gus->dma_lock);
125 return;
126 }
127 block = snd_gf1_dma_next_block(gus);
128 spin_unlock(&gus->dma_lock);
129 snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd);
130 kfree(block);
131 #if 0
132 snd_printd(KERN_DEBUG "program dma (IRQ) - "
133 "addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n",
134 block->addr, block->buf_addr, block->count, block->cmd);
135 #endif
136 }
137
138 int snd_gf1_dma_init(struct snd_gus_card * gus)
139 {
140 mutex_lock(&gus->dma_mutex);
141 gus->gf1.dma_shared++;
142 if (gus->gf1.dma_shared > 1) {
143 mutex_unlock(&gus->dma_mutex);
144 return 0;
145 }
146 gus->gf1.interrupt_handler_dma_write = snd_gf1_dma_interrupt;
147 gus->gf1.dma_data_pcm =
148 gus->gf1.dma_data_pcm_last =
149 gus->gf1.dma_data_synth =
150 gus->gf1.dma_data_synth_last = NULL;
151 mutex_unlock(&gus->dma_mutex);
152 return 0;
153 }
154
155 int snd_gf1_dma_done(struct snd_gus_card * gus)
156 {
157 struct snd_gf1_dma_block *block;
158
159 mutex_lock(&gus->dma_mutex);
160 gus->gf1.dma_shared--;
161 if (!gus->gf1.dma_shared) {
162 snd_dma_disable(gus->gf1.dma1);
163 snd_gf1_set_default_handlers(gus, SNDRV_GF1_HANDLER_DMA_WRITE);
164 snd_gf1_dma_ack(gus);
165 while ((block = gus->gf1.dma_data_pcm)) {
166 gus->gf1.dma_data_pcm = block->next;
167 kfree(block);
168 }
169 while ((block = gus->gf1.dma_data_synth)) {
170 gus->gf1.dma_data_synth = block->next;
171 kfree(block);
172 }
173 gus->gf1.dma_data_pcm_last =
174 gus->gf1.dma_data_synth_last = NULL;
175 }
176 mutex_unlock(&gus->dma_mutex);
177 return 0;
178 }
179
180 int snd_gf1_dma_transfer_block(struct snd_gus_card * gus,
181 struct snd_gf1_dma_block * __block,
182 int atomic,
183 int synth)
184 {
185 unsigned long flags;
186 struct snd_gf1_dma_block *block;
187
188 block = kmalloc(sizeof(*block), atomic ? GFP_ATOMIC : GFP_KERNEL);
189 if (!block)
190 return -ENOMEM;
191
192 *block = *__block;
193 block->next = NULL;
194
195 snd_printdd("addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n",
196 block->addr, (long) block->buffer, block->count,
197 block->cmd);
198
199 snd_printdd("gus->gf1.dma_data_pcm_last = 0x%lx\n",
200 (long)gus->gf1.dma_data_pcm_last);
201 snd_printdd("gus->gf1.dma_data_pcm = 0x%lx\n",
202 (long)gus->gf1.dma_data_pcm);
203
204 spin_lock_irqsave(&gus->dma_lock, flags);
205 if (synth) {
206 if (gus->gf1.dma_data_synth_last) {
207 gus->gf1.dma_data_synth_last->next = block;
208 gus->gf1.dma_data_synth_last = block;
209 } else {
210 gus->gf1.dma_data_synth =
211 gus->gf1.dma_data_synth_last = block;
212 }
213 } else {
214 if (gus->gf1.dma_data_pcm_last) {
215 gus->gf1.dma_data_pcm_last->next = block;
216 gus->gf1.dma_data_pcm_last = block;
217 } else {
218 gus->gf1.dma_data_pcm =
219 gus->gf1.dma_data_pcm_last = block;
220 }
221 }
222 if (!(gus->gf1.dma_flags & SNDRV_GF1_DMA_TRIGGER)) {
223 gus->gf1.dma_flags |= SNDRV_GF1_DMA_TRIGGER;
224 block = snd_gf1_dma_next_block(gus);
225 spin_unlock_irqrestore(&gus->dma_lock, flags);
226 if (block == NULL)
227 return 0;
228 snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd);
229 kfree(block);
230 return 0;
231 }
232 spin_unlock_irqrestore(&gus->dma_lock, flags);
233 return 0;
234 }