This source file includes following definitions.
- snd_vx_check_reg_bit
- vx_send_irq_dsp
- vx_reset_chk
- vx_transfer_end
- vx_read_status
- vx_send_msg_nolock
- vx_send_msg
- vx_send_rih_nolock
- vx_send_rih
- snd_vx_load_boot_image
- vx_test_irq_src
- snd_vx_threaded_irq_handler
- snd_vx_irq_handler
- vx_reset_board
- vx_proc_read
- vx_proc_init
- snd_vx_dsp_boot
- snd_vx_dsp_load
- snd_vx_suspend
- snd_vx_resume
- snd_vx_create
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8
9
10 #include <linux/delay.h>
11 #include <linux/slab.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/firmware.h>
16 #include <linux/module.h>
17 #include <linux/io.h>
18 #include <sound/core.h>
19 #include <sound/pcm.h>
20 #include <sound/asoundef.h>
21 #include <sound/info.h>
22 #include <sound/vx_core.h>
23 #include "vx_cmd.h"
24
25 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
26 MODULE_DESCRIPTION("Common routines for Digigram VX drivers");
27 MODULE_LICENSE("GPL");
28
29
30
31
32
33
34
35
36
37
38
39 int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time)
40 {
41 unsigned long end_time = jiffies + (time * HZ + 999) / 1000;
42 static char *reg_names[VX_REG_MAX] = {
43 "ICR", "CVR", "ISR", "IVR", "RXH", "RXM", "RXL",
44 "DMA", "CDSP", "RFREQ", "RUER/V2", "DATA", "MEMIRQ",
45 "ACQ", "BIT0", "BIT1", "MIC0", "MIC1", "MIC2",
46 "MIC3", "INTCSR", "CNTRL", "GPIOC",
47 "LOFREQ", "HIFREQ", "CSUER", "RUER"
48 };
49
50 do {
51 if ((snd_vx_inb(chip, reg) & mask) == bit)
52 return 0;
53
54 } while (time_after_eq(end_time, jiffies));
55 snd_printd(KERN_DEBUG "vx_check_reg_bit: timeout, reg=%s, mask=0x%x, val=0x%x\n", reg_names[reg], mask, snd_vx_inb(chip, reg));
56 return -EIO;
57 }
58
59 EXPORT_SYMBOL(snd_vx_check_reg_bit);
60
61
62
63
64
65
66
67
68
69 static int vx_send_irq_dsp(struct vx_core *chip, int num)
70 {
71 int nirq;
72
73
74 if (snd_vx_check_reg_bit(chip, VX_CVR, CVR_HC, 0, 200) < 0)
75 return -EIO;
76
77 nirq = num;
78 if (vx_has_new_dsp(chip))
79 nirq += VXP_IRQ_OFFSET;
80 vx_outb(chip, CVR, (nirq >> 1) | CVR_HC);
81 return 0;
82 }
83
84
85
86
87
88
89
90 static int vx_reset_chk(struct vx_core *chip)
91 {
92
93 if (vx_send_irq_dsp(chip, IRQ_RESET_CHK) < 0)
94 return -EIO;
95
96 if (vx_check_isr(chip, ISR_CHK, 0, 200) < 0)
97 return -EIO;
98 return 0;
99 }
100
101
102
103
104
105
106
107
108
109 static int vx_transfer_end(struct vx_core *chip, int cmd)
110 {
111 int err;
112
113 if ((err = vx_reset_chk(chip)) < 0)
114 return err;
115
116
117 if ((err = vx_send_irq_dsp(chip, cmd)) < 0)
118 return err;
119
120
121 if ((err = vx_wait_isr_bit(chip, ISR_CHK)) < 0)
122 return err;
123
124
125 if ((err = vx_inb(chip, ISR)) & ISR_ERR) {
126 if ((err = vx_wait_for_rx_full(chip)) < 0) {
127 snd_printd(KERN_DEBUG "transfer_end: error in rx_full\n");
128 return err;
129 }
130 err = vx_inb(chip, RXH) << 16;
131 err |= vx_inb(chip, RXM) << 8;
132 err |= vx_inb(chip, RXL);
133 snd_printd(KERN_DEBUG "transfer_end: error = 0x%x\n", err);
134 return -(VX_ERR_MASK | err);
135 }
136 return 0;
137 }
138
139
140
141
142
143
144
145
146
147 static int vx_read_status(struct vx_core *chip, struct vx_rmh *rmh)
148 {
149 int i, err, val, size;
150
151
152 if (rmh->DspStat == RMH_SSIZE_FIXED && rmh->LgStat == 0)
153 return 0;
154
155
156
157
158 err = vx_wait_for_rx_full(chip);
159 if (err < 0)
160 return err;
161
162
163 val = vx_inb(chip, RXH) << 16;
164 val |= vx_inb(chip, RXM) << 8;
165 val |= vx_inb(chip, RXL);
166
167
168 switch (rmh->DspStat) {
169 case RMH_SSIZE_ARG:
170 size = val & 0xff;
171 rmh->Stat[0] = val & 0xffff00;
172 rmh->LgStat = size + 1;
173 break;
174 case RMH_SSIZE_MASK:
175
176 rmh->Stat[0] = val;
177 size = 0;
178 while (val) {
179 if (val & 0x01)
180 size++;
181 val >>= 1;
182 }
183 rmh->LgStat = size + 1;
184 break;
185 default:
186
187 size = rmh->LgStat;
188 rmh->Stat[0] = val;
189 size--;
190 break;
191 }
192
193 if (size < 1)
194 return 0;
195 if (snd_BUG_ON(size >= SIZE_MAX_STATUS))
196 return -EINVAL;
197
198 for (i = 1; i <= size; i++) {
199
200 err = vx_send_irq_dsp(chip, IRQ_MESS_WRITE_NEXT);
201 if (err < 0)
202 return err;
203
204 err = vx_wait_for_rx_full(chip);
205 if (err < 0)
206 return err;
207 rmh->Stat[i] = vx_inb(chip, RXH) << 16;
208 rmh->Stat[i] |= vx_inb(chip, RXM) << 8;
209 rmh->Stat[i] |= vx_inb(chip, RXL);
210 }
211
212 return vx_transfer_end(chip, IRQ_MESS_WRITE_END);
213 }
214
215
216 #define MASK_MORE_THAN_1_WORD_COMMAND 0x00008000
217 #define MASK_1_WORD_COMMAND 0x00ff7fff
218
219
220
221
222
223
224
225
226
227
228 int vx_send_msg_nolock(struct vx_core *chip, struct vx_rmh *rmh)
229 {
230 int i, err;
231
232 if (chip->chip_status & VX_STAT_IS_STALE)
233 return -EBUSY;
234
235 if ((err = vx_reset_chk(chip)) < 0) {
236 snd_printd(KERN_DEBUG "vx_send_msg: vx_reset_chk error\n");
237 return err;
238 }
239
240 #if 0
241 printk(KERN_DEBUG "rmh: cmd = 0x%06x, length = %d, stype = %d\n",
242 rmh->Cmd[0], rmh->LgCmd, rmh->DspStat);
243 if (rmh->LgCmd > 1) {
244 printk(KERN_DEBUG " ");
245 for (i = 1; i < rmh->LgCmd; i++)
246 printk(KERN_CONT "0x%06x ", rmh->Cmd[i]);
247 printk(KERN_CONT "\n");
248 }
249 #endif
250
251 if (rmh->LgCmd > 1)
252 rmh->Cmd[0] |= MASK_MORE_THAN_1_WORD_COMMAND;
253 else
254 rmh->Cmd[0] &= MASK_1_WORD_COMMAND;
255
256
257 if ((err = vx_wait_isr_bit(chip, ISR_TX_EMPTY)) < 0) {
258 snd_printd(KERN_DEBUG "vx_send_msg: wait tx empty error\n");
259 return err;
260 }
261
262
263 vx_outb(chip, TXH, (rmh->Cmd[0] >> 16) & 0xff);
264 vx_outb(chip, TXM, (rmh->Cmd[0] >> 8) & 0xff);
265 vx_outb(chip, TXL, rmh->Cmd[0] & 0xff);
266
267
268 if ((err = vx_send_irq_dsp(chip, IRQ_MESSAGE)) < 0) {
269 snd_printd(KERN_DEBUG "vx_send_msg: send IRQ_MESSAGE error\n");
270 return err;
271 }
272
273
274 if ((err = vx_wait_isr_bit(chip, ISR_CHK)) < 0)
275 return err;
276
277
278 if (vx_inb(chip, ISR) & ISR_ERR) {
279 if ((err = vx_wait_for_rx_full(chip)) < 0) {
280 snd_printd(KERN_DEBUG "vx_send_msg: rx_full read error\n");
281 return err;
282 }
283 err = vx_inb(chip, RXH) << 16;
284 err |= vx_inb(chip, RXM) << 8;
285 err |= vx_inb(chip, RXL);
286 snd_printd(KERN_DEBUG "msg got error = 0x%x at cmd[0]\n", err);
287 err = -(VX_ERR_MASK | err);
288 return err;
289 }
290
291
292 if (rmh->LgCmd > 1) {
293 for (i = 1; i < rmh->LgCmd; i++) {
294
295 if ((err = vx_wait_isr_bit(chip, ISR_TX_READY)) < 0) {
296 snd_printd(KERN_DEBUG "vx_send_msg: tx_ready error\n");
297 return err;
298 }
299
300
301 vx_outb(chip, TXH, (rmh->Cmd[i] >> 16) & 0xff);
302 vx_outb(chip, TXM, (rmh->Cmd[i] >> 8) & 0xff);
303 vx_outb(chip, TXL, rmh->Cmd[i] & 0xff);
304
305
306 if ((err = vx_send_irq_dsp(chip, IRQ_MESS_READ_NEXT)) < 0) {
307 snd_printd(KERN_DEBUG "vx_send_msg: IRQ_READ_NEXT error\n");
308 return err;
309 }
310 }
311
312 if ((err = vx_wait_isr_bit(chip, ISR_TX_READY)) < 0) {
313 snd_printd(KERN_DEBUG "vx_send_msg: TX_READY error\n");
314 return err;
315 }
316
317 err = vx_transfer_end(chip, IRQ_MESS_READ_END);
318 if (err < 0)
319 return err;
320 }
321
322 return vx_read_status(chip, rmh);
323 }
324
325
326
327
328
329
330
331
332
333 int vx_send_msg(struct vx_core *chip, struct vx_rmh *rmh)
334 {
335 int err;
336
337 mutex_lock(&chip->lock);
338 err = vx_send_msg_nolock(chip, rmh);
339 mutex_unlock(&chip->lock);
340 return err;
341 }
342
343
344
345
346
347
348
349
350
351
352
353
354
355 int vx_send_rih_nolock(struct vx_core *chip, int cmd)
356 {
357 int err;
358
359 if (chip->chip_status & VX_STAT_IS_STALE)
360 return -EBUSY;
361
362 #if 0
363 printk(KERN_DEBUG "send_rih: cmd = 0x%x\n", cmd);
364 #endif
365 if ((err = vx_reset_chk(chip)) < 0)
366 return err;
367
368 if ((err = vx_send_irq_dsp(chip, cmd)) < 0)
369 return err;
370
371 if ((err = vx_wait_isr_bit(chip, ISR_CHK)) < 0)
372 return err;
373
374 if (vx_inb(chip, ISR) & ISR_ERR) {
375 if ((err = vx_wait_for_rx_full(chip)) < 0)
376 return err;
377 err = vx_inb(chip, RXH) << 16;
378 err |= vx_inb(chip, RXM) << 8;
379 err |= vx_inb(chip, RXL);
380 return -(VX_ERR_MASK | err);
381 }
382 return 0;
383 }
384
385
386
387
388
389
390
391
392 int vx_send_rih(struct vx_core *chip, int cmd)
393 {
394 int err;
395
396 mutex_lock(&chip->lock);
397 err = vx_send_rih_nolock(chip, cmd);
398 mutex_unlock(&chip->lock);
399 return err;
400 }
401
402 #define END_OF_RESET_WAIT_TIME 500
403
404
405
406
407
408
409 int snd_vx_load_boot_image(struct vx_core *chip, const struct firmware *boot)
410 {
411 unsigned int i;
412 int no_fillup = vx_has_new_dsp(chip);
413
414
415 if (boot->size <= 0)
416 return -EINVAL;
417 if (boot->size % 3)
418 return -EINVAL;
419 #if 0
420 {
421
422 unsigned int c = ((u32)boot->data[0] << 16) | ((u32)boot->data[1] << 8) | boot->data[2];
423 if (boot->size != (c + 2) * 3)
424 return -EINVAL;
425 }
426 #endif
427
428
429 vx_reset_dsp(chip);
430
431 udelay(END_OF_RESET_WAIT_TIME);
432
433
434 for (i = 0; i < 0x600; i += 3) {
435 if (i >= boot->size) {
436 if (no_fillup)
437 break;
438 if (vx_wait_isr_bit(chip, ISR_TX_EMPTY) < 0) {
439 snd_printk(KERN_ERR "dsp boot failed at %d\n", i);
440 return -EIO;
441 }
442 vx_outb(chip, TXH, 0);
443 vx_outb(chip, TXM, 0);
444 vx_outb(chip, TXL, 0);
445 } else {
446 const unsigned char *image = boot->data + i;
447 if (vx_wait_isr_bit(chip, ISR_TX_EMPTY) < 0) {
448 snd_printk(KERN_ERR "dsp boot failed at %d\n", i);
449 return -EIO;
450 }
451 vx_outb(chip, TXH, image[0]);
452 vx_outb(chip, TXM, image[1]);
453 vx_outb(chip, TXL, image[2]);
454 }
455 }
456 return 0;
457 }
458
459 EXPORT_SYMBOL(snd_vx_load_boot_image);
460
461
462
463
464
465
466 static int vx_test_irq_src(struct vx_core *chip, unsigned int *ret)
467 {
468 int err;
469
470 vx_init_rmh(&chip->irq_rmh, CMD_TEST_IT);
471 mutex_lock(&chip->lock);
472 err = vx_send_msg_nolock(chip, &chip->irq_rmh);
473 if (err < 0)
474 *ret = 0;
475 else
476 *ret = chip->irq_rmh.Stat[0];
477 mutex_unlock(&chip->lock);
478 return err;
479 }
480
481
482
483
484
485 irqreturn_t snd_vx_threaded_irq_handler(int irq, void *dev)
486 {
487 struct vx_core *chip = dev;
488 unsigned int events;
489
490 if (chip->chip_status & VX_STAT_IS_STALE)
491 return IRQ_HANDLED;
492
493 if (vx_test_irq_src(chip, &events) < 0)
494 return IRQ_HANDLED;
495
496 #if 0
497 if (events & 0x000800)
498 printk(KERN_ERR "DSP Stream underrun ! IRQ events = 0x%x\n", events);
499 #endif
500
501
502
503
504
505
506 if (events & FATAL_DSP_ERROR) {
507 snd_printk(KERN_ERR "vx_core: fatal DSP error!!\n");
508 return IRQ_HANDLED;
509 }
510
511
512
513
514 if (events & TIME_CODE_EVENT_PENDING)
515 ;
516
517
518 if (events & FREQUENCY_CHANGE_EVENT_PENDING)
519 vx_change_frequency(chip);
520
521
522 vx_pcm_update_intr(chip, events);
523 return IRQ_HANDLED;
524 }
525 EXPORT_SYMBOL(snd_vx_threaded_irq_handler);
526
527
528
529
530
531
532 irqreturn_t snd_vx_irq_handler(int irq, void *dev)
533 {
534 struct vx_core *chip = dev;
535
536 if (! (chip->chip_status & VX_STAT_CHIP_INIT) ||
537 (chip->chip_status & VX_STAT_IS_STALE))
538 return IRQ_NONE;
539 if (! vx_test_and_ack(chip))
540 return IRQ_WAKE_THREAD;
541 return IRQ_NONE;
542 }
543
544 EXPORT_SYMBOL(snd_vx_irq_handler);
545
546
547
548 static void vx_reset_board(struct vx_core *chip, int cold_reset)
549 {
550 if (snd_BUG_ON(!chip->ops->reset_board))
551 return;
552
553
554 chip->audio_source = VX_AUDIO_SRC_LINE;
555 if (cold_reset) {
556 chip->audio_source_target = chip->audio_source;
557 chip->clock_source = INTERNAL_QUARTZ;
558 chip->clock_mode = VX_CLOCK_MODE_AUTO;
559 chip->freq = 48000;
560 chip->uer_detected = VX_UER_MODE_NOT_PRESENT;
561 chip->uer_bits = SNDRV_PCM_DEFAULT_CON_SPDIF;
562 }
563
564 chip->ops->reset_board(chip, cold_reset);
565
566 vx_reset_codec(chip, cold_reset);
567
568 vx_set_internal_clock(chip, chip->freq);
569
570
571 vx_reset_dsp(chip);
572
573 if (vx_is_pcmcia(chip)) {
574
575 vx_test_and_ack(chip);
576 vx_validate_irq(chip, 1);
577 }
578
579
580 vx_set_iec958_status(chip, chip->uer_bits);
581 }
582
583
584
585
586
587
588 static void vx_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
589 {
590 struct vx_core *chip = entry->private_data;
591 static char *audio_src_vxp[] = { "Line", "Mic", "Digital" };
592 static char *audio_src_vx2[] = { "Analog", "Analog", "Digital" };
593 static char *clock_mode[] = { "Auto", "Internal", "External" };
594 static char *clock_src[] = { "Internal", "External" };
595 static char *uer_type[] = { "Consumer", "Professional", "Not Present" };
596
597 snd_iprintf(buffer, "%s\n", chip->card->longname);
598 snd_iprintf(buffer, "Xilinx Firmware: %s\n",
599 chip->chip_status & VX_STAT_XILINX_LOADED ? "Loaded" : "No");
600 snd_iprintf(buffer, "Device Initialized: %s\n",
601 chip->chip_status & VX_STAT_DEVICE_INIT ? "Yes" : "No");
602 snd_iprintf(buffer, "DSP audio info:");
603 if (chip->audio_info & VX_AUDIO_INFO_REAL_TIME)
604 snd_iprintf(buffer, " realtime");
605 if (chip->audio_info & VX_AUDIO_INFO_OFFLINE)
606 snd_iprintf(buffer, " offline");
607 if (chip->audio_info & VX_AUDIO_INFO_MPEG1)
608 snd_iprintf(buffer, " mpeg1");
609 if (chip->audio_info & VX_AUDIO_INFO_MPEG2)
610 snd_iprintf(buffer, " mpeg2");
611 if (chip->audio_info & VX_AUDIO_INFO_LINEAR_8)
612 snd_iprintf(buffer, " linear8");
613 if (chip->audio_info & VX_AUDIO_INFO_LINEAR_16)
614 snd_iprintf(buffer, " linear16");
615 if (chip->audio_info & VX_AUDIO_INFO_LINEAR_24)
616 snd_iprintf(buffer, " linear24");
617 snd_iprintf(buffer, "\n");
618 snd_iprintf(buffer, "Input Source: %s\n", vx_is_pcmcia(chip) ?
619 audio_src_vxp[chip->audio_source] :
620 audio_src_vx2[chip->audio_source]);
621 snd_iprintf(buffer, "Clock Mode: %s\n", clock_mode[chip->clock_mode]);
622 snd_iprintf(buffer, "Clock Source: %s\n", clock_src[chip->clock_source]);
623 snd_iprintf(buffer, "Frequency: %d\n", chip->freq);
624 snd_iprintf(buffer, "Detected Frequency: %d\n", chip->freq_detected);
625 snd_iprintf(buffer, "Detected UER type: %s\n", uer_type[chip->uer_detected]);
626 snd_iprintf(buffer, "Min/Max/Cur IBL: %d/%d/%d (granularity=%d)\n",
627 chip->ibl.min_size, chip->ibl.max_size, chip->ibl.size,
628 chip->ibl.granularity);
629 }
630
631 static void vx_proc_init(struct vx_core *chip)
632 {
633 snd_card_ro_proc_new(chip->card, "vx-status", chip, vx_proc_read);
634 }
635
636
637
638
639
640
641
642 int snd_vx_dsp_boot(struct vx_core *chip, const struct firmware *boot)
643 {
644 int err;
645 int cold_reset = !(chip->chip_status & VX_STAT_DEVICE_INIT);
646
647 vx_reset_board(chip, cold_reset);
648 vx_validate_irq(chip, 0);
649
650 if ((err = snd_vx_load_boot_image(chip, boot)) < 0)
651 return err;
652 msleep(10);
653
654 return 0;
655 }
656
657 EXPORT_SYMBOL(snd_vx_dsp_boot);
658
659
660
661
662
663
664 int snd_vx_dsp_load(struct vx_core *chip, const struct firmware *dsp)
665 {
666 unsigned int i;
667 int err;
668 unsigned int csum = 0;
669 const unsigned char *image, *cptr;
670
671 if (dsp->size % 3)
672 return -EINVAL;
673
674 vx_toggle_dac_mute(chip, 1);
675
676
677 for (i = 0; i < dsp->size; i += 3) {
678 image = dsp->data + i;
679
680 if ((err = vx_wait_isr_bit(chip, ISR_TX_EMPTY)) < 0) {
681 printk(KERN_ERR
682 "dsp loading error at position %d\n", i);
683 return err;
684 }
685 cptr = image;
686 csum ^= *cptr;
687 csum = (csum >> 24) | (csum << 8);
688 vx_outb(chip, TXH, *cptr++);
689 csum ^= *cptr;
690 csum = (csum >> 24) | (csum << 8);
691 vx_outb(chip, TXM, *cptr++);
692 csum ^= *cptr;
693 csum = (csum >> 24) | (csum << 8);
694 vx_outb(chip, TXL, *cptr++);
695 }
696 snd_printdd(KERN_DEBUG "checksum = 0x%08x\n", csum);
697
698 msleep(200);
699
700 if ((err = vx_wait_isr_bit(chip, ISR_CHK)) < 0)
701 return err;
702
703 vx_toggle_dac_mute(chip, 0);
704
705 vx_test_and_ack(chip);
706 vx_validate_irq(chip, 1);
707
708 return 0;
709 }
710
711 EXPORT_SYMBOL(snd_vx_dsp_load);
712
713 #ifdef CONFIG_PM
714
715
716
717 int snd_vx_suspend(struct vx_core *chip)
718 {
719 snd_power_change_state(chip->card, SNDRV_CTL_POWER_D3hot);
720 chip->chip_status |= VX_STAT_IN_SUSPEND;
721
722 return 0;
723 }
724
725 EXPORT_SYMBOL(snd_vx_suspend);
726
727
728
729
730 int snd_vx_resume(struct vx_core *chip)
731 {
732 int i, err;
733
734 chip->chip_status &= ~VX_STAT_CHIP_INIT;
735
736 for (i = 0; i < 4; i++) {
737 if (! chip->firmware[i])
738 continue;
739 err = chip->ops->load_dsp(chip, i, chip->firmware[i]);
740 if (err < 0) {
741 snd_printk(KERN_ERR "vx: firmware resume error at DSP %d\n", i);
742 return -EIO;
743 }
744 }
745
746 chip->chip_status |= VX_STAT_CHIP_INIT;
747 chip->chip_status &= ~VX_STAT_IN_SUSPEND;
748
749 snd_power_change_state(chip->card, SNDRV_CTL_POWER_D0);
750 return 0;
751 }
752
753 EXPORT_SYMBOL(snd_vx_resume);
754 #endif
755
756
757
758
759
760
761
762
763
764
765
766
767
768 struct vx_core *snd_vx_create(struct snd_card *card, struct snd_vx_hardware *hw,
769 struct snd_vx_ops *ops,
770 int extra_size)
771 {
772 struct vx_core *chip;
773
774 if (snd_BUG_ON(!card || !hw || !ops))
775 return NULL;
776
777 chip = kzalloc(sizeof(*chip) + extra_size, GFP_KERNEL);
778 if (! chip)
779 return NULL;
780 mutex_init(&chip->lock);
781 chip->irq = -1;
782 chip->hw = hw;
783 chip->type = hw->type;
784 chip->ops = ops;
785 mutex_init(&chip->mixer_mutex);
786
787 chip->card = card;
788 card->private_data = chip;
789 strcpy(card->driver, hw->name);
790 sprintf(card->shortname, "Digigram %s", hw->name);
791
792 vx_proc_init(chip);
793
794 return chip;
795 }
796
797 EXPORT_SYMBOL(snd_vx_create);