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24 #ifndef ACP_2_2_D_H
25 #define ACP_2_2_D_H
26
27 #define mmACP_DMA_CNTL_0 0x5000
28 #define mmACP_DMA_CNTL_1 0x5001
29 #define mmACP_DMA_CNTL_2 0x5002
30 #define mmACP_DMA_CNTL_3 0x5003
31 #define mmACP_DMA_CNTL_4 0x5004
32 #define mmACP_DMA_CNTL_5 0x5005
33 #define mmACP_DMA_CNTL_6 0x5006
34 #define mmACP_DMA_CNTL_7 0x5007
35 #define mmACP_DMA_CNTL_8 0x5008
36 #define mmACP_DMA_CNTL_9 0x5009
37 #define mmACP_DMA_CNTL_10 0x500a
38 #define mmACP_DMA_CNTL_11 0x500b
39 #define mmACP_DMA_CNTL_12 0x500c
40 #define mmACP_DMA_CNTL_13 0x500d
41 #define mmACP_DMA_CNTL_14 0x500e
42 #define mmACP_DMA_CNTL_15 0x500f
43 #define mmACP_DMA_DSCR_STRT_IDX_0 0x5010
44 #define mmACP_DMA_DSCR_STRT_IDX_1 0x5011
45 #define mmACP_DMA_DSCR_STRT_IDX_2 0x5012
46 #define mmACP_DMA_DSCR_STRT_IDX_3 0x5013
47 #define mmACP_DMA_DSCR_STRT_IDX_4 0x5014
48 #define mmACP_DMA_DSCR_STRT_IDX_5 0x5015
49 #define mmACP_DMA_DSCR_STRT_IDX_6 0x5016
50 #define mmACP_DMA_DSCR_STRT_IDX_7 0x5017
51 #define mmACP_DMA_DSCR_STRT_IDX_8 0x5018
52 #define mmACP_DMA_DSCR_STRT_IDX_9 0x5019
53 #define mmACP_DMA_DSCR_STRT_IDX_10 0x501a
54 #define mmACP_DMA_DSCR_STRT_IDX_11 0x501b
55 #define mmACP_DMA_DSCR_STRT_IDX_12 0x501c
56 #define mmACP_DMA_DSCR_STRT_IDX_13 0x501d
57 #define mmACP_DMA_DSCR_STRT_IDX_14 0x501e
58 #define mmACP_DMA_DSCR_STRT_IDX_15 0x501f
59 #define mmACP_DMA_DSCR_CNT_0 0x5020
60 #define mmACP_DMA_DSCR_CNT_1 0x5021
61 #define mmACP_DMA_DSCR_CNT_2 0x5022
62 #define mmACP_DMA_DSCR_CNT_3 0x5023
63 #define mmACP_DMA_DSCR_CNT_4 0x5024
64 #define mmACP_DMA_DSCR_CNT_5 0x5025
65 #define mmACP_DMA_DSCR_CNT_6 0x5026
66 #define mmACP_DMA_DSCR_CNT_7 0x5027
67 #define mmACP_DMA_DSCR_CNT_8 0x5028
68 #define mmACP_DMA_DSCR_CNT_9 0x5029
69 #define mmACP_DMA_DSCR_CNT_10 0x502a
70 #define mmACP_DMA_DSCR_CNT_11 0x502b
71 #define mmACP_DMA_DSCR_CNT_12 0x502c
72 #define mmACP_DMA_DSCR_CNT_13 0x502d
73 #define mmACP_DMA_DSCR_CNT_14 0x502e
74 #define mmACP_DMA_DSCR_CNT_15 0x502f
75 #define mmACP_DMA_PRIO_0 0x5030
76 #define mmACP_DMA_PRIO_1 0x5031
77 #define mmACP_DMA_PRIO_2 0x5032
78 #define mmACP_DMA_PRIO_3 0x5033
79 #define mmACP_DMA_PRIO_4 0x5034
80 #define mmACP_DMA_PRIO_5 0x5035
81 #define mmACP_DMA_PRIO_6 0x5036
82 #define mmACP_DMA_PRIO_7 0x5037
83 #define mmACP_DMA_PRIO_8 0x5038
84 #define mmACP_DMA_PRIO_9 0x5039
85 #define mmACP_DMA_PRIO_10 0x503a
86 #define mmACP_DMA_PRIO_11 0x503b
87 #define mmACP_DMA_PRIO_12 0x503c
88 #define mmACP_DMA_PRIO_13 0x503d
89 #define mmACP_DMA_PRIO_14 0x503e
90 #define mmACP_DMA_PRIO_15 0x503f
91 #define mmACP_DMA_CUR_DSCR_0 0x5040
92 #define mmACP_DMA_CUR_DSCR_1 0x5041
93 #define mmACP_DMA_CUR_DSCR_2 0x5042
94 #define mmACP_DMA_CUR_DSCR_3 0x5043
95 #define mmACP_DMA_CUR_DSCR_4 0x5044
96 #define mmACP_DMA_CUR_DSCR_5 0x5045
97 #define mmACP_DMA_CUR_DSCR_6 0x5046
98 #define mmACP_DMA_CUR_DSCR_7 0x5047
99 #define mmACP_DMA_CUR_DSCR_8 0x5048
100 #define mmACP_DMA_CUR_DSCR_9 0x5049
101 #define mmACP_DMA_CUR_DSCR_10 0x504a
102 #define mmACP_DMA_CUR_DSCR_11 0x504b
103 #define mmACP_DMA_CUR_DSCR_12 0x504c
104 #define mmACP_DMA_CUR_DSCR_13 0x504d
105 #define mmACP_DMA_CUR_DSCR_14 0x504e
106 #define mmACP_DMA_CUR_DSCR_15 0x504f
107 #define mmACP_DMA_CUR_TRANS_CNT_0 0x5050
108 #define mmACP_DMA_CUR_TRANS_CNT_1 0x5051
109 #define mmACP_DMA_CUR_TRANS_CNT_2 0x5052
110 #define mmACP_DMA_CUR_TRANS_CNT_3 0x5053
111 #define mmACP_DMA_CUR_TRANS_CNT_4 0x5054
112 #define mmACP_DMA_CUR_TRANS_CNT_5 0x5055
113 #define mmACP_DMA_CUR_TRANS_CNT_6 0x5056
114 #define mmACP_DMA_CUR_TRANS_CNT_7 0x5057
115 #define mmACP_DMA_CUR_TRANS_CNT_8 0x5058
116 #define mmACP_DMA_CUR_TRANS_CNT_9 0x5059
117 #define mmACP_DMA_CUR_TRANS_CNT_10 0x505a
118 #define mmACP_DMA_CUR_TRANS_CNT_11 0x505b
119 #define mmACP_DMA_CUR_TRANS_CNT_12 0x505c
120 #define mmACP_DMA_CUR_TRANS_CNT_13 0x505d
121 #define mmACP_DMA_CUR_TRANS_CNT_14 0x505e
122 #define mmACP_DMA_CUR_TRANS_CNT_15 0x505f
123 #define mmACP_DMA_ERR_STS_0 0x5060
124 #define mmACP_DMA_ERR_STS_1 0x5061
125 #define mmACP_DMA_ERR_STS_2 0x5062
126 #define mmACP_DMA_ERR_STS_3 0x5063
127 #define mmACP_DMA_ERR_STS_4 0x5064
128 #define mmACP_DMA_ERR_STS_5 0x5065
129 #define mmACP_DMA_ERR_STS_6 0x5066
130 #define mmACP_DMA_ERR_STS_7 0x5067
131 #define mmACP_DMA_ERR_STS_8 0x5068
132 #define mmACP_DMA_ERR_STS_9 0x5069
133 #define mmACP_DMA_ERR_STS_10 0x506a
134 #define mmACP_DMA_ERR_STS_11 0x506b
135 #define mmACP_DMA_ERR_STS_12 0x506c
136 #define mmACP_DMA_ERR_STS_13 0x506d
137 #define mmACP_DMA_ERR_STS_14 0x506e
138 #define mmACP_DMA_ERR_STS_15 0x506f
139 #define mmACP_DMA_DESC_BASE_ADDR 0x5070
140 #define mmACP_DMA_DESC_MAX_NUM_DSCR 0x5071
141 #define mmACP_DMA_CH_STS 0x5072
142 #define mmACP_DMA_CH_GROUP 0x5073
143 #define mmACP_DSP0_CACHE_OFFSET0 0x5078
144 #define mmACP_DSP0_CACHE_SIZE0 0x5079
145 #define mmACP_DSP0_CACHE_OFFSET1 0x507a
146 #define mmACP_DSP0_CACHE_SIZE1 0x507b
147 #define mmACP_DSP0_CACHE_OFFSET2 0x507c
148 #define mmACP_DSP0_CACHE_SIZE2 0x507d
149 #define mmACP_DSP0_CACHE_OFFSET3 0x507e
150 #define mmACP_DSP0_CACHE_SIZE3 0x507f
151 #define mmACP_DSP0_CACHE_OFFSET4 0x5080
152 #define mmACP_DSP0_CACHE_SIZE4 0x5081
153 #define mmACP_DSP0_CACHE_OFFSET5 0x5082
154 #define mmACP_DSP0_CACHE_SIZE5 0x5083
155 #define mmACP_DSP0_CACHE_OFFSET6 0x5084
156 #define mmACP_DSP0_CACHE_SIZE6 0x5085
157 #define mmACP_DSP0_CACHE_OFFSET7 0x5086
158 #define mmACP_DSP0_CACHE_SIZE7 0x5087
159 #define mmACP_DSP0_CACHE_OFFSET8 0x5088
160 #define mmACP_DSP0_CACHE_SIZE8 0x5089
161 #define mmACP_DSP0_NONCACHE_OFFSET0 0x508a
162 #define mmACP_DSP0_NONCACHE_SIZE0 0x508b
163 #define mmACP_DSP0_NONCACHE_OFFSET1 0x508c
164 #define mmACP_DSP0_NONCACHE_SIZE1 0x508d
165 #define mmACP_DSP0_DEBUG_PC 0x508e
166 #define mmACP_DSP0_NMI_SEL 0x508f
167 #define mmACP_DSP0_CLKRST_CNTL 0x5090
168 #define mmACP_DSP0_RUNSTALL 0x5091
169 #define mmACP_DSP0_OCD_HALT_ON_RST 0x5092
170 #define mmACP_DSP0_WAIT_MODE 0x5093
171 #define mmACP_DSP0_VECT_SEL 0x5094
172 #define mmACP_DSP0_DEBUG_REG1 0x5095
173 #define mmACP_DSP0_DEBUG_REG2 0x5096
174 #define mmACP_DSP0_DEBUG_REG3 0x5097
175 #define mmACP_DSP1_CACHE_OFFSET0 0x509d
176 #define mmACP_DSP1_CACHE_SIZE0 0x509e
177 #define mmACP_DSP1_CACHE_OFFSET1 0x509f
178 #define mmACP_DSP1_CACHE_SIZE1 0x50a0
179 #define mmACP_DSP1_CACHE_OFFSET2 0x50a1
180 #define mmACP_DSP1_CACHE_SIZE2 0x50a2
181 #define mmACP_DSP1_CACHE_OFFSET3 0x50a3
182 #define mmACP_DSP1_CACHE_SIZE3 0x50a4
183 #define mmACP_DSP1_CACHE_OFFSET4 0x50a5
184 #define mmACP_DSP1_CACHE_SIZE4 0x50a6
185 #define mmACP_DSP1_CACHE_OFFSET5 0x50a7
186 #define mmACP_DSP1_CACHE_SIZE5 0x50a8
187 #define mmACP_DSP1_CACHE_OFFSET6 0x50a9
188 #define mmACP_DSP1_CACHE_SIZE6 0x50aa
189 #define mmACP_DSP1_CACHE_OFFSET7 0x50ab
190 #define mmACP_DSP1_CACHE_SIZE7 0x50ac
191 #define mmACP_DSP1_CACHE_OFFSET8 0x50ad
192 #define mmACP_DSP1_CACHE_SIZE8 0x50ae
193 #define mmACP_DSP1_NONCACHE_OFFSET0 0x50af
194 #define mmACP_DSP1_NONCACHE_SIZE0 0x50b0
195 #define mmACP_DSP1_NONCACHE_OFFSET1 0x50b1
196 #define mmACP_DSP1_NONCACHE_SIZE1 0x50b2
197 #define mmACP_DSP1_DEBUG_PC 0x50b3
198 #define mmACP_DSP1_NMI_SEL 0x50b4
199 #define mmACP_DSP1_CLKRST_CNTL 0x50b5
200 #define mmACP_DSP1_RUNSTALL 0x50b6
201 #define mmACP_DSP1_OCD_HALT_ON_RST 0x50b7
202 #define mmACP_DSP1_WAIT_MODE 0x50b8
203 #define mmACP_DSP1_VECT_SEL 0x50b9
204 #define mmACP_DSP1_DEBUG_REG1 0x50ba
205 #define mmACP_DSP1_DEBUG_REG2 0x50bb
206 #define mmACP_DSP1_DEBUG_REG3 0x50bc
207 #define mmACP_DSP2_CACHE_OFFSET0 0x50c2
208 #define mmACP_DSP2_CACHE_SIZE0 0x50c3
209 #define mmACP_DSP2_CACHE_OFFSET1 0x50c4
210 #define mmACP_DSP2_CACHE_SIZE1 0x50c5
211 #define mmACP_DSP2_CACHE_OFFSET2 0x50c6
212 #define mmACP_DSP2_CACHE_SIZE2 0x50c7
213 #define mmACP_DSP2_CACHE_OFFSET3 0x50c8
214 #define mmACP_DSP2_CACHE_SIZE3 0x50c9
215 #define mmACP_DSP2_CACHE_OFFSET4 0x50ca
216 #define mmACP_DSP2_CACHE_SIZE4 0x50cb
217 #define mmACP_DSP2_CACHE_OFFSET5 0x50cc
218 #define mmACP_DSP2_CACHE_SIZE5 0x50cd
219 #define mmACP_DSP2_CACHE_OFFSET6 0x50ce
220 #define mmACP_DSP2_CACHE_SIZE6 0x50cf
221 #define mmACP_DSP2_CACHE_OFFSET7 0x50d0
222 #define mmACP_DSP2_CACHE_SIZE7 0x50d1
223 #define mmACP_DSP2_CACHE_OFFSET8 0x50d2
224 #define mmACP_DSP2_CACHE_SIZE8 0x50d3
225 #define mmACP_DSP2_NONCACHE_OFFSET0 0x50d4
226 #define mmACP_DSP2_NONCACHE_SIZE0 0x50d5
227 #define mmACP_DSP2_NONCACHE_OFFSET1 0x50d6
228 #define mmACP_DSP2_NONCACHE_SIZE1 0x50d7
229 #define mmACP_DSP2_DEBUG_PC 0x50d8
230 #define mmACP_DSP2_NMI_SEL 0x50d9
231 #define mmACP_DSP2_CLKRST_CNTL 0x50da
232 #define mmACP_DSP2_RUNSTALL 0x50db
233 #define mmACP_DSP2_OCD_HALT_ON_RST 0x50dc
234 #define mmACP_DSP2_WAIT_MODE 0x50dd
235 #define mmACP_DSP2_VECT_SEL 0x50de
236 #define mmACP_DSP2_DEBUG_REG1 0x50df
237 #define mmACP_DSP2_DEBUG_REG2 0x50e0
238 #define mmACP_DSP2_DEBUG_REG3 0x50e1
239 #define mmACP_AXI2DAGB_ONION_CNTL 0x50e7
240 #define mmACP_AXI2DAGB_ONION_ERR_STATUS_WR 0x50e8
241 #define mmACP_AXI2DAGB_ONION_ERR_STATUS_RD 0x50e9
242 #define mmACP_DAGB_Onion_TransPerf_Counter_Control 0x50ea
243 #define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Current 0x50eb
244 #define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Peak 0x50ec
245 #define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Current 0x50ed
246 #define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Peak 0x50ee
247 #define mmACP_AXI2DAGB_GARLIC_CNTL 0x50f3
248 #define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_WR 0x50f4
249 #define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_RD 0x50f5
250 #define mmACP_DAGB_Garlic_TransPerf_Counter_Control 0x50f6
251 #define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Current 0x50f7
252 #define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak 0x50f8
253 #define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Current 0x50f9
254 #define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak 0x50fa
255 #define mmACP_DAGB_PAGE_SIZE_GRP_1 0x50ff
256 #define mmACP_DAGB_BASE_ADDR_GRP_1 0x5100
257 #define mmACP_DAGB_PAGE_SIZE_GRP_2 0x5101
258 #define mmACP_DAGB_BASE_ADDR_GRP_2 0x5102
259 #define mmACP_DAGB_PAGE_SIZE_GRP_3 0x5103
260 #define mmACP_DAGB_BASE_ADDR_GRP_3 0x5104
261 #define mmACP_DAGB_PAGE_SIZE_GRP_4 0x5105
262 #define mmACP_DAGB_BASE_ADDR_GRP_4 0x5106
263 #define mmACP_DAGB_PAGE_SIZE_GRP_5 0x5107
264 #define mmACP_DAGB_BASE_ADDR_GRP_5 0x5108
265 #define mmACP_DAGB_PAGE_SIZE_GRP_6 0x5109
266 #define mmACP_DAGB_BASE_ADDR_GRP_6 0x510a
267 #define mmACP_DAGB_PAGE_SIZE_GRP_7 0x510b
268 #define mmACP_DAGB_BASE_ADDR_GRP_7 0x510c
269 #define mmACP_DAGB_PAGE_SIZE_GRP_8 0x510d
270 #define mmACP_DAGB_BASE_ADDR_GRP_8 0x510e
271 #define mmACP_DAGB_ATU_CTRL 0x510f
272 #define mmACP_CONTROL 0x5131
273 #define mmACP_STATUS 0x5133
274 #define mmACP_SOFT_RESET 0x5134
275 #define mmACP_PwrMgmt_CNTL 0x5135
276 #define mmACP_CAC_INDICATOR_CONTROL 0x5136
277 #define mmACP_SMU_MAILBOX 0x5137
278 #define mmACP_FUTURE_REG_SCLK_0 0x5138
279 #define mmACP_FUTURE_REG_SCLK_1 0x5139
280 #define mmACP_FUTURE_REG_SCLK_2 0x513a
281 #define mmACP_FUTURE_REG_SCLK_3 0x513b
282 #define mmACP_FUTURE_REG_SCLK_4 0x513c
283 #define mmACP_DAGB_DEBUG_CNT_ENABLE 0x513d
284 #define mmACP_DAGBG_WR_ASK_CNT 0x513e
285 #define mmACP_DAGBG_WR_GO_CNT 0x513f
286 #define mmACP_DAGBG_WR_EXP_RESP_CNT 0x5140
287 #define mmACP_DAGBG_WR_ACTUAL_RESP_CNT 0x5141
288 #define mmACP_DAGBG_RD_ASK_CNT 0x5142
289 #define mmACP_DAGBG_RD_GO_CNT 0x5143
290 #define mmACP_DAGBG_RD_EXP_RESP_CNT 0x5144
291 #define mmACP_DAGBG_RD_ACTUAL_RESP_CNT 0x5145
292 #define mmACP_DAGBO_WR_ASK_CNT 0x5146
293 #define mmACP_DAGBO_WR_GO_CNT 0x5147
294 #define mmACP_DAGBO_WR_EXP_RESP_CNT 0x5148
295 #define mmACP_DAGBO_WR_ACTUAL_RESP_CNT 0x5149
296 #define mmACP_DAGBO_RD_ASK_CNT 0x514a
297 #define mmACP_DAGBO_RD_GO_CNT 0x514b
298 #define mmACP_DAGBO_RD_EXP_RESP_CNT 0x514c
299 #define mmACP_DAGBO_RD_ACTUAL_RESP_CNT 0x514d
300 #define mmACP_BRB_CONTROL 0x5156
301 #define mmACP_EXTERNAL_INTR_ENB 0x5157
302 #define mmACP_EXTERNAL_INTR_CNTL 0x5158
303 #define mmACP_ERROR_SOURCE_STS 0x5159
304 #define mmACP_DSP_SW_INTR_TRIG 0x515a
305 #define mmACP_DSP_SW_INTR_CNTL 0x515b
306 #define mmACP_DAGBG_TIMEOUT_CNTL 0x515c
307 #define mmACP_DAGBO_TIMEOUT_CNTL 0x515d
308 #define mmACP_EXTERNAL_INTR_STAT 0x515e
309 #define mmACP_DSP_SW_INTR_STAT 0x515f
310 #define mmACP_DSP0_INTR_CNTL 0x5160
311 #define mmACP_DSP0_INTR_STAT 0x5161
312 #define mmACP_DSP0_TIMEOUT_CNTL 0x5162
313 #define mmACP_DSP1_INTR_CNTL 0x5163
314 #define mmACP_DSP1_INTR_STAT 0x5164
315 #define mmACP_DSP1_TIMEOUT_CNTL 0x5165
316 #define mmACP_DSP2_INTR_CNTL 0x5166
317 #define mmACP_DSP2_INTR_STAT 0x5167
318 #define mmACP_DSP2_TIMEOUT_CNTL 0x5168
319 #define mmACP_DSP0_EXT_TIMER_CNTL 0x5169
320 #define mmACP_DSP1_EXT_TIMER_CNTL 0x516a
321 #define mmACP_DSP2_EXT_TIMER_CNTL 0x516b
322 #define mmACP_AXI2DAGB_SEM_0 0x516c
323 #define mmACP_AXI2DAGB_SEM_1 0x516d
324 #define mmACP_AXI2DAGB_SEM_2 0x516e
325 #define mmACP_AXI2DAGB_SEM_3 0x516f
326 #define mmACP_AXI2DAGB_SEM_4 0x5170
327 #define mmACP_AXI2DAGB_SEM_5 0x5171
328 #define mmACP_AXI2DAGB_SEM_6 0x5172
329 #define mmACP_AXI2DAGB_SEM_7 0x5173
330 #define mmACP_AXI2DAGB_SEM_8 0x5174
331 #define mmACP_AXI2DAGB_SEM_9 0x5175
332 #define mmACP_AXI2DAGB_SEM_10 0x5176
333 #define mmACP_AXI2DAGB_SEM_11 0x5177
334 #define mmACP_AXI2DAGB_SEM_12 0x5178
335 #define mmACP_AXI2DAGB_SEM_13 0x5179
336 #define mmACP_AXI2DAGB_SEM_14 0x517a
337 #define mmACP_AXI2DAGB_SEM_15 0x517b
338 #define mmACP_AXI2DAGB_SEM_16 0x517c
339 #define mmACP_AXI2DAGB_SEM_17 0x517d
340 #define mmACP_AXI2DAGB_SEM_18 0x517e
341 #define mmACP_AXI2DAGB_SEM_19 0x517f
342 #define mmACP_AXI2DAGB_SEM_20 0x5180
343 #define mmACP_AXI2DAGB_SEM_21 0x5181
344 #define mmACP_AXI2DAGB_SEM_22 0x5182
345 #define mmACP_AXI2DAGB_SEM_23 0x5183
346 #define mmACP_AXI2DAGB_SEM_24 0x5184
347 #define mmACP_AXI2DAGB_SEM_25 0x5185
348 #define mmACP_AXI2DAGB_SEM_26 0x5186
349 #define mmACP_AXI2DAGB_SEM_27 0x5187
350 #define mmACP_AXI2DAGB_SEM_28 0x5188
351 #define mmACP_AXI2DAGB_SEM_29 0x5189
352 #define mmACP_AXI2DAGB_SEM_30 0x518a
353 #define mmACP_AXI2DAGB_SEM_31 0x518b
354 #define mmACP_AXI2DAGB_SEM_32 0x518c
355 #define mmACP_AXI2DAGB_SEM_33 0x518d
356 #define mmACP_AXI2DAGB_SEM_34 0x518e
357 #define mmACP_AXI2DAGB_SEM_35 0x518f
358 #define mmACP_AXI2DAGB_SEM_36 0x5190
359 #define mmACP_AXI2DAGB_SEM_37 0x5191
360 #define mmACP_AXI2DAGB_SEM_38 0x5192
361 #define mmACP_AXI2DAGB_SEM_39 0x5193
362 #define mmACP_AXI2DAGB_SEM_40 0x5194
363 #define mmACP_AXI2DAGB_SEM_41 0x5195
364 #define mmACP_AXI2DAGB_SEM_42 0x5196
365 #define mmACP_AXI2DAGB_SEM_43 0x5197
366 #define mmACP_AXI2DAGB_SEM_44 0x5198
367 #define mmACP_AXI2DAGB_SEM_45 0x5199
368 #define mmACP_AXI2DAGB_SEM_46 0x519a
369 #define mmACP_AXI2DAGB_SEM_47 0x519b
370 #define mmACP_SRBM_Client_Base_Addr 0x519c
371 #define mmACP_SRBM_Client_RDDATA 0x519d
372 #define mmACP_SRBM_Cycle_Sts 0x519e
373 #define mmACP_SRBM_Targ_Idx_Addr 0x519f
374 #define mmACP_SRBM_Targ_Idx_Data 0x51a0
375 #define mmACP_SEMA_ADDR_LOW 0x51a1
376 #define mmACP_SEMA_ADDR_HIGH 0x51a2
377 #define mmACP_SEMA_CMD 0x51a3
378 #define mmACP_SEMA_STS 0x51a4
379 #define mmACP_SEMA_REQ 0x51a5
380 #define mmACP_FW_STATUS 0x51a6
381 #define mmACP_FUTURE_REG_ACLK_0 0x51a7
382 #define mmACP_FUTURE_REG_ACLK_1 0x51a8
383 #define mmACP_FUTURE_REG_ACLK_2 0x51a9
384 #define mmACP_FUTURE_REG_ACLK_3 0x51aa
385 #define mmACP_FUTURE_REG_ACLK_4 0x51ab
386 #define mmACP_TIMER 0x51ac
387 #define mmACP_TIMER_CNTL 0x51ad
388 #define mmACP_DSP0_TIMER 0x51ae
389 #define mmACP_DSP1_TIMER 0x51af
390 #define mmACP_DSP2_TIMER 0x51b0
391 #define mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH 0x51b1
392 #define mmACP_I2S_TRANSMIT_BYTE_CNT_LOW 0x51b2
393 #define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH 0x51b3
394 #define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW 0x51b4
395 #define mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH 0x51b5
396 #define mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW 0x51b6
397 #define mmACP_DSP0_CS_STATE 0x51b7
398 #define mmACP_DSP1_CS_STATE 0x51b8
399 #define mmACP_DSP2_CS_STATE 0x51b9
400 #define mmACP_SCRATCH_REG_BASE_ADDR 0x51ba
401 #define mmCC_ACP_EFUSE 0x51c8
402 #define mmACP_PGFSM_RETAIN_REG 0x51c9
403 #define mmACP_PGFSM_CONFIG_REG 0x51ca
404 #define mmACP_PGFSM_WRITE_REG 0x51cb
405 #define mmACP_PGFSM_READ_REG_0 0x51cc
406 #define mmACP_PGFSM_READ_REG_1 0x51cd
407 #define mmACP_PGFSM_READ_REG_2 0x51ce
408 #define mmACP_PGFSM_READ_REG_3 0x51cf
409 #define mmACP_PGFSM_READ_REG_4 0x51d0
410 #define mmACP_PGFSM_READ_REG_5 0x51d1
411 #define mmACP_IP_PGFSM_ENABLE 0x51d2
412 #define mmACP_I2S_PIN_CONFIG 0x51d3
413 #define mmACP_AZALIA_I2S_SELECT 0x51d4
414 #define mmACP_CHIP_PKG_FOR_PAD_ISOLATION 0x51d5
415 #define mmACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL 0x51d6
416 #define mmACP_BT_UART_PAD_SEL 0x51d7
417 #define mmACP_SCRATCH_REG_0 0x52c0
418 #define mmACP_SCRATCH_REG_1 0x52c1
419 #define mmACP_SCRATCH_REG_2 0x52c2
420 #define mmACP_SCRATCH_REG_3 0x52c3
421 #define mmACP_SCRATCH_REG_4 0x52c4
422 #define mmACP_SCRATCH_REG_5 0x52c5
423 #define mmACP_SCRATCH_REG_6 0x52c6
424 #define mmACP_SCRATCH_REG_7 0x52c7
425 #define mmACP_SCRATCH_REG_8 0x52c8
426 #define mmACP_SCRATCH_REG_9 0x52c9
427 #define mmACP_SCRATCH_REG_10 0x52ca
428 #define mmACP_SCRATCH_REG_11 0x52cb
429 #define mmACP_SCRATCH_REG_12 0x52cc
430 #define mmACP_SCRATCH_REG_13 0x52cd
431 #define mmACP_SCRATCH_REG_14 0x52ce
432 #define mmACP_SCRATCH_REG_15 0x52cf
433 #define mmACP_SCRATCH_REG_16 0x52d0
434 #define mmACP_SCRATCH_REG_17 0x52d1
435 #define mmACP_SCRATCH_REG_18 0x52d2
436 #define mmACP_SCRATCH_REG_19 0x52d3
437 #define mmACP_SCRATCH_REG_20 0x52d4
438 #define mmACP_SCRATCH_REG_21 0x52d5
439 #define mmACP_SCRATCH_REG_22 0x52d6
440 #define mmACP_SCRATCH_REG_23 0x52d7
441 #define mmACP_SCRATCH_REG_24 0x52d8
442 #define mmACP_SCRATCH_REG_25 0x52d9
443 #define mmACP_SCRATCH_REG_26 0x52da
444 #define mmACP_SCRATCH_REG_27 0x52db
445 #define mmACP_SCRATCH_REG_28 0x52dc
446 #define mmACP_SCRATCH_REG_29 0x52dd
447 #define mmACP_SCRATCH_REG_30 0x52de
448 #define mmACP_SCRATCH_REG_31 0x52df
449 #define mmACP_SCRATCH_REG_32 0x52e0
450 #define mmACP_SCRATCH_REG_33 0x52e1
451 #define mmACP_SCRATCH_REG_34 0x52e2
452 #define mmACP_SCRATCH_REG_35 0x52e3
453 #define mmACP_SCRATCH_REG_36 0x52e4
454 #define mmACP_SCRATCH_REG_37 0x52e5
455 #define mmACP_SCRATCH_REG_38 0x52e6
456 #define mmACP_SCRATCH_REG_39 0x52e7
457 #define mmACP_SCRATCH_REG_40 0x52e8
458 #define mmACP_SCRATCH_REG_41 0x52e9
459 #define mmACP_SCRATCH_REG_42 0x52ea
460 #define mmACP_SCRATCH_REG_43 0x52eb
461 #define mmACP_SCRATCH_REG_44 0x52ec
462 #define mmACP_SCRATCH_REG_45 0x52ed
463 #define mmACP_SCRATCH_REG_46 0x52ee
464 #define mmACP_SCRATCH_REG_47 0x52ef
465 #define mmACP_VOICE_WAKEUP_ENABLE 0x51e8
466 #define mmACP_VOICE_WAKEUP_STATUS 0x51e9
467 #define mmI2S_VOICE_WAKEUP_LOWER_THRESHOLD 0x51ea
468 #define mmI2S_VOICE_WAKEUP_HIGHER_THRESHOLD 0x51eb
469 #define mmI2S_VOICE_WAKEUP_NO_OF_SAMPLES 0x51ec
470 #define mmI2S_VOICE_WAKEUP_NO_OF_PEAKS 0x51ed
471 #define mmI2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS 0x51ee
472 #define mmI2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION 0x51ef
473 #define mmI2S_VOICE_WAKEUP_DATA_PATH_SWITCH 0x51f0
474 #define mmI2S_VOICE_WAKEUP_DATA_POINTER 0x51f1
475 #define mmI2S_VOICE_WAKEUP_AUTH_MATCH 0x51f2
476 #define mmI2S_VOICE_WAKEUP_8KB_WRAP 0x51f3
477 #define mmACP_I2S_RECEIVED_BYTE_CNT_HIGH 0x51f4
478 #define mmACP_I2S_RECEIVED_BYTE_CNT_LOW 0x51f5
479 #define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH 0x51f6
480 #define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW 0x51f7
481 #define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
482 #define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
483 #define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
484 #define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
485 #define mmACP_MEM_DEEP_SLEEP_REQ_LO 0x51fc
486 #define mmACP_MEM_DEEP_SLEEP_REQ_HI 0x51fd
487 #define mmACP_MEM_DEEP_SLEEP_STS_LO 0x51fe
488 #define mmACP_MEM_DEEP_SLEEP_STS_HI 0x51ff
489 #define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO 0x5200
490 #define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI 0x5201
491 #define mmACP_MEM_WAKEUP_FROM_SLEEP_LO 0x5202
492 #define mmACP_MEM_WAKEUP_FROM_SLEEP_HI 0x5203
493 #define mmACP_I2SSP_IER 0x5210
494 #define mmACP_I2SSP_IRER 0x5211
495 #define mmACP_I2SSP_ITER 0x5212
496 #define mmACP_I2SSP_CER 0x5213
497 #define mmACP_I2SSP_CCR 0x5214
498 #define mmACP_I2SSP_RXFFR 0x5215
499 #define mmACP_I2SSP_TXFFR 0x5216
500 #define mmACP_I2SSP_LRBR0 0x5218
501 #define mmACP_I2SSP_RRBR0 0x5219
502 #define mmACP_I2SSP_RER0 0x521a
503 #define mmACP_I2SSP_TER0 0x521b
504 #define mmACP_I2SSP_RCR0 0x521c
505 #define mmACP_I2SSP_TCR0 0x521d
506 #define mmACP_I2SSP_ISR0 0x521e
507 #define mmACP_I2SSP_IMR0 0x521f
508 #define mmACP_I2SSP_ROR0 0x5220
509 #define mmACP_I2SSP_TOR0 0x5221
510 #define mmACP_I2SSP_RFCR0 0x5222
511 #define mmACP_I2SSP_TFCR0 0x5223
512 #define mmACP_I2SSP_RFF0 0x5224
513 #define mmACP_I2SSP_TFF0 0x5225
514 #define mmACP_I2SSP_RXDMA 0x5226
515 #define mmACP_I2SSP_RRXDMA 0x5227
516 #define mmACP_I2SSP_TXDMA 0x5228
517 #define mmACP_I2SSP_RTXDMA 0x5229
518 #define mmACP_I2SSP_COMP_PARAM_2 0x522a
519 #define mmACP_I2SSP_COMP_PARAM_1 0x522b
520 #define mmACP_I2SSP_COMP_VERSION 0x522c
521 #define mmACP_I2SSP_COMP_TYPE 0x522d
522 #define mmACP_I2SMICSP_IER 0x522e
523 #define mmACP_I2SMICSP_IRER 0x522f
524 #define mmACP_I2SMICSP_ITER 0x5230
525 #define mmACP_I2SMICSP_CER 0x5231
526 #define mmACP_I2SMICSP_CCR 0x5232
527 #define mmACP_I2SMICSP_RXFFR 0x5233
528 #define mmACP_I2SMICSP_TXFFR 0x5234
529 #define mmACP_I2SMICSP_LRBR0 0x5236
530 #define mmACP_I2SMICSP_RRBR0 0x5237
531 #define mmACP_I2SMICSP_RER0 0x5238
532 #define mmACP_I2SMICSP_TER0 0x5239
533 #define mmACP_I2SMICSP_RCR0 0x523a
534 #define mmACP_I2SMICSP_TCR0 0x523b
535 #define mmACP_I2SMICSP_ISR0 0x523c
536 #define mmACP_I2SMICSP_IMR0 0x523d
537 #define mmACP_I2SMICSP_ROR0 0x523e
538 #define mmACP_I2SMICSP_TOR0 0x523f
539 #define mmACP_I2SMICSP_RFCR0 0x5240
540 #define mmACP_I2SMICSP_TFCR0 0x5241
541 #define mmACP_I2SMICSP_RFF0 0x5242
542 #define mmACP_I2SMICSP_TFF0 0x5243
543 #define mmACP_I2SMICSP_LRBR1 0x5246
544 #define mmACP_I2SMICSP_RRBR1 0x5247
545 #define mmACP_I2SMICSP_RER1 0x5248
546 #define mmACP_I2SMICSP_TER1 0x5249
547 #define mmACP_I2SMICSP_RCR1 0x524a
548 #define mmACP_I2SMICSP_TCR1 0x524b
549 #define mmACP_I2SMICSP_ISR1 0x524c
550 #define mmACP_I2SMICSP_IMR1 0x524d
551 #define mmACP_I2SMICSP_ROR1 0x524e
552 #define mmACP_I2SMICSP_TOR1 0x524f
553 #define mmACP_I2SMICSP_RFCR1 0x5250
554 #define mmACP_I2SMICSP_TFCR1 0x5251
555 #define mmACP_I2SMICSP_RFF1 0x5252
556 #define mmACP_I2SMICSP_TFF1 0x5253
557 #define mmACP_I2SMICSP_RXDMA 0x5254
558 #define mmACP_I2SMICSP_RRXDMA 0x5255
559 #define mmACP_I2SMICSP_TXDMA 0x5256
560 #define mmACP_I2SMICSP_RTXDMA 0x5257
561 #define mmACP_I2SMICSP_COMP_PARAM_2 0x5258
562 #define mmACP_I2SMICSP_COMP_PARAM_1 0x5259
563 #define mmACP_I2SMICSP_COMP_VERSION 0x525a
564 #define mmACP_I2SMICSP_COMP_TYPE 0x525b
565 #define mmACP_I2SBT_IER 0x525c
566 #define mmACP_I2SBT_IRER 0x525d
567 #define mmACP_I2SBT_ITER 0x525e
568 #define mmACP_I2SBT_CER 0x525f
569 #define mmACP_I2SBT_CCR 0x5260
570 #define mmACP_I2SBT_RXFFR 0x5261
571 #define mmACP_I2SBT_TXFFR 0x5262
572 #define mmACP_I2SBT_LRBR0 0x5264
573 #define mmACP_I2SBT_RRBR0 0x5265
574 #define mmACP_I2SBT_RER0 0x5266
575 #define mmACP_I2SBT_TER0 0x5267
576 #define mmACP_I2SBT_RCR0 0x5268
577 #define mmACP_I2SBT_TCR0 0x5269
578 #define mmACP_I2SBT_ISR0 0x526a
579 #define mmACP_I2SBT_IMR0 0x526b
580 #define mmACP_I2SBT_ROR0 0x526c
581 #define mmACP_I2SBT_TOR0 0x526d
582 #define mmACP_I2SBT_RFCR0 0x526e
583 #define mmACP_I2SBT_TFCR0 0x526f
584 #define mmACP_I2SBT_RFF0 0x5270
585 #define mmACP_I2SBT_TFF0 0x5271
586 #define mmACP_I2SBT_LRBR1 0x5274
587 #define mmACP_I2SBT_RRBR1 0x5275
588 #define mmACP_I2SBT_RER1 0x5276
589 #define mmACP_I2SBT_TER1 0x5277
590 #define mmACP_I2SBT_RCR1 0x5278
591 #define mmACP_I2SBT_TCR1 0x5279
592 #define mmACP_I2SBT_ISR1 0x527a
593 #define mmACP_I2SBT_IMR1 0x527b
594 #define mmACP_I2SBT_ROR1 0x527c
595 #define mmACP_I2SBT_TOR1 0x527d
596 #define mmACP_I2SBT_RFCR1 0x527e
597 #define mmACP_I2SBT_TFCR1 0x527f
598 #define mmACP_I2SBT_RFF1 0x5280
599 #define mmACP_I2SBT_TFF1 0x5281
600 #define mmACP_I2SBT_RXDMA 0x5282
601 #define mmACP_I2SBT_RRXDMA 0x5283
602 #define mmACP_I2SBT_TXDMA 0x5284
603 #define mmACP_I2SBT_RTXDMA 0x5285
604 #define mmACP_I2SBT_COMP_PARAM_2 0x5286
605 #define mmACP_I2SBT_COMP_PARAM_1 0x5287
606 #define mmACP_I2SBT_COMP_VERSION 0x5288
607 #define mmACP_I2SBT_COMP_TYPE 0x5289
608
609 #endif