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12 #ifndef UX500_msp_dai_H
13 #define UX500_msp_dai_H
14
15 #include <linux/types.h>
16 #include <linux/spinlock.h>
17
18 #include "ux500_msp_i2s.h"
19
20 #define UX500_NBR_OF_DAI 4
21
22 #define UX500_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | \
23 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
24
25 #define UX500_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
26
27 #define FRAME_PER_SINGLE_SLOT_8_KHZ 31
28 #define FRAME_PER_SINGLE_SLOT_16_KHZ 124
29 #define FRAME_PER_SINGLE_SLOT_44_1_KHZ 63
30 #define FRAME_PER_SINGLE_SLOT_48_KHZ 49
31 #define FRAME_PER_2_SLOTS 31
32 #define FRAME_PER_8_SLOTS 138
33 #define FRAME_PER_16_SLOTS 277
34
35 #define UX500_MSP_INTERNAL_CLOCK_FREQ 40000000
36 #define UX500_MSP1_INTERNAL_CLOCK_FREQ UX500_MSP_INTERNAL_CLOCK_FREQ
37
38 #define UX500_MSP_MIN_CHANNELS 1
39 #define UX500_MSP_MAX_CHANNELS 8
40
41 #define PLAYBACK_CONFIGURED 1
42 #define CAPTURE_CONFIGURED 2
43
44 enum ux500_msp_clock_id {
45 UX500_MSP_MASTER_CLOCK,
46 };
47
48 struct ux500_msp_i2s_drvdata {
49 struct ux500_msp *msp;
50 struct regulator *reg_vape;
51 unsigned int fmt;
52 unsigned int tx_mask;
53 unsigned int rx_mask;
54 int slots;
55 int slot_width;
56
57
58 unsigned int master_clk;
59 struct clk *clk;
60 struct clk *pclk;
61
62
63 int vape_opp_constraint;
64 };
65
66 int ux500_msp_dai_set_data_delay(struct snd_soc_dai *dai, int delay);
67
68 #endif