root/sound/soc/stm/stm32_spdifrx.c

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DEFINITIONS

This source file includes following definitions.
  1. stm32_spdifrx_dma_complete
  2. stm32_spdifrx_dma_ctrl_start
  3. stm32_spdifrx_dma_ctrl_stop
  4. stm32_spdifrx_start_sync
  5. stm32_spdifrx_stop
  6. stm32_spdifrx_dma_ctrl_register
  7. stm32_spdifrx_info
  8. stm32_spdifrx_ub_info
  9. stm32_spdifrx_get_ctrl_data
  10. stm32_spdifrx_capture_get
  11. stm32_spdif_user_bits_get
  12. stm32_spdifrx_dai_register_ctrls
  13. stm32_spdifrx_dai_probe
  14. stm32_spdifrx_readable_reg
  15. stm32_spdifrx_volatile_reg
  16. stm32_spdifrx_writeable_reg
  17. stm32_spdifrx_isr
  18. stm32_spdifrx_startup
  19. stm32_spdifrx_hw_params
  20. stm32_spdifrx_trigger
  21. stm32_spdifrx_shutdown
  22. stm32_spdifrx_parse_of
  23. stm32_spdifrx_probe
  24. stm32_spdifrx_remove
  25. stm32_spdifrx_suspend
  26. stm32_spdifrx_resume

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver.
   4  *
   5  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   6  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
   7  */
   8 
   9 #include <linux/bitfield.h>
  10 #include <linux/clk.h>
  11 #include <linux/completion.h>
  12 #include <linux/delay.h>
  13 #include <linux/module.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/regmap.h>
  16 #include <linux/reset.h>
  17 
  18 #include <sound/dmaengine_pcm.h>
  19 #include <sound/pcm_params.h>
  20 
  21 /* SPDIF-rx Register Map */
  22 #define STM32_SPDIFRX_CR        0x00
  23 #define STM32_SPDIFRX_IMR       0x04
  24 #define STM32_SPDIFRX_SR        0x08
  25 #define STM32_SPDIFRX_IFCR      0x0C
  26 #define STM32_SPDIFRX_DR        0x10
  27 #define STM32_SPDIFRX_CSR       0x14
  28 #define STM32_SPDIFRX_DIR       0x18
  29 #define STM32_SPDIFRX_VERR      0x3F4
  30 #define STM32_SPDIFRX_IDR       0x3F8
  31 #define STM32_SPDIFRX_SIDR      0x3FC
  32 
  33 /* Bit definition for SPDIF_CR register */
  34 #define SPDIFRX_CR_SPDIFEN_SHIFT        0
  35 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
  36 #define SPDIFRX_CR_SPDIFENSET(x)        ((x) << SPDIFRX_CR_SPDIFEN_SHIFT)
  37 
  38 #define SPDIFRX_CR_RXDMAEN      BIT(2)
  39 #define SPDIFRX_CR_RXSTEO       BIT(3)
  40 
  41 #define SPDIFRX_CR_DRFMT_SHIFT  4
  42 #define SPDIFRX_CR_DRFMT_MASK   GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
  43 #define SPDIFRX_CR_DRFMTSET(x)  ((x) << SPDIFRX_CR_DRFMT_SHIFT)
  44 
  45 #define SPDIFRX_CR_PMSK         BIT(6)
  46 #define SPDIFRX_CR_VMSK         BIT(7)
  47 #define SPDIFRX_CR_CUMSK        BIT(8)
  48 #define SPDIFRX_CR_PTMSK        BIT(9)
  49 #define SPDIFRX_CR_CBDMAEN      BIT(10)
  50 #define SPDIFRX_CR_CHSEL_SHIFT  11
  51 #define SPDIFRX_CR_CHSEL        BIT(SPDIFRX_CR_CHSEL_SHIFT)
  52 
  53 #define SPDIFRX_CR_NBTR_SHIFT   12
  54 #define SPDIFRX_CR_NBTR_MASK    GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
  55 #define SPDIFRX_CR_NBTRSET(x)   ((x) << SPDIFRX_CR_NBTR_SHIFT)
  56 
  57 #define SPDIFRX_CR_WFA          BIT(14)
  58 
  59 #define SPDIFRX_CR_INSEL_SHIFT  16
  60 #define SPDIFRX_CR_INSEL_MASK   GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
  61 #define SPDIFRX_CR_INSELSET(x)  ((x) << SPDIFRX_CR_INSEL_SHIFT)
  62 
  63 #define SPDIFRX_CR_CKSEN_SHIFT  20
  64 #define SPDIFRX_CR_CKSEN        BIT(20)
  65 #define SPDIFRX_CR_CKSBKPEN     BIT(21)
  66 
  67 /* Bit definition for SPDIFRX_IMR register */
  68 #define SPDIFRX_IMR_RXNEI       BIT(0)
  69 #define SPDIFRX_IMR_CSRNEIE     BIT(1)
  70 #define SPDIFRX_IMR_PERRIE      BIT(2)
  71 #define SPDIFRX_IMR_OVRIE       BIT(3)
  72 #define SPDIFRX_IMR_SBLKIE      BIT(4)
  73 #define SPDIFRX_IMR_SYNCDIE     BIT(5)
  74 #define SPDIFRX_IMR_IFEIE       BIT(6)
  75 
  76 #define SPDIFRX_XIMR_MASK       GENMASK(6, 0)
  77 
  78 /* Bit definition for SPDIFRX_SR register */
  79 #define SPDIFRX_SR_RXNE         BIT(0)
  80 #define SPDIFRX_SR_CSRNE        BIT(1)
  81 #define SPDIFRX_SR_PERR         BIT(2)
  82 #define SPDIFRX_SR_OVR          BIT(3)
  83 #define SPDIFRX_SR_SBD          BIT(4)
  84 #define SPDIFRX_SR_SYNCD        BIT(5)
  85 #define SPDIFRX_SR_FERR         BIT(6)
  86 #define SPDIFRX_SR_SERR         BIT(7)
  87 #define SPDIFRX_SR_TERR         BIT(8)
  88 
  89 #define SPDIFRX_SR_WIDTH5_SHIFT 16
  90 #define SPDIFRX_SR_WIDTH5_MASK  GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
  91 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT)
  92 
  93 /* Bit definition for SPDIFRX_IFCR register */
  94 #define SPDIFRX_IFCR_PERRCF     BIT(2)
  95 #define SPDIFRX_IFCR_OVRCF      BIT(3)
  96 #define SPDIFRX_IFCR_SBDCF      BIT(4)
  97 #define SPDIFRX_IFCR_SYNCDCF    BIT(5)
  98 
  99 #define SPDIFRX_XIFCR_MASK      GENMASK(5, 2)
 100 
 101 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */
 102 #define SPDIFRX_DR0_DR_SHIFT    0
 103 #define SPDIFRX_DR0_DR_MASK     GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
 104 #define SPDIFRX_DR0_DRSET(x)    ((x) << SPDIFRX_DR0_DR_SHIFT)
 105 
 106 #define SPDIFRX_DR0_PE          BIT(24)
 107 
 108 #define SPDIFRX_DR0_V           BIT(25)
 109 #define SPDIFRX_DR0_U           BIT(26)
 110 #define SPDIFRX_DR0_C           BIT(27)
 111 
 112 #define SPDIFRX_DR0_PT_SHIFT    28
 113 #define SPDIFRX_DR0_PT_MASK     GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
 114 #define SPDIFRX_DR0_PTSET(x)    ((x) << SPDIFRX_DR0_PT_SHIFT)
 115 
 116 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */
 117 #define  SPDIFRX_DR1_PE         BIT(0)
 118 #define  SPDIFRX_DR1_V          BIT(1)
 119 #define  SPDIFRX_DR1_U          BIT(2)
 120 #define  SPDIFRX_DR1_C          BIT(3)
 121 
 122 #define  SPDIFRX_DR1_PT_SHIFT   4
 123 #define  SPDIFRX_DR1_PT_MASK    GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
 124 #define  SPDIFRX_DR1_PTSET(x)   ((x) << SPDIFRX_DR1_PT_SHIFT)
 125 
 126 #define SPDIFRX_DR1_DR_SHIFT    8
 127 #define SPDIFRX_DR1_DR_MASK     GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
 128 #define SPDIFRX_DR1_DRSET(x)    ((x) << SPDIFRX_DR1_DR_SHIFT)
 129 
 130 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */
 131 #define SPDIFRX_DR1_DRNL1_SHIFT 0
 132 #define SPDIFRX_DR1_DRNL1_MASK  GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
 133 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT)
 134 
 135 #define SPDIFRX_DR1_DRNL2_SHIFT 16
 136 #define SPDIFRX_DR1_DRNL2_MASK  GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
 137 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT)
 138 
 139 /* Bit definition for SPDIFRX_CSR register */
 140 #define SPDIFRX_CSR_USR_SHIFT   0
 141 #define SPDIFRX_CSR_USR_MASK    GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
 142 #define SPDIFRX_CSR_USRGET(x)   (((x) & SPDIFRX_CSR_USR_MASK)\
 143                                 >> SPDIFRX_CSR_USR_SHIFT)
 144 
 145 #define SPDIFRX_CSR_CS_SHIFT    16
 146 #define SPDIFRX_CSR_CS_MASK     GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
 147 #define SPDIFRX_CSR_CSGET(x)    (((x) & SPDIFRX_CSR_CS_MASK)\
 148                                 >> SPDIFRX_CSR_CS_SHIFT)
 149 
 150 #define SPDIFRX_CSR_SOB         BIT(24)
 151 
 152 /* Bit definition for SPDIFRX_DIR register */
 153 #define SPDIFRX_DIR_THI_SHIFT   0
 154 #define SPDIFRX_DIR_THI_MASK    GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
 155 #define SPDIFRX_DIR_THI_SET(x)  ((x) << SPDIFRX_DIR_THI_SHIFT)
 156 
 157 #define SPDIFRX_DIR_TLO_SHIFT   16
 158 #define SPDIFRX_DIR_TLO_MASK    GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
 159 #define SPDIFRX_DIR_TLO_SET(x)  ((x) << SPDIFRX_DIR_TLO_SHIFT)
 160 
 161 #define SPDIFRX_SPDIFEN_DISABLE 0x0
 162 #define SPDIFRX_SPDIFEN_SYNC    0x1
 163 #define SPDIFRX_SPDIFEN_ENABLE  0x3
 164 
 165 /* Bit definition for SPDIFRX_VERR register */
 166 #define SPDIFRX_VERR_MIN_MASK   GENMASK(3, 0)
 167 #define SPDIFRX_VERR_MAJ_MASK   GENMASK(7, 4)
 168 
 169 /* Bit definition for SPDIFRX_IDR register */
 170 #define SPDIFRX_IDR_ID_MASK     GENMASK(31, 0)
 171 
 172 /* Bit definition for SPDIFRX_SIDR register */
 173 #define SPDIFRX_SIDR_SID_MASK   GENMASK(31, 0)
 174 
 175 #define SPDIFRX_IPIDR_NUMBER    0x00130041
 176 
 177 #define SPDIFRX_IN1             0x1
 178 #define SPDIFRX_IN2             0x2
 179 #define SPDIFRX_IN3             0x3
 180 #define SPDIFRX_IN4             0x4
 181 #define SPDIFRX_IN5             0x5
 182 #define SPDIFRX_IN6             0x6
 183 #define SPDIFRX_IN7             0x7
 184 #define SPDIFRX_IN8             0x8
 185 
 186 #define SPDIFRX_NBTR_NONE       0x0
 187 #define SPDIFRX_NBTR_3          0x1
 188 #define SPDIFRX_NBTR_15         0x2
 189 #define SPDIFRX_NBTR_63         0x3
 190 
 191 #define SPDIFRX_DRFMT_RIGHT     0x0
 192 #define SPDIFRX_DRFMT_LEFT      0x1
 193 #define SPDIFRX_DRFMT_PACKED    0x2
 194 
 195 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */
 196 #define SPDIFRX_CS_BYTES_NB     24
 197 #define SPDIFRX_UB_BYTES_NB     48
 198 
 199 /*
 200  * CSR register is retrieved as a 32 bits word
 201  * It contains 1 channel status byte and 2 user data bytes
 202  * 2 S/PDIF frames are acquired to get all CS/UB bits
 203  */
 204 #define SPDIFRX_CSR_BUF_LENGTH  (SPDIFRX_CS_BYTES_NB * 4 * 2)
 205 
 206 /**
 207  * struct stm32_spdifrx_data - private data of SPDIFRX
 208  * @pdev: device data pointer
 209  * @base: mmio register base virtual address
 210  * @regmap: SPDIFRX register map pointer
 211  * @regmap_conf: SPDIFRX register map configuration pointer
 212  * @cs_completion: channel status retrieving completion
 213  * @kclk: kernel clock feeding the SPDIFRX clock generator
 214  * @dma_params: dma configuration data for rx channel
 215  * @substream: PCM substream data pointer
 216  * @dmab: dma buffer info pointer
 217  * @ctrl_chan: dma channel for S/PDIF control bits
 218  * @desc:dma async transaction descriptor
 219  * @slave_config: dma slave channel runtime config pointer
 220  * @phys_addr: SPDIFRX registers physical base address
 221  * @lock: synchronization enabling lock
 222  * @irq_lock: prevent race condition with IRQ on stream state
 223  * @cs: channel status buffer
 224  * @ub: user data buffer
 225  * @irq: SPDIFRX interrupt line
 226  * @refcount: keep count of opened DMA channels
 227  */
 228 struct stm32_spdifrx_data {
 229         struct platform_device *pdev;
 230         void __iomem *base;
 231         struct regmap *regmap;
 232         const struct regmap_config *regmap_conf;
 233         struct completion cs_completion;
 234         struct clk *kclk;
 235         struct snd_dmaengine_dai_dma_data dma_params;
 236         struct snd_pcm_substream *substream;
 237         struct snd_dma_buffer *dmab;
 238         struct dma_chan *ctrl_chan;
 239         struct dma_async_tx_descriptor *desc;
 240         struct dma_slave_config slave_config;
 241         dma_addr_t phys_addr;
 242         spinlock_t lock;  /* Sync enabling lock */
 243         spinlock_t irq_lock; /* Prevent race condition on stream state */
 244         unsigned char cs[SPDIFRX_CS_BYTES_NB];
 245         unsigned char ub[SPDIFRX_UB_BYTES_NB];
 246         int irq;
 247         int refcount;
 248 };
 249 
 250 static void stm32_spdifrx_dma_complete(void *data)
 251 {
 252         struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
 253         struct platform_device *pdev = spdifrx->pdev;
 254         u32 *p_start = (u32 *)spdifrx->dmab->area;
 255         u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
 256         u32 *ptr = p_start;
 257         u16 *ub_ptr = (short *)spdifrx->ub;
 258         int i = 0;
 259 
 260         regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
 261                            SPDIFRX_CR_CBDMAEN,
 262                            (unsigned int)~SPDIFRX_CR_CBDMAEN);
 263 
 264         if (!spdifrx->dmab->area)
 265                 return;
 266 
 267         while (ptr <= p_end) {
 268                 if (*ptr & SPDIFRX_CSR_SOB)
 269                         break;
 270                 ptr++;
 271         }
 272 
 273         if (ptr > p_end) {
 274                 dev_err(&pdev->dev, "Start of S/PDIF block not found\n");
 275                 return;
 276         }
 277 
 278         while (i < SPDIFRX_CS_BYTES_NB) {
 279                 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr);
 280                 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++);
 281                 if (ptr > p_end) {
 282                         dev_err(&pdev->dev, "Failed to get channel status\n");
 283                         return;
 284                 }
 285                 i++;
 286         }
 287 
 288         complete(&spdifrx->cs_completion);
 289 }
 290 
 291 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx)
 292 {
 293         dma_cookie_t cookie;
 294         int err;
 295 
 296         spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan,
 297                                                     spdifrx->dmab->addr,
 298                                                     SPDIFRX_CSR_BUF_LENGTH,
 299                                                     DMA_DEV_TO_MEM,
 300                                                     DMA_CTRL_ACK);
 301         if (!spdifrx->desc)
 302                 return -EINVAL;
 303 
 304         spdifrx->desc->callback = stm32_spdifrx_dma_complete;
 305         spdifrx->desc->callback_param = spdifrx;
 306         cookie = dmaengine_submit(spdifrx->desc);
 307         err = dma_submit_error(cookie);
 308         if (err)
 309                 return -EINVAL;
 310 
 311         dma_async_issue_pending(spdifrx->ctrl_chan);
 312 
 313         return 0;
 314 }
 315 
 316 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
 317 {
 318         dmaengine_terminate_async(spdifrx->ctrl_chan);
 319 }
 320 
 321 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
 322 {
 323         int cr, cr_mask, imr, ret;
 324         unsigned long flags;
 325 
 326         /* Enable IRQs */
 327         imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
 328         ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr);
 329         if (ret)
 330                 return ret;
 331 
 332         spin_lock_irqsave(&spdifrx->lock, flags);
 333 
 334         spdifrx->refcount++;
 335 
 336         regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
 337 
 338         if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) {
 339                 /*
 340                  * Start sync if SPDIFRX is still in idle state.
 341                  * SPDIFRX reception enabled when sync done
 342                  */
 343                 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n");
 344 
 345                 /*
 346                  * SPDIFRX configuration:
 347                  * Wait for activity before starting sync process. This avoid
 348                  * to issue sync errors when spdif signal is missing on input.
 349                  * Preamble, CS, user, validity and parity error bits not copied
 350                  * to DR register.
 351                  */
 352                 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK |
 353                      SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO;
 354                 cr_mask = cr;
 355 
 356                 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
 357                 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK;
 358                 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
 359                                          cr_mask, cr);
 360                 if (ret < 0)
 361                         dev_err(&spdifrx->pdev->dev,
 362                                 "Failed to start synchronization\n");
 363         }
 364 
 365         spin_unlock_irqrestore(&spdifrx->lock, flags);
 366 
 367         return ret;
 368 }
 369 
 370 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
 371 {
 372         int cr, cr_mask, reg;
 373         unsigned long flags;
 374 
 375         spin_lock_irqsave(&spdifrx->lock, flags);
 376 
 377         if (--spdifrx->refcount) {
 378                 spin_unlock_irqrestore(&spdifrx->lock, flags);
 379                 return;
 380         }
 381 
 382         cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
 383         cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
 384 
 385         regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr);
 386 
 387         regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
 388                            SPDIFRX_XIMR_MASK, 0);
 389 
 390         regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
 391                            SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK);
 392 
 393         /* dummy read to clear CSRNE and RXNE in status register */
 394         regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, &reg);
 395         regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, &reg);
 396 
 397         spin_unlock_irqrestore(&spdifrx->lock, flags);
 398 }
 399 
 400 static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
 401                                            struct stm32_spdifrx_data *spdifrx)
 402 {
 403         int ret;
 404 
 405         spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
 406         if (IS_ERR(spdifrx->ctrl_chan)) {
 407                 dev_err(dev, "dma_request_slave_channel failed\n");
 408                 return PTR_ERR(spdifrx->ctrl_chan);
 409         }
 410 
 411         spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
 412                                      GFP_KERNEL);
 413         if (!spdifrx->dmab)
 414                 return -ENOMEM;
 415 
 416         spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM;
 417         spdifrx->dmab->dev.dev = dev;
 418         ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev,
 419                                   SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab);
 420         if (ret < 0) {
 421                 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret);
 422                 return ret;
 423         }
 424 
 425         spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
 426         spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
 427                                          STM32_SPDIFRX_CSR);
 428         spdifrx->slave_config.dst_addr = spdifrx->dmab->addr;
 429         spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 430         spdifrx->slave_config.src_maxburst = 1;
 431 
 432         ret = dmaengine_slave_config(spdifrx->ctrl_chan,
 433                                      &spdifrx->slave_config);
 434         if (ret < 0) {
 435                 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
 436                 spdifrx->ctrl_chan = NULL;
 437         }
 438 
 439         return ret;
 440 };
 441 
 442 static const char * const spdifrx_enum_input[] = {
 443         "in0", "in1", "in2", "in3"
 444 };
 445 
 446 /*  By default CS bits are retrieved from channel A */
 447 static const char * const spdifrx_enum_cs_channel[] = {
 448         "A", "B"
 449 };
 450 
 451 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input,
 452                             STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT,
 453                             spdifrx_enum_input);
 454 
 455 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel,
 456                             STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT,
 457                             spdifrx_enum_cs_channel);
 458 
 459 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol,
 460                               struct snd_ctl_elem_info *uinfo)
 461 {
 462         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 463         uinfo->count = 1;
 464 
 465         return 0;
 466 }
 467 
 468 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol,
 469                                  struct snd_ctl_elem_info *uinfo)
 470 {
 471         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 472         uinfo->count = 1;
 473 
 474         return 0;
 475 }
 476 
 477 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx)
 478 {
 479         int ret = 0;
 480 
 481         memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB);
 482         memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB);
 483 
 484         ret = stm32_spdifrx_dma_ctrl_start(spdifrx);
 485         if (ret < 0)
 486                 return ret;
 487 
 488         ret = clk_prepare_enable(spdifrx->kclk);
 489         if (ret) {
 490                 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
 491                 return ret;
 492         }
 493 
 494         ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
 495                                  SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN);
 496         if (ret < 0)
 497                 goto end;
 498 
 499         ret = stm32_spdifrx_start_sync(spdifrx);
 500         if (ret < 0)
 501                 goto end;
 502 
 503         if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion,
 504                                                       msecs_to_jiffies(100))
 505                                                       <= 0) {
 506                 dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n");
 507                 ret = -EAGAIN;
 508         }
 509 
 510         stm32_spdifrx_stop(spdifrx);
 511         stm32_spdifrx_dma_ctrl_stop(spdifrx);
 512 
 513 end:
 514         clk_disable_unprepare(spdifrx->kclk);
 515 
 516         return ret;
 517 }
 518 
 519 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol,
 520                                      struct snd_ctl_elem_value *ucontrol)
 521 {
 522         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 523         struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
 524 
 525         stm32_spdifrx_get_ctrl_data(spdifrx);
 526 
 527         ucontrol->value.iec958.status[0] = spdifrx->cs[0];
 528         ucontrol->value.iec958.status[1] = spdifrx->cs[1];
 529         ucontrol->value.iec958.status[2] = spdifrx->cs[2];
 530         ucontrol->value.iec958.status[3] = spdifrx->cs[3];
 531         ucontrol->value.iec958.status[4] = spdifrx->cs[4];
 532 
 533         return 0;
 534 }
 535 
 536 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol,
 537                                      struct snd_ctl_elem_value *ucontrol)
 538 {
 539         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 540         struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
 541 
 542         stm32_spdifrx_get_ctrl_data(spdifrx);
 543 
 544         ucontrol->value.iec958.status[0] = spdifrx->ub[0];
 545         ucontrol->value.iec958.status[1] = spdifrx->ub[1];
 546         ucontrol->value.iec958.status[2] = spdifrx->ub[2];
 547         ucontrol->value.iec958.status[3] = spdifrx->ub[3];
 548         ucontrol->value.iec958.status[4] = spdifrx->ub[4];
 549 
 550         return 0;
 551 }
 552 
 553 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = {
 554         /* Channel status control */
 555         {
 556                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 557                 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
 558                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
 559                           SNDRV_CTL_ELEM_ACCESS_VOLATILE,
 560                 .info = stm32_spdifrx_info,
 561                 .get = stm32_spdifrx_capture_get,
 562         },
 563         /* User bits control */
 564         {
 565                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 566                 .name = "IEC958 User Bit Capture Default",
 567                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
 568                           SNDRV_CTL_ELEM_ACCESS_VOLATILE,
 569                 .info = stm32_spdifrx_ub_info,
 570                 .get = stm32_spdif_user_bits_get,
 571         },
 572 };
 573 
 574 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = {
 575         SOC_ENUM("SPDIFRX input", ctrl_enum_input),
 576         SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel),
 577 };
 578 
 579 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai)
 580 {
 581         int ret;
 582 
 583         ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls,
 584                                        ARRAY_SIZE(stm32_spdifrx_iec_ctrls));
 585         if (ret < 0)
 586                 return ret;
 587 
 588         return snd_soc_add_component_controls(cpu_dai->component,
 589                                               stm32_spdifrx_ctrls,
 590                                               ARRAY_SIZE(stm32_spdifrx_ctrls));
 591 }
 592 
 593 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai)
 594 {
 595         struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev);
 596 
 597         spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr +
 598                                    STM32_SPDIFRX_DR);
 599         spdifrx->dma_params.maxburst = 1;
 600 
 601         snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
 602 
 603         return stm32_spdifrx_dai_register_ctrls(cpu_dai);
 604 }
 605 
 606 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
 607 {
 608         switch (reg) {
 609         case STM32_SPDIFRX_CR:
 610         case STM32_SPDIFRX_IMR:
 611         case STM32_SPDIFRX_SR:
 612         case STM32_SPDIFRX_IFCR:
 613         case STM32_SPDIFRX_DR:
 614         case STM32_SPDIFRX_CSR:
 615         case STM32_SPDIFRX_DIR:
 616         case STM32_SPDIFRX_VERR:
 617         case STM32_SPDIFRX_IDR:
 618         case STM32_SPDIFRX_SIDR:
 619                 return true;
 620         default:
 621                 return false;
 622         }
 623 }
 624 
 625 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
 626 {
 627         switch (reg) {
 628         case STM32_SPDIFRX_DR:
 629         case STM32_SPDIFRX_CSR:
 630         case STM32_SPDIFRX_SR:
 631         case STM32_SPDIFRX_DIR:
 632                 return true;
 633         default:
 634                 return false;
 635         }
 636 }
 637 
 638 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
 639 {
 640         switch (reg) {
 641         case STM32_SPDIFRX_CR:
 642         case STM32_SPDIFRX_IMR:
 643         case STM32_SPDIFRX_IFCR:
 644                 return true;
 645         default:
 646                 return false;
 647         }
 648 }
 649 
 650 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
 651         .reg_bits = 32,
 652         .reg_stride = 4,
 653         .val_bits = 32,
 654         .max_register = STM32_SPDIFRX_SIDR,
 655         .readable_reg = stm32_spdifrx_readable_reg,
 656         .volatile_reg = stm32_spdifrx_volatile_reg,
 657         .writeable_reg = stm32_spdifrx_writeable_reg,
 658         .num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1,
 659         .fast_io = true,
 660         .cache_type = REGCACHE_FLAT,
 661 };
 662 
 663 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
 664 {
 665         struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid;
 666         struct platform_device *pdev = spdifrx->pdev;
 667         unsigned int cr, mask, sr, imr;
 668         unsigned int flags;
 669         int err = 0, err_xrun = 0;
 670 
 671         regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr);
 672         regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr);
 673 
 674         mask = imr & SPDIFRX_XIMR_MASK;
 675         /* SERR, TERR, FERR IRQs are generated if IFEIE is set */
 676         if (mask & SPDIFRX_IMR_IFEIE)
 677                 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2);
 678 
 679         flags = sr & mask;
 680         if (!flags) {
 681                 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n",
 682                         sr, imr);
 683                 return IRQ_NONE;
 684         }
 685 
 686         /* Clear IRQs */
 687         regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
 688                            SPDIFRX_XIFCR_MASK, flags);
 689 
 690         if (flags & SPDIFRX_SR_PERR) {
 691                 dev_dbg(&pdev->dev, "Parity error\n");
 692                 err_xrun = 1;
 693         }
 694 
 695         if (flags & SPDIFRX_SR_OVR) {
 696                 dev_dbg(&pdev->dev, "Overrun error\n");
 697                 err_xrun = 1;
 698         }
 699 
 700         if (flags & SPDIFRX_SR_SBD)
 701                 dev_dbg(&pdev->dev, "Synchronization block detected\n");
 702 
 703         if (flags & SPDIFRX_SR_SYNCD) {
 704                 dev_dbg(&pdev->dev, "Synchronization done\n");
 705 
 706                 /* Enable spdifrx */
 707                 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE);
 708                 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
 709                                    SPDIFRX_CR_SPDIFEN_MASK, cr);
 710         }
 711 
 712         if (flags & SPDIFRX_SR_FERR) {
 713                 dev_dbg(&pdev->dev, "Frame error\n");
 714                 err = 1;
 715         }
 716 
 717         if (flags & SPDIFRX_SR_SERR) {
 718                 dev_dbg(&pdev->dev, "Synchronization error\n");
 719                 err = 1;
 720         }
 721 
 722         if (flags & SPDIFRX_SR_TERR) {
 723                 dev_dbg(&pdev->dev, "Timeout error\n");
 724                 err = 1;
 725         }
 726 
 727         if (err) {
 728                 /* SPDIFRX in STATE_STOP. Disable SPDIFRX to clear errors */
 729                 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
 730                 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
 731                                    SPDIFRX_CR_SPDIFEN_MASK, cr);
 732 
 733                 spin_lock(&spdifrx->irq_lock);
 734                 if (spdifrx->substream)
 735                         snd_pcm_stop(spdifrx->substream,
 736                                      SNDRV_PCM_STATE_DISCONNECTED);
 737                 spin_unlock(&spdifrx->irq_lock);
 738 
 739                 return IRQ_HANDLED;
 740         }
 741 
 742         spin_lock(&spdifrx->irq_lock);
 743         if (err_xrun && spdifrx->substream)
 744                 snd_pcm_stop_xrun(spdifrx->substream);
 745         spin_unlock(&spdifrx->irq_lock);
 746 
 747         return IRQ_HANDLED;
 748 }
 749 
 750 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
 751                                  struct snd_soc_dai *cpu_dai)
 752 {
 753         struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
 754         unsigned long flags;
 755         int ret;
 756 
 757         spin_lock_irqsave(&spdifrx->irq_lock, flags);
 758         spdifrx->substream = substream;
 759         spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
 760 
 761         ret = clk_prepare_enable(spdifrx->kclk);
 762         if (ret)
 763                 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
 764 
 765         return ret;
 766 }
 767 
 768 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
 769                                    struct snd_pcm_hw_params *params,
 770                                    struct snd_soc_dai *cpu_dai)
 771 {
 772         struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
 773         int data_size = params_width(params);
 774         int fmt;
 775 
 776         switch (data_size) {
 777         case 16:
 778                 fmt = SPDIFRX_DRFMT_PACKED;
 779                 break;
 780         case 32:
 781                 fmt = SPDIFRX_DRFMT_LEFT;
 782                 break;
 783         default:
 784                 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
 785                 return -EINVAL;
 786         }
 787 
 788         /*
 789          * Set buswidth to 4 bytes for all data formats.
 790          * Packed format: transfer 2 x 2 bytes samples
 791          * Left format: transfer 1 x 3 bytes samples + 1 dummy byte
 792          */
 793         spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 794         snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
 795 
 796         return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
 797                                   SPDIFRX_CR_DRFMT_MASK,
 798                                   SPDIFRX_CR_DRFMTSET(fmt));
 799 }
 800 
 801 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
 802                                  struct snd_soc_dai *cpu_dai)
 803 {
 804         struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
 805         int ret = 0;
 806 
 807         switch (cmd) {
 808         case SNDRV_PCM_TRIGGER_START:
 809         case SNDRV_PCM_TRIGGER_RESUME:
 810         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 811                 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
 812                                    SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE);
 813 
 814                 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
 815                                    SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN);
 816 
 817                 ret = stm32_spdifrx_start_sync(spdifrx);
 818                 break;
 819         case SNDRV_PCM_TRIGGER_SUSPEND:
 820         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 821         case SNDRV_PCM_TRIGGER_STOP:
 822                 stm32_spdifrx_stop(spdifrx);
 823                 break;
 824         default:
 825                 return -EINVAL;
 826         }
 827 
 828         return ret;
 829 }
 830 
 831 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
 832                                    struct snd_soc_dai *cpu_dai)
 833 {
 834         struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
 835         unsigned long flags;
 836 
 837         spin_lock_irqsave(&spdifrx->irq_lock, flags);
 838         spdifrx->substream = NULL;
 839         spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
 840 
 841         clk_disable_unprepare(spdifrx->kclk);
 842 }
 843 
 844 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = {
 845         .startup        = stm32_spdifrx_startup,
 846         .hw_params      = stm32_spdifrx_hw_params,
 847         .trigger        = stm32_spdifrx_trigger,
 848         .shutdown       = stm32_spdifrx_shutdown,
 849 };
 850 
 851 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = {
 852         {
 853                 .probe = stm32_spdifrx_dai_probe,
 854                 .capture = {
 855                         .stream_name = "CPU-Capture",
 856                         .channels_min = 1,
 857                         .channels_max = 2,
 858                         .rates = SNDRV_PCM_RATE_8000_192000,
 859                         .formats = SNDRV_PCM_FMTBIT_S32_LE |
 860                                    SNDRV_PCM_FMTBIT_S16_LE,
 861                 },
 862                 .ops = &stm32_spdifrx_pcm_dai_ops,
 863         }
 864 };
 865 
 866 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = {
 867         .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
 868         .buffer_bytes_max = 8 * PAGE_SIZE,
 869         .period_bytes_min = 1024,
 870         .period_bytes_max = 4 * PAGE_SIZE,
 871         .periods_min = 2,
 872         .periods_max = 8,
 873 };
 874 
 875 static const struct snd_soc_component_driver stm32_spdifrx_component = {
 876         .name = "stm32-spdifrx",
 877 };
 878 
 879 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = {
 880         .pcm_hardware = &stm32_spdifrx_pcm_hw,
 881         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
 882 };
 883 
 884 static const struct of_device_id stm32_spdifrx_ids[] = {
 885         {
 886                 .compatible = "st,stm32h7-spdifrx",
 887                 .data = &stm32_h7_spdifrx_regmap_conf
 888         },
 889         {}
 890 };
 891 
 892 static int stm32_spdifrx_parse_of(struct platform_device *pdev,
 893                                   struct stm32_spdifrx_data *spdifrx)
 894 {
 895         struct device_node *np = pdev->dev.of_node;
 896         const struct of_device_id *of_id;
 897         struct resource *res;
 898 
 899         if (!np)
 900                 return -ENODEV;
 901 
 902         of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev);
 903         if (of_id)
 904                 spdifrx->regmap_conf =
 905                         (const struct regmap_config *)of_id->data;
 906         else
 907                 return -EINVAL;
 908 
 909         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 910         spdifrx->base = devm_ioremap_resource(&pdev->dev, res);
 911         if (IS_ERR(spdifrx->base))
 912                 return PTR_ERR(spdifrx->base);
 913 
 914         spdifrx->phys_addr = res->start;
 915 
 916         spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk");
 917         if (IS_ERR(spdifrx->kclk)) {
 918                 dev_err(&pdev->dev, "Could not get kclk\n");
 919                 return PTR_ERR(spdifrx->kclk);
 920         }
 921 
 922         spdifrx->irq = platform_get_irq(pdev, 0);
 923         if (spdifrx->irq < 0)
 924                 return spdifrx->irq;
 925 
 926         return 0;
 927 }
 928 
 929 static int stm32_spdifrx_probe(struct platform_device *pdev)
 930 {
 931         struct stm32_spdifrx_data *spdifrx;
 932         struct reset_control *rst;
 933         const struct snd_dmaengine_pcm_config *pcm_config = NULL;
 934         u32 ver, idr;
 935         int ret;
 936 
 937         spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
 938         if (!spdifrx)
 939                 return -ENOMEM;
 940 
 941         spdifrx->pdev = pdev;
 942         init_completion(&spdifrx->cs_completion);
 943         spin_lock_init(&spdifrx->lock);
 944         spin_lock_init(&spdifrx->irq_lock);
 945 
 946         platform_set_drvdata(pdev, spdifrx);
 947 
 948         ret = stm32_spdifrx_parse_of(pdev, spdifrx);
 949         if (ret)
 950                 return ret;
 951 
 952         spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk",
 953                                                     spdifrx->base,
 954                                                     spdifrx->regmap_conf);
 955         if (IS_ERR(spdifrx->regmap)) {
 956                 dev_err(&pdev->dev, "Regmap init failed\n");
 957                 return PTR_ERR(spdifrx->regmap);
 958         }
 959 
 960         ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0,
 961                                dev_name(&pdev->dev), spdifrx);
 962         if (ret) {
 963                 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
 964                 return ret;
 965         }
 966 
 967         rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 968         if (!IS_ERR(rst)) {
 969                 reset_control_assert(rst);
 970                 udelay(2);
 971                 reset_control_deassert(rst);
 972         }
 973 
 974         ret = devm_snd_soc_register_component(&pdev->dev,
 975                                               &stm32_spdifrx_component,
 976                                               stm32_spdifrx_dai,
 977                                               ARRAY_SIZE(stm32_spdifrx_dai));
 978         if (ret)
 979                 return ret;
 980 
 981         ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx);
 982         if (ret)
 983                 goto error;
 984 
 985         pcm_config = &stm32_spdifrx_pcm_config;
 986         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0);
 987         if (ret) {
 988                 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret);
 989                 goto error;
 990         }
 991 
 992         ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr);
 993         if (ret)
 994                 goto error;
 995 
 996         if (idr == SPDIFRX_IPIDR_NUMBER) {
 997                 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver);
 998                 if (ret)
 999                         goto error;
1000 
1001                 dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n",
1002                         FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver),
1003                         FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver));
1004         }
1005 
1006         return ret;
1007 
1008 error:
1009         if (!IS_ERR(spdifrx->ctrl_chan))
1010                 dma_release_channel(spdifrx->ctrl_chan);
1011         if (spdifrx->dmab)
1012                 snd_dma_free_pages(spdifrx->dmab);
1013 
1014         return ret;
1015 }
1016 
1017 static int stm32_spdifrx_remove(struct platform_device *pdev)
1018 {
1019         struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev);
1020 
1021         if (spdifrx->ctrl_chan)
1022                 dma_release_channel(spdifrx->ctrl_chan);
1023 
1024         if (spdifrx->dmab)
1025                 snd_dma_free_pages(spdifrx->dmab);
1026 
1027         return 0;
1028 }
1029 
1030 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids);
1031 
1032 #ifdef CONFIG_PM_SLEEP
1033 static int stm32_spdifrx_suspend(struct device *dev)
1034 {
1035         struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
1036 
1037         regcache_cache_only(spdifrx->regmap, true);
1038         regcache_mark_dirty(spdifrx->regmap);
1039 
1040         return 0;
1041 }
1042 
1043 static int stm32_spdifrx_resume(struct device *dev)
1044 {
1045         struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
1046 
1047         regcache_cache_only(spdifrx->regmap, false);
1048 
1049         return regcache_sync(spdifrx->regmap);
1050 }
1051 #endif /* CONFIG_PM_SLEEP */
1052 
1053 static const struct dev_pm_ops stm32_spdifrx_pm_ops = {
1054         SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume)
1055 };
1056 
1057 static struct platform_driver stm32_spdifrx_driver = {
1058         .driver = {
1059                 .name = "st,stm32-spdifrx",
1060                 .of_match_table = stm32_spdifrx_ids,
1061                 .pm = &stm32_spdifrx_pm_ops,
1062         },
1063         .probe = stm32_spdifrx_probe,
1064         .remove = stm32_spdifrx_remove,
1065 };
1066 
1067 module_platform_driver(stm32_spdifrx_driver);
1068 
1069 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface");
1070 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1071 MODULE_ALIAS("platform:stm32-spdifrx");
1072 MODULE_LICENSE("GPL v2");

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