root/sound/soc/intel/skylake/cnl-sst-dsp.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Cannonlake SST DSP Support
   4  *
   5  * Copyright (C) 2016-17, Intel Corporation.
   6  */
   7 
   8 #ifndef __CNL_SST_DSP_H__
   9 #define __CNL_SST_DSP_H__
  10 
  11 struct sst_dsp;
  12 struct sst_dsp_device;
  13 struct sst_generic_ipc;
  14 
  15 /* Intel HD Audio General DSP Registers */
  16 #define CNL_ADSP_GEN_BASE               0x0
  17 #define CNL_ADSP_REG_ADSPCS             (CNL_ADSP_GEN_BASE + 0x04)
  18 #define CNL_ADSP_REG_ADSPIC             (CNL_ADSP_GEN_BASE + 0x08)
  19 #define CNL_ADSP_REG_ADSPIS             (CNL_ADSP_GEN_BASE + 0x0c)
  20 
  21 /* Intel HD Audio Inter-Processor Communication Registers */
  22 #define CNL_ADSP_IPC_BASE               0xc0
  23 #define CNL_ADSP_REG_HIPCTDR            (CNL_ADSP_IPC_BASE + 0x00)
  24 #define CNL_ADSP_REG_HIPCTDA            (CNL_ADSP_IPC_BASE + 0x04)
  25 #define CNL_ADSP_REG_HIPCTDD            (CNL_ADSP_IPC_BASE + 0x08)
  26 #define CNL_ADSP_REG_HIPCIDR            (CNL_ADSP_IPC_BASE + 0x10)
  27 #define CNL_ADSP_REG_HIPCIDA            (CNL_ADSP_IPC_BASE + 0x14)
  28 #define CNL_ADSP_REG_HIPCIDD            (CNL_ADSP_IPC_BASE + 0x18)
  29 #define CNL_ADSP_REG_HIPCCTL            (CNL_ADSP_IPC_BASE + 0x28)
  30 
  31 /* HIPCTDR */
  32 #define CNL_ADSP_REG_HIPCTDR_BUSY       BIT(31)
  33 
  34 /* HIPCTDA */
  35 #define CNL_ADSP_REG_HIPCTDA_DONE       BIT(31)
  36 
  37 /* HIPCIDR */
  38 #define CNL_ADSP_REG_HIPCIDR_BUSY       BIT(31)
  39 
  40 /* HIPCIDA */
  41 #define CNL_ADSP_REG_HIPCIDA_DONE       BIT(31)
  42 
  43 /* CNL HIPCCTL */
  44 #define CNL_ADSP_REG_HIPCCTL_DONE       BIT(1)
  45 #define CNL_ADSP_REG_HIPCCTL_BUSY       BIT(0)
  46 
  47 /* CNL HIPCT */
  48 #define CNL_ADSP_REG_HIPCT_BUSY         BIT(31)
  49 
  50 /* Intel HD Audio SRAM Window 1 */
  51 #define CNL_ADSP_SRAM1_BASE             0xa0000
  52 
  53 #define CNL_ADSP_MMIO_LEN               0x10000
  54 
  55 #define CNL_ADSP_W0_STAT_SZ             0x1000
  56 
  57 #define CNL_ADSP_W0_UP_SZ               0x1000
  58 
  59 #define CNL_ADSP_W1_SZ                  0x1000
  60 
  61 #define CNL_FW_STS_MASK                 0xf
  62 
  63 #define CNL_ADSPIC_IPC                  0x1
  64 #define CNL_ADSPIS_IPC                  0x1
  65 
  66 #define CNL_DSP_CORES           4
  67 #define CNL_DSP_CORES_MASK      ((1 << CNL_DSP_CORES) - 1)
  68 
  69 /* core reset - asserted high */
  70 #define CNL_ADSPCS_CRST_SHIFT   0
  71 #define CNL_ADSPCS_CRST(x)      (x << CNL_ADSPCS_CRST_SHIFT)
  72 
  73 /* core run/stall - when set to 1 core is stalled */
  74 #define CNL_ADSPCS_CSTALL_SHIFT 8
  75 #define CNL_ADSPCS_CSTALL(x)    (x << CNL_ADSPCS_CSTALL_SHIFT)
  76 
  77 /* set power active - when set to 1 turn core on */
  78 #define CNL_ADSPCS_SPA_SHIFT    16
  79 #define CNL_ADSPCS_SPA(x)       (x << CNL_ADSPCS_SPA_SHIFT)
  80 
  81 /* current power active - power status of cores, set by hardware */
  82 #define CNL_ADSPCS_CPA_SHIFT    24
  83 #define CNL_ADSPCS_CPA(x)       (x << CNL_ADSPCS_CPA_SHIFT)
  84 
  85 int cnl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core);
  86 int cnl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core);
  87 irqreturn_t cnl_dsp_sst_interrupt(int irq, void *dev_id);
  88 void cnl_dsp_free(struct sst_dsp *dsp);
  89 
  90 void cnl_ipc_int_enable(struct sst_dsp *ctx);
  91 void cnl_ipc_int_disable(struct sst_dsp *ctx);
  92 void cnl_ipc_op_int_enable(struct sst_dsp *ctx);
  93 void cnl_ipc_op_int_disable(struct sst_dsp *ctx);
  94 bool cnl_ipc_int_status(struct sst_dsp *ctx);
  95 void cnl_ipc_free(struct sst_generic_ipc *ipc);
  96 
  97 int cnl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
  98                      const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
  99                      struct skl_dev **dsp);
 100 int cnl_sst_init_fw(struct device *dev, struct skl_dev *skl);
 101 void cnl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl);
 102 
 103 #endif /*__CNL_SST_DSP_H__*/