root/sound/soc/mediatek/mt6797/mt6797-reg.h

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INCLUDED FROM


   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * mt6797-reg.h  --  Mediatek 6797 audio driver reg definition
   4  *
   5  * Copyright (c) 2018 MediaTek Inc.
   6  * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
   7  */
   8 
   9 #ifndef _MT6797_REG_H_
  10 #define _MT6797_REG_H_
  11 
  12 #define AUDIO_TOP_CON0            0x0000
  13 #define AUDIO_TOP_CON1            0x0004
  14 #define AUDIO_TOP_CON3            0x000c
  15 #define AFE_DAC_CON0              0x0010
  16 #define AFE_DAC_CON1              0x0014
  17 #define AFE_I2S_CON               0x0018
  18 #define AFE_DAIBT_CON0            0x001c
  19 #define AFE_CONN0                 0x0020
  20 #define AFE_CONN1                 0x0024
  21 #define AFE_CONN2                 0x0028
  22 #define AFE_CONN3                 0x002c
  23 #define AFE_CONN4                 0x0030
  24 #define AFE_I2S_CON1              0x0034
  25 #define AFE_I2S_CON2              0x0038
  26 #define AFE_MRGIF_CON             0x003c
  27 #define AFE_DL1_BASE              0x0040
  28 #define AFE_DL1_CUR               0x0044
  29 #define AFE_DL1_END               0x0048
  30 #define AFE_I2S_CON3              0x004c
  31 #define AFE_DL2_BASE              0x0050
  32 #define AFE_DL2_CUR               0x0054
  33 #define AFE_DL2_END               0x0058
  34 #define AFE_CONN5                 0x005c
  35 #define AFE_CONN_24BIT            0x006c
  36 #define AFE_AWB_BASE              0x0070
  37 #define AFE_AWB_END               0x0078
  38 #define AFE_AWB_CUR               0x007c
  39 #define AFE_VUL_BASE              0x0080
  40 #define AFE_VUL_END               0x0088
  41 #define AFE_VUL_CUR               0x008c
  42 #define AFE_DAI_BASE              0x0090
  43 #define AFE_DAI_END               0x0098
  44 #define AFE_DAI_CUR               0x009c
  45 #define AFE_CONN6                 0x00bc
  46 #define AFE_MEMIF_MSB             0x00cc
  47 #define AFE_MEMIF_MON0            0x00d0
  48 #define AFE_MEMIF_MON1            0x00d4
  49 #define AFE_MEMIF_MON2            0x00d8
  50 #define AFE_MEMIF_MON4            0x00e0
  51 #define AFE_ADDA_DL_SRC2_CON0     0x0108
  52 #define AFE_ADDA_DL_SRC2_CON1     0x010c
  53 #define AFE_ADDA_UL_SRC_CON0      0x0114
  54 #define AFE_ADDA_UL_SRC_CON1      0x0118
  55 #define AFE_ADDA_TOP_CON0         0x0120
  56 #define AFE_ADDA_UL_DL_CON0       0x0124
  57 #define AFE_ADDA_SRC_DEBUG        0x012c
  58 #define AFE_ADDA_SRC_DEBUG_MON0   0x0130
  59 #define AFE_ADDA_SRC_DEBUG_MON1   0x0134
  60 #define AFE_ADDA_NEWIF_CFG0       0x0138
  61 #define AFE_ADDA_NEWIF_CFG1       0x013c
  62 #define AFE_ADDA_NEWIF_CFG2       0x0140
  63 #define AFE_DMA_CTL               0x0150
  64 #define AFE_DMA_MON0              0x0154
  65 #define AFE_DMA_MON1              0x0158
  66 #define AFE_SIDETONE_DEBUG        0x01d0
  67 #define AFE_SIDETONE_MON          0x01d4
  68 #define AFE_SIDETONE_CON0         0x01e0
  69 #define AFE_SIDETONE_COEFF        0x01e4
  70 #define AFE_SIDETONE_CON1         0x01e8
  71 #define AFE_SIDETONE_GAIN         0x01ec
  72 #define AFE_SGEN_CON0             0x01f0
  73 #define AFE_SINEGEN_CON_TDM       0x01fc
  74 #define AFE_TOP_CON0              0x0200
  75 #define AFE_ADDA_PREDIS_CON0      0x0260
  76 #define AFE_ADDA_PREDIS_CON1      0x0264
  77 #define AFE_MRGIF_MON0            0x0270
  78 #define AFE_MRGIF_MON1            0x0274
  79 #define AFE_MRGIF_MON2            0x0278
  80 #define AFE_I2S_MON               0x027c
  81 #define AFE_MOD_DAI_BASE          0x0330
  82 #define AFE_MOD_DAI_END           0x0338
  83 #define AFE_MOD_DAI_CUR           0x033c
  84 #define AFE_VUL_D2_BASE           0x0350
  85 #define AFE_VUL_D2_END            0x0358
  86 #define AFE_VUL_D2_CUR            0x035c
  87 #define AFE_DL3_BASE              0x0360
  88 #define AFE_DL3_CUR               0x0364
  89 #define AFE_DL3_END               0x0368
  90 #define AFE_HDMI_OUT_CON0         0x0370
  91 #define AFE_HDMI_BASE             0x0374
  92 #define AFE_HDMI_CUR              0x0378
  93 #define AFE_HDMI_END              0x037c
  94 #define AFE_HDMI_CONN0            0x0390
  95 #define AFE_IRQ3_MCU_CNT_MON      0x0398
  96 #define AFE_IRQ4_MCU_CNT_MON      0x039c
  97 #define AFE_IRQ_MCU_CON           0x03a0
  98 #define AFE_IRQ_MCU_STATUS        0x03a4
  99 #define AFE_IRQ_MCU_CLR           0x03a8
 100 #define AFE_IRQ_MCU_CNT1          0x03ac
 101 #define AFE_IRQ_MCU_CNT2          0x03b0
 102 #define AFE_IRQ_MCU_EN            0x03b4
 103 #define AFE_IRQ_MCU_MON2          0x03b8
 104 #define AFE_IRQ_MCU_CNT5          0x03bc
 105 #define AFE_IRQ1_MCU_CNT_MON      0x03c0
 106 #define AFE_IRQ2_MCU_CNT_MON      0x03c4
 107 #define AFE_IRQ1_MCU_EN_CNT_MON   0x03c8
 108 #define AFE_IRQ5_MCU_CNT_MON      0x03cc
 109 #define AFE_MEMIF_MINLEN          0x03d0
 110 #define AFE_MEMIF_MAXLEN          0x03d4
 111 #define AFE_MEMIF_PBUF_SIZE       0x03d8
 112 #define AFE_IRQ_MCU_CNT7          0x03dc
 113 #define AFE_IRQ7_MCU_CNT_MON      0x03e0
 114 #define AFE_IRQ_MCU_CNT3          0x03e4
 115 #define AFE_IRQ_MCU_CNT4          0x03e8
 116 #define AFE_APLL1_TUNER_CFG       0x03f0
 117 #define AFE_APLL2_TUNER_CFG       0x03f4
 118 #define AFE_MEMIF_HD_MODE         0x03f8
 119 #define AFE_MEMIF_HDALIGN         0x03fc
 120 #define AFE_GAIN1_CON0            0x0410
 121 #define AFE_GAIN1_CON1            0x0414
 122 #define AFE_GAIN1_CON2            0x0418
 123 #define AFE_GAIN1_CON3            0x041c
 124 #define AFE_CONN7                 0x0420
 125 #define AFE_GAIN1_CUR             0x0424
 126 #define AFE_GAIN2_CON0            0x0428
 127 #define AFE_GAIN2_CON1            0x042c
 128 #define AFE_GAIN2_CON2            0x0430
 129 #define AFE_GAIN2_CON3            0x0434
 130 #define AFE_CONN8                 0x0438
 131 #define AFE_GAIN2_CUR             0x043c
 132 #define AFE_CONN9                 0x0440
 133 #define AFE_CONN10                0x0444
 134 #define AFE_CONN11                0x0448
 135 #define AFE_CONN12                0x044c
 136 #define AFE_CONN13                0x0450
 137 #define AFE_CONN14                0x0454
 138 #define AFE_CONN15                0x0458
 139 #define AFE_CONN16                0x045c
 140 #define AFE_CONN17                0x0460
 141 #define AFE_CONN18                0x0464
 142 #define AFE_CONN19                0x0468
 143 #define AFE_CONN20                0x046c
 144 #define AFE_CONN21                0x0470
 145 #define AFE_CONN22                0x0474
 146 #define AFE_CONN23                0x0478
 147 #define AFE_CONN24                0x047c
 148 #define AFE_CONN_RS               0x0494
 149 #define AFE_CONN_DI               0x0498
 150 #define AFE_CONN25                0x04b0
 151 #define AFE_CONN26                0x04b4
 152 #define AFE_CONN27                0x04b8
 153 #define AFE_CONN28                0x04bc
 154 #define AFE_CONN29                0x04c0
 155 #define AFE_SRAM_DELSEL_CON0      0x04f0
 156 #define AFE_SRAM_DELSEL_CON1      0x04f4
 157 #define AFE_ASRC_CON0             0x0500
 158 #define AFE_ASRC_CON1             0x0504
 159 #define AFE_ASRC_CON2             0x0508
 160 #define AFE_ASRC_CON3             0x050c
 161 #define AFE_ASRC_CON4             0x0510
 162 #define AFE_ASRC_CON5             0x0514
 163 #define AFE_ASRC_CON6             0x0518
 164 #define AFE_ASRC_CON7             0x051c
 165 #define AFE_ASRC_CON8             0x0520
 166 #define AFE_ASRC_CON9             0x0524
 167 #define AFE_ASRC_CON10            0x0528
 168 #define AFE_ASRC_CON11            0x052c
 169 #define PCM_INTF_CON1             0x0530
 170 #define PCM_INTF_CON2             0x0538
 171 #define PCM2_INTF_CON             0x053c
 172 #define AFE_TDM_CON1              0x0548
 173 #define AFE_TDM_CON2              0x054c
 174 #define AFE_ASRC_CON13            0x0550
 175 #define AFE_ASRC_CON14            0x0554
 176 #define AFE_ASRC_CON15            0x0558
 177 #define AFE_ASRC_CON16            0x055c
 178 #define AFE_ASRC_CON17            0x0560
 179 #define AFE_ASRC_CON18            0x0564
 180 #define AFE_ASRC_CON19            0x0568
 181 #define AFE_ASRC_CON20            0x056c
 182 #define AFE_ASRC_CON21            0x0570
 183 #define CLK_AUDDIV_0              0x05a0
 184 #define CLK_AUDDIV_1              0x05a4
 185 #define CLK_AUDDIV_2              0x05a8
 186 #define CLK_AUDDIV_3              0x05ac
 187 #define AUDIO_TOP_DBG_CON         0x05c8
 188 #define AUDIO_TOP_DBG_MON0        0x05cc
 189 #define AUDIO_TOP_DBG_MON1        0x05d0
 190 #define AUDIO_TOP_DBG_MON2        0x05d4
 191 #define AFE_ADDA2_TOP_CON0        0x0600
 192 #define AFE_ASRC4_CON0            0x06c0
 193 #define AFE_ASRC4_CON1            0x06c4
 194 #define AFE_ASRC4_CON2            0x06c8
 195 #define AFE_ASRC4_CON3            0x06cc
 196 #define AFE_ASRC4_CON4            0x06d0
 197 #define AFE_ASRC4_CON5            0x06d4
 198 #define AFE_ASRC4_CON6            0x06d8
 199 #define AFE_ASRC4_CON7            0x06dc
 200 #define AFE_ASRC4_CON8            0x06e0
 201 #define AFE_ASRC4_CON9            0x06e4
 202 #define AFE_ASRC4_CON10           0x06e8
 203 #define AFE_ASRC4_CON11           0x06ec
 204 #define AFE_ASRC4_CON12           0x06f0
 205 #define AFE_ASRC4_CON13           0x06f4
 206 #define AFE_ASRC4_CON14           0x06f8
 207 #define AFE_ASRC2_CON0            0x0700
 208 #define AFE_ASRC2_CON1            0x0704
 209 #define AFE_ASRC2_CON2            0x0708
 210 #define AFE_ASRC2_CON3            0x070c
 211 #define AFE_ASRC2_CON4            0x0710
 212 #define AFE_ASRC2_CON5            0x0714
 213 #define AFE_ASRC2_CON6            0x0718
 214 #define AFE_ASRC2_CON7            0x071c
 215 #define AFE_ASRC2_CON8            0x0720
 216 #define AFE_ASRC2_CON9            0x0724
 217 #define AFE_ASRC2_CON10           0x0728
 218 #define AFE_ASRC2_CON11           0x072c
 219 #define AFE_ASRC2_CON12           0x0730
 220 #define AFE_ASRC2_CON13           0x0734
 221 #define AFE_ASRC2_CON14           0x0738
 222 #define AFE_ASRC3_CON0            0x0740
 223 #define AFE_ASRC3_CON1            0x0744
 224 #define AFE_ASRC3_CON2            0x0748
 225 #define AFE_ASRC3_CON3            0x074c
 226 #define AFE_ASRC3_CON4            0x0750
 227 #define AFE_ASRC3_CON5            0x0754
 228 #define AFE_ASRC3_CON6            0x0758
 229 #define AFE_ASRC3_CON7            0x075c
 230 #define AFE_ASRC3_CON8            0x0760
 231 #define AFE_ASRC3_CON9            0x0764
 232 #define AFE_ASRC3_CON10           0x0768
 233 #define AFE_ASRC3_CON11           0x076c
 234 #define AFE_ASRC3_CON12           0x0770
 235 #define AFE_ASRC3_CON13           0x0774
 236 #define AFE_ASRC3_CON14           0x0778
 237 #define AFE_GENERAL_REG0          0x0800
 238 #define AFE_GENERAL_REG1          0x0804
 239 #define AFE_GENERAL_REG2          0x0808
 240 #define AFE_GENERAL_REG3          0x080c
 241 #define AFE_GENERAL_REG4          0x0810
 242 #define AFE_GENERAL_REG5          0x0814
 243 #define AFE_GENERAL_REG6          0x0818
 244 #define AFE_GENERAL_REG7          0x081c
 245 #define AFE_GENERAL_REG8          0x0820
 246 #define AFE_GENERAL_REG9          0x0824
 247 #define AFE_GENERAL_REG10         0x0828
 248 #define AFE_GENERAL_REG11         0x082c
 249 #define AFE_GENERAL_REG12         0x0830
 250 #define AFE_GENERAL_REG13         0x0834
 251 #define AFE_GENERAL_REG14         0x0838
 252 #define AFE_GENERAL_REG15         0x083c
 253 #define AFE_CBIP_CFG0             0x0840
 254 #define AFE_CBIP_MON0             0x0844
 255 #define AFE_CBIP_SLV_MUX_MON0     0x0848
 256 #define AFE_CBIP_SLV_DECODER_MON0 0x084c
 257 
 258 #define AFE_MAX_REGISTER AFE_CBIP_SLV_DECODER_MON0
 259 #define AFE_IRQ_STATUS_BITS 0x5f
 260 
 261 /* AUDIO_TOP_CON0 */
 262 #define AHB_IDLE_EN_INT_SFT                                 30
 263 #define AHB_IDLE_EN_INT_MASK                                0x1
 264 #define AHB_IDLE_EN_INT_MASK_SFT                            (0x1 << 30)
 265 #define AHB_IDLE_EN_EXT_SFT                                 29
 266 #define AHB_IDLE_EN_EXT_MASK                                0x1
 267 #define AHB_IDLE_EN_EXT_MASK_SFT                            (0x1 << 29)
 268 #define PDN_TML_SFT                                         27
 269 #define PDN_TML_MASK                                        0x1
 270 #define PDN_TML_MASK_SFT                                    (0x1 << 27)
 271 #define PDN_DAC_PREDIS_SFT                                  26
 272 #define PDN_DAC_PREDIS_MASK                                 0x1
 273 #define PDN_DAC_PREDIS_MASK_SFT                             (0x1 << 26)
 274 #define PDN_DAC_SFT                                         25
 275 #define PDN_DAC_MASK                                        0x1
 276 #define PDN_DAC_MASK_SFT                                    (0x1 << 25)
 277 #define PDN_ADC_SFT                                         24
 278 #define PDN_ADC_MASK                                        0x1
 279 #define PDN_ADC_MASK_SFT                                    (0x1 << 24)
 280 #define PDN_TDM_CK_SFT                                      20
 281 #define PDN_TDM_CK_MASK                                     0x1
 282 #define PDN_TDM_CK_MASK_SFT                                 (0x1 << 20)
 283 #define PDN_APLL_TUNER_SFT                                  19
 284 #define PDN_APLL_TUNER_MASK                                 0x1
 285 #define PDN_APLL_TUNER_MASK_SFT                             (0x1 << 19)
 286 #define PDN_APLL2_TUNER_SFT                                 18
 287 #define PDN_APLL2_TUNER_MASK                                0x1
 288 #define PDN_APLL2_TUNER_MASK_SFT                            (0x1 << 18)
 289 #define APB3_SEL_SFT                                        14
 290 #define APB3_SEL_MASK                                       0x1
 291 #define APB3_SEL_MASK_SFT                                   (0x1 << 14)
 292 #define APB_R2T_SFT                                         13
 293 #define APB_R2T_MASK                                        0x1
 294 #define APB_R2T_MASK_SFT                                    (0x1 << 13)
 295 #define APB_W2T_SFT                                         12
 296 #define APB_W2T_MASK                                        0x1
 297 #define APB_W2T_MASK_SFT                                    (0x1 << 12)
 298 #define PDN_24M_SFT                                         9
 299 #define PDN_24M_MASK                                        0x1
 300 #define PDN_24M_MASK_SFT                                    (0x1 << 9)
 301 #define PDN_22M_SFT                                         8
 302 #define PDN_22M_MASK                                        0x1
 303 #define PDN_22M_MASK_SFT                                    (0x1 << 8)
 304 #define PDN_ADDA4_ADC_SFT                                   7
 305 #define PDN_ADDA4_ADC_MASK                                  0x1
 306 #define PDN_ADDA4_ADC_MASK_SFT                              (0x1 << 7)
 307 #define PDN_I2S_SFT                                         6
 308 #define PDN_I2S_MASK                                        0x1
 309 #define PDN_I2S_MASK_SFT                                    (0x1 << 6)
 310 #define PDN_AFE_SFT                                         2
 311 #define PDN_AFE_MASK                                        0x1
 312 #define PDN_AFE_MASK_SFT                                    (0x1 << 2)
 313 
 314 /* AUDIO_TOP_CON1 */
 315 #define PDN_ADC_HIRES_TML_SFT                               17
 316 #define PDN_ADC_HIRES_TML_MASK                              0x1
 317 #define PDN_ADC_HIRES_TML_MASK_SFT                          (0x1 << 17)
 318 #define PDN_ADC_HIRES_SFT                                   16
 319 #define PDN_ADC_HIRES_MASK                                  0x1
 320 #define PDN_ADC_HIRES_MASK_SFT                              (0x1 << 16)
 321 #define I2S4_BCLK_SW_CG_SFT                                 7
 322 #define I2S4_BCLK_SW_CG_MASK                                0x1
 323 #define I2S4_BCLK_SW_CG_MASK_SFT                            (0x1 << 7)
 324 #define I2S3_BCLK_SW_CG_SFT                                 6
 325 #define I2S3_BCLK_SW_CG_MASK                                0x1
 326 #define I2S3_BCLK_SW_CG_MASK_SFT                            (0x1 << 6)
 327 #define I2S2_BCLK_SW_CG_SFT                                 5
 328 #define I2S2_BCLK_SW_CG_MASK                                0x1
 329 #define I2S2_BCLK_SW_CG_MASK_SFT                            (0x1 << 5)
 330 #define I2S1_BCLK_SW_CG_SFT                                 4
 331 #define I2S1_BCLK_SW_CG_MASK                                0x1
 332 #define I2S1_BCLK_SW_CG_MASK_SFT                            (0x1 << 4)
 333 #define I2S_SOFT_RST2_SFT                                   2
 334 #define I2S_SOFT_RST2_MASK                                  0x1
 335 #define I2S_SOFT_RST2_MASK_SFT                              (0x1 << 2)
 336 #define I2S_SOFT_RST_SFT                                    1
 337 #define I2S_SOFT_RST_MASK                                   0x1
 338 #define I2S_SOFT_RST_MASK_SFT                               (0x1 << 1)
 339 
 340 /* AFE_DAC_CON0 */
 341 #define AFE_AWB_RETM_SFT                                    31
 342 #define AFE_AWB_RETM_MASK                                   0x1
 343 #define AFE_AWB_RETM_MASK_SFT                               (0x1 << 31)
 344 #define AFE_DL1_DATA2_RETM_SFT                              30
 345 #define AFE_DL1_DATA2_RETM_MASK                             0x1
 346 #define AFE_DL1_DATA2_RETM_MASK_SFT                         (0x1 << 30)
 347 #define AFE_DL2_RETM_SFT                                    29
 348 #define AFE_DL2_RETM_MASK                                   0x1
 349 #define AFE_DL2_RETM_MASK_SFT                               (0x1 << 29)
 350 #define AFE_DL1_RETM_SFT                                    28
 351 #define AFE_DL1_RETM_MASK                                   0x1
 352 #define AFE_DL1_RETM_MASK_SFT                               (0x1 << 28)
 353 #define AFE_ON_RETM_SFT                                     27
 354 #define AFE_ON_RETM_MASK                                    0x1
 355 #define AFE_ON_RETM_MASK_SFT                                (0x1 << 27)
 356 #define MOD_DAI_DUP_WR_SFT                                  26
 357 #define MOD_DAI_DUP_WR_MASK                                 0x1
 358 #define MOD_DAI_DUP_WR_MASK_SFT                             (0x1 << 26)
 359 #define DAI_MODE_SFT                                        24
 360 #define DAI_MODE_MASK                                       0x3
 361 #define DAI_MODE_MASK_SFT                                   (0x3 << 24)
 362 #define VUL_DATA2_MODE_SFT                                  20
 363 #define VUL_DATA2_MODE_MASK                                 0xf
 364 #define VUL_DATA2_MODE_MASK_SFT                             (0xf << 20)
 365 #define DL1_DATA2_MODE_SFT                                  16
 366 #define DL1_DATA2_MODE_MASK                                 0xf
 367 #define DL1_DATA2_MODE_MASK_SFT                             (0xf << 16)
 368 #define DL3_MODE_SFT                                        12
 369 #define DL3_MODE_MASK                                       0xf
 370 #define DL3_MODE_MASK_SFT                                   (0xf << 12)
 371 #define VUL_DATA2_R_MONO_SFT                                11
 372 #define VUL_DATA2_R_MONO_MASK                               0x1
 373 #define VUL_DATA2_R_MONO_MASK_SFT                           (0x1 << 11)
 374 #define VUL_DATA2_DATA_SFT                                  10
 375 #define VUL_DATA2_DATA_MASK                                 0x1
 376 #define VUL_DATA2_DATA_MASK_SFT                             (0x1 << 10)
 377 #define VUL_DATA2_ON_SFT                                    9
 378 #define VUL_DATA2_ON_MASK                                   0x1
 379 #define VUL_DATA2_ON_MASK_SFT                               (0x1 << 9)
 380 #define DL1_DATA2_ON_SFT                                    8
 381 #define DL1_DATA2_ON_MASK                                   0x1
 382 #define DL1_DATA2_ON_MASK_SFT                               (0x1 << 8)
 383 #define MOD_DAI_ON_SFT                                      7
 384 #define MOD_DAI_ON_MASK                                     0x1
 385 #define MOD_DAI_ON_MASK_SFT                                 (0x1 << 7)
 386 #define AWB_ON_SFT                                          6
 387 #define AWB_ON_MASK                                         0x1
 388 #define AWB_ON_MASK_SFT                                     (0x1 << 6)
 389 #define DL3_ON_SFT                                          5
 390 #define DL3_ON_MASK                                         0x1
 391 #define DL3_ON_MASK_SFT                                     (0x1 << 5)
 392 #define DAI_ON_SFT                                          4
 393 #define DAI_ON_MASK                                         0x1
 394 #define DAI_ON_MASK_SFT                                     (0x1 << 4)
 395 #define VUL_ON_SFT                                          3
 396 #define VUL_ON_MASK                                         0x1
 397 #define VUL_ON_MASK_SFT                                     (0x1 << 3)
 398 #define DL2_ON_SFT                                          2
 399 #define DL2_ON_MASK                                         0x1
 400 #define DL2_ON_MASK_SFT                                     (0x1 << 2)
 401 #define DL1_ON_SFT                                          1
 402 #define DL1_ON_MASK                                         0x1
 403 #define DL1_ON_MASK_SFT                                     (0x1 << 1)
 404 #define AFE_ON_SFT                                          0
 405 #define AFE_ON_MASK                                         0x1
 406 #define AFE_ON_MASK_SFT                                     (0x1 << 0)
 407 
 408 /* AFE_DAC_CON1 */
 409 #define MOD_DAI_MODE_SFT                                    30
 410 #define MOD_DAI_MODE_MASK                                   0x3
 411 #define MOD_DAI_MODE_MASK_SFT                               (0x3 << 30)
 412 #define DAI_DUP_WR_SFT                                      29
 413 #define DAI_DUP_WR_MASK                                     0x1
 414 #define DAI_DUP_WR_MASK_SFT                                 (0x1 << 29)
 415 #define VUL_R_MONO_SFT                                      28
 416 #define VUL_R_MONO_MASK                                     0x1
 417 #define VUL_R_MONO_MASK_SFT                                 (0x1 << 28)
 418 #define VUL_DATA_SFT                                        27
 419 #define VUL_DATA_MASK                                       0x1
 420 #define VUL_DATA_MASK_SFT                                   (0x1 << 27)
 421 #define AXI_2X1_CG_DISABLE_SFT                              26
 422 #define AXI_2X1_CG_DISABLE_MASK                             0x1
 423 #define AXI_2X1_CG_DISABLE_MASK_SFT                         (0x1 << 26)
 424 #define AWB_R_MONO_SFT                                      25
 425 #define AWB_R_MONO_MASK                                     0x1
 426 #define AWB_R_MONO_MASK_SFT                                 (0x1 << 25)
 427 #define AWB_DATA_SFT                                        24
 428 #define AWB_DATA_MASK                                       0x1
 429 #define AWB_DATA_MASK_SFT                                   (0x1 << 24)
 430 #define DL3_DATA_SFT                                        23
 431 #define DL3_DATA_MASK                                       0x1
 432 #define DL3_DATA_MASK_SFT                                   (0x1 << 23)
 433 #define DL2_DATA_SFT                                        22
 434 #define DL2_DATA_MASK                                       0x1
 435 #define DL2_DATA_MASK_SFT                                   (0x1 << 22)
 436 #define DL1_DATA_SFT                                        21
 437 #define DL1_DATA_MASK                                       0x1
 438 #define DL1_DATA_MASK_SFT                                   (0x1 << 21)
 439 #define DL1_DATA2_DATA_SFT                                  20
 440 #define DL1_DATA2_DATA_MASK                                 0x1
 441 #define DL1_DATA2_DATA_MASK_SFT                             (0x1 << 20)
 442 #define VUL_MODE_SFT                                        16
 443 #define VUL_MODE_MASK                                       0xf
 444 #define VUL_MODE_MASK_SFT                                   (0xf << 16)
 445 #define AWB_MODE_SFT                                        12
 446 #define AWB_MODE_MASK                                       0xf
 447 #define AWB_MODE_MASK_SFT                                   (0xf << 12)
 448 #define I2S_MODE_SFT                                        8
 449 #define I2S_MODE_MASK                                       0xf
 450 #define I2S_MODE_MASK_SFT                                   (0xf << 8)
 451 #define DL2_MODE_SFT                                        4
 452 #define DL2_MODE_MASK                                       0xf
 453 #define DL2_MODE_MASK_SFT                                   (0xf << 4)
 454 #define DL1_MODE_SFT                                        0
 455 #define DL1_MODE_MASK                                       0xf
 456 #define DL1_MODE_MASK_SFT                                   (0xf << 0)
 457 
 458 /* AFE_ADDA_DL_SRC2_CON0 */
 459 #define DL_2_INPUT_MODE_CTL_SFT                             28
 460 #define DL_2_INPUT_MODE_CTL_MASK                            0xf
 461 #define DL_2_INPUT_MODE_CTL_MASK_SFT                        (0xf << 28)
 462 #define DL_2_CH1_SATURATION_EN_CTL_SFT                      27
 463 #define DL_2_CH1_SATURATION_EN_CTL_MASK                     0x1
 464 #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT                 (0x1 << 27)
 465 #define DL_2_CH2_SATURATION_EN_CTL_SFT                      26
 466 #define DL_2_CH2_SATURATION_EN_CTL_MASK                     0x1
 467 #define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT                 (0x1 << 26)
 468 #define DL_2_OUTPUT_SEL_CTL_SFT                             24
 469 #define DL_2_OUTPUT_SEL_CTL_MASK                            0x3
 470 #define DL_2_OUTPUT_SEL_CTL_MASK_SFT                        (0x3 << 24)
 471 #define DL_2_FADEIN_0START_EN_SFT                           16
 472 #define DL_2_FADEIN_0START_EN_MASK                          0x3
 473 #define DL_2_FADEIN_0START_EN_MASK_SFT                      (0x3 << 16)
 474 #define DL_DISABLE_HW_CG_CTL_SFT                            15
 475 #define DL_DISABLE_HW_CG_CTL_MASK                           0x1
 476 #define DL_DISABLE_HW_CG_CTL_MASK_SFT                       (0x1 << 15)
 477 #define C_DATA_EN_SEL_CTL_PRE_SFT                           14
 478 #define C_DATA_EN_SEL_CTL_PRE_MASK                          0x1
 479 #define C_DATA_EN_SEL_CTL_PRE_MASK_SFT                      (0x1 << 14)
 480 #define DL_2_SIDE_TONE_ON_CTL_PRE_SFT                       13
 481 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK                      0x1
 482 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT                  (0x1 << 13)
 483 #define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT                       12
 484 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK                      0x1
 485 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT                  (0x1 << 12)
 486 #define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT                       11
 487 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK                      0x1
 488 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT                  (0x1 << 11)
 489 #define DL2_ARAMPSP_CTL_PRE_SFT                             9
 490 #define DL2_ARAMPSP_CTL_PRE_MASK                            0x3
 491 #define DL2_ARAMPSP_CTL_PRE_MASK_SFT                        (0x3 << 9)
 492 #define DL_2_IIRMODE_CTL_PRE_SFT                            6
 493 #define DL_2_IIRMODE_CTL_PRE_MASK                           0x7
 494 #define DL_2_IIRMODE_CTL_PRE_MASK_SFT                       (0x7 << 6)
 495 #define DL_2_VOICE_MODE_CTL_PRE_SFT                         5
 496 #define DL_2_VOICE_MODE_CTL_PRE_MASK                        0x1
 497 #define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT                    (0x1 << 5)
 498 #define D2_2_MUTE_CH1_ON_CTL_PRE_SFT                        4
 499 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK                       0x1
 500 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT                   (0x1 << 4)
 501 #define D2_2_MUTE_CH2_ON_CTL_PRE_SFT                        3
 502 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK                       0x1
 503 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT                   (0x1 << 3)
 504 #define DL_2_IIR_ON_CTL_PRE_SFT                             2
 505 #define DL_2_IIR_ON_CTL_PRE_MASK                            0x1
 506 #define DL_2_IIR_ON_CTL_PRE_MASK_SFT                        (0x1 << 2)
 507 #define DL_2_GAIN_ON_CTL_PRE_SFT                            1
 508 #define DL_2_GAIN_ON_CTL_PRE_MASK                           0x1
 509 #define DL_2_GAIN_ON_CTL_PRE_MASK_SFT                       (0x1 << 1)
 510 #define DL_2_SRC_ON_TMP_CTL_PRE_SFT                         0
 511 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK                        0x1
 512 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT                    (0x1 << 0)
 513 
 514 /* AFE_ADDA_DL_SRC2_CON1 */
 515 #define DL_2_GAIN_CTL_PRE_SFT                               16
 516 #define DL_2_GAIN_CTL_PRE_MASK                              0xffff
 517 #define DL_2_GAIN_CTL_PRE_MASK_SFT                          (0xffff << 16)
 518 #define DL_2_GAIN_MODE_CTL_SFT                              0
 519 #define DL_2_GAIN_MODE_CTL_MASK                             0x1
 520 #define DL_2_GAIN_MODE_CTL_MASK_SFT                         (0x1 << 0)
 521 
 522 /* AFE_ADDA_UL_SRC_CON0 */
 523 #define C_COMB_OUT_SIN_GEN_CTL_SFT                          31
 524 #define C_COMB_OUT_SIN_GEN_CTL_MASK                         0x1
 525 #define C_COMB_OUT_SIN_GEN_CTL_MASK_SFT                     (0x1 << 31)
 526 #define C_BASEBAND_SIN_GEN_CTL_SFT                          30
 527 #define C_BASEBAND_SIN_GEN_CTL_MASK                         0x1
 528 #define C_BASEBAND_SIN_GEN_CTL_MASK_SFT                     (0x1 << 30)
 529 #define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT                      27
 530 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK                     0x7
 531 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT                 (0x7 << 27)
 532 #define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT                      24
 533 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK                     0x7
 534 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT                 (0x7 << 24)
 535 #define C_TWO_DIGITAL_MIC_CTL_SFT                           23
 536 #define C_TWO_DIGITAL_MIC_CTL_MASK                          0x1
 537 #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT                      (0x1 << 23)
 538 #define UL_MODE_3P25M_CH2_CTL_SFT                           22
 539 #define UL_MODE_3P25M_CH2_CTL_MASK                          0x1
 540 #define UL_MODE_3P25M_CH2_CTL_MASK_SFT                      (0x1 << 22)
 541 #define UL_MODE_3P25M_CH1_CTL_SFT                           21
 542 #define UL_MODE_3P25M_CH1_CTL_MASK                          0x1
 543 #define UL_MODE_3P25M_CH1_CTL_MASK_SFT                      (0x1 << 21)
 544 #define UL_SRC_USE_CIC_OUT_CTL_SFT                          20
 545 #define UL_SRC_USE_CIC_OUT_CTL_MASK                         0x1
 546 #define UL_SRC_USE_CIC_OUT_CTL_MASK_SFT                     (0x1 << 20)
 547 #define UL_VOICE_MODE_CH1_CH2_CTL_SFT                       17
 548 #define UL_VOICE_MODE_CH1_CH2_CTL_MASK                      0x7
 549 #define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT                  (0x7 << 17)
 550 #define DMIC_LOW_POWER_MODE_CTL_SFT                         14
 551 #define DMIC_LOW_POWER_MODE_CTL_MASK                        0x3
 552 #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT                    (0x3 << 14)
 553 #define DMIC_48K_SEL_CTL_SFT                                13
 554 #define DMIC_48K_SEL_CTL_MASK                               0x1
 555 #define DMIC_48K_SEL_CTL_MASK_SFT                           (0x1 << 13)
 556 #define UL_DISABLE_HW_CG_CTL_SFT                            12
 557 #define UL_DISABLE_HW_CG_CTL_MASK                           0x1
 558 #define UL_DISABLE_HW_CG_CTL_MASK_SFT                       (0x1 << 12)
 559 #define UL_IIR_ON_TMP_CTL_SFT                               10
 560 #define UL_IIR_ON_TMP_CTL_MASK                              0x1
 561 #define UL_IIR_ON_TMP_CTL_MASK_SFT                          (0x1 << 10)
 562 #define UL_IIRMODE_CTL_SFT                                  7
 563 #define UL_IIRMODE_CTL_MASK                                 0x7
 564 #define UL_IIRMODE_CTL_MASK_SFT                             (0x7 << 7)
 565 #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT                     5
 566 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK                    0x1
 567 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT                (0x1 << 5)
 568 #define AGC_260K_SEL_CH2_CTL_SFT                            4
 569 #define AGC_260K_SEL_CH2_CTL_MASK                           0x1
 570 #define AGC_260K_SEL_CH2_CTL_MASK_SFT                       (0x1 << 4)
 571 #define AGC_260K_SEL_CH1_CTL_SFT                            3
 572 #define AGC_260K_SEL_CH1_CTL_MASK                           0x1
 573 #define AGC_260K_SEL_CH1_CTL_MASK_SFT                       (0x1 << 3)
 574 #define UL_LOOP_BACK_MODE_CTL_SFT                           2
 575 #define UL_LOOP_BACK_MODE_CTL_MASK                          0x1
 576 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT                      (0x1 << 2)
 577 #define UL_SDM_3_LEVEL_CTL_SFT                              1
 578 #define UL_SDM_3_LEVEL_CTL_MASK                             0x1
 579 #define UL_SDM_3_LEVEL_CTL_MASK_SFT                         (0x1 << 1)
 580 #define UL_SRC_ON_TMP_CTL_SFT                               0
 581 #define UL_SRC_ON_TMP_CTL_MASK                              0x1
 582 #define UL_SRC_ON_TMP_CTL_MASK_SFT                          (0x1 << 0)
 583 
 584 /* AFE_ADDA_UL_SRC_CON1 */
 585 #define C_SDM_RESET_CTL_SFT                                 31
 586 #define C_SDM_RESET_CTL_MASK                                0x1
 587 #define C_SDM_RESET_CTL_MASK_SFT                            (0x1 << 31)
 588 #define ADITHON_CTL_SFT                                     30
 589 #define ADITHON_CTL_MASK                                    0x1
 590 #define ADITHON_CTL_MASK_SFT                                (0x1 << 30)
 591 #define ADITHVAL_CTL_SFT                                    28
 592 #define ADITHVAL_CTL_MASK                                   0x3
 593 #define ADITHVAL_CTL_MASK_SFT                               (0x3 << 28)
 594 #define C_DAC_EN_CTL_SFT                                    27
 595 #define C_DAC_EN_CTL_MASK                                   0x1
 596 #define C_DAC_EN_CTL_MASK_SFT                               (0x1 << 27)
 597 #define C_MUTE_SW_CTL_SFT                                   26
 598 #define C_MUTE_SW_CTL_MASK                                  0x1
 599 #define C_MUTE_SW_CTL_MASK_SFT                              (0x1 << 26)
 600 #define ASDM_SRC_SEL_CTL_SFT                                25
 601 #define ASDM_SRC_SEL_CTL_MASK                               0x1
 602 #define ASDM_SRC_SEL_CTL_MASK_SFT                           (0x1 << 25)
 603 #define C_AMP_DIV_CH2_CTL_SFT                               21
 604 #define C_AMP_DIV_CH2_CTL_MASK                              0x7
 605 #define C_AMP_DIV_CH2_CTL_MASK_SFT                          (0x7 << 21)
 606 #define C_FREQ_DIV_CH2_CTL_SFT                              16
 607 #define C_FREQ_DIV_CH2_CTL_MASK                             0x1f
 608 #define C_FREQ_DIV_CH2_CTL_MASK_SFT                         (0x1f << 16)
 609 #define C_SINE_MODE_CH2_CTL_SFT                             12
 610 #define C_SINE_MODE_CH2_CTL_MASK                            0xf
 611 #define C_SINE_MODE_CH2_CTL_MASK_SFT                        (0xf << 12)
 612 #define C_AMP_DIV_CH1_CTL_SFT                               9
 613 #define C_AMP_DIV_CH1_CTL_MASK                              0x7
 614 #define C_AMP_DIV_CH1_CTL_MASK_SFT                          (0x7 << 9)
 615 #define C_FREQ_DIV_CH1_CTL_SFT                              4
 616 #define C_FREQ_DIV_CH1_CTL_MASK                             0x1f
 617 #define C_FREQ_DIV_CH1_CTL_MASK_SFT                         (0x1f << 4)
 618 #define C_SINE_MODE_CH1_CTL_SFT                             0
 619 #define C_SINE_MODE_CH1_CTL_MASK                            0xf
 620 #define C_SINE_MODE_CH1_CTL_MASK_SFT                        (0xf << 0)
 621 
 622 /* AFE_ADDA_TOP_CON0 */
 623 #define C_LOOP_BACK_MODE_CTL_SFT                            12
 624 #define C_LOOP_BACK_MODE_CTL_MASK                           0xf
 625 #define C_LOOP_BACK_MODE_CTL_MASK_SFT                       (0xf << 12)
 626 #define C_EXT_ADC_CTL_SFT                                   0
 627 #define C_EXT_ADC_CTL_MASK                                  0x1
 628 #define C_EXT_ADC_CTL_MASK_SFT                              (0x1 << 0)
 629 
 630 /* AFE_ADDA_UL_DL_CON0 */
 631 #define AFE_UL_DL_CON0_RESERVED_SFT                         1
 632 #define AFE_UL_DL_CON0_RESERVED_MASK                        0x3fff
 633 #define AFE_UL_DL_CON0_RESERVED_MASK_SFT                    (0x3fff << 1)
 634 #define ADDA_AFE_ON_SFT                                     0
 635 #define ADDA_AFE_ON_MASK                                    0x1
 636 #define ADDA_AFE_ON_MASK_SFT                                (0x1 << 0)
 637 
 638 /* AFE_IRQ_MCU_CON */
 639 #define IRQ7_MCU_MODE_SFT                                   24
 640 #define IRQ7_MCU_MODE_MASK                                  0xf
 641 #define IRQ7_MCU_MODE_MASK_SFT                              (0xf << 24)
 642 #define IRQ4_MCU_MODE_SFT                                   20
 643 #define IRQ4_MCU_MODE_MASK                                  0xf
 644 #define IRQ4_MCU_MODE_MASK_SFT                              (0xf << 20)
 645 #define IRQ3_MCU_MODE_SFT                                   16
 646 #define IRQ3_MCU_MODE_MASK                                  0xf
 647 #define IRQ3_MCU_MODE_MASK_SFT                              (0xf << 16)
 648 #define IRQ7_MCU_ON_SFT                                     14
 649 #define IRQ7_MCU_ON_MASK                                    0x1
 650 #define IRQ7_MCU_ON_MASK_SFT                                (0x1 << 14)
 651 #define IRQ5_MCU_ON_SFT                                     12
 652 #define IRQ5_MCU_ON_MASK                                    0x1
 653 #define IRQ5_MCU_ON_MASK_SFT                                (0x1 << 12)
 654 #define IRQ2_MCU_MODE_SFT                                   8
 655 #define IRQ2_MCU_MODE_MASK                                  0xf
 656 #define IRQ2_MCU_MODE_MASK_SFT                              (0xf << 8)
 657 #define IRQ1_MCU_MODE_SFT                                   4
 658 #define IRQ1_MCU_MODE_MASK                                  0xf
 659 #define IRQ1_MCU_MODE_MASK_SFT                              (0xf << 4)
 660 #define IRQ4_MCU_ON_SFT                                     3
 661 #define IRQ4_MCU_ON_MASK                                    0x1
 662 #define IRQ4_MCU_ON_MASK_SFT                                (0x1 << 3)
 663 #define IRQ3_MCU_ON_SFT                                     2
 664 #define IRQ3_MCU_ON_MASK                                    0x1
 665 #define IRQ3_MCU_ON_MASK_SFT                                (0x1 << 2)
 666 #define IRQ2_MCU_ON_SFT                                     1
 667 #define IRQ2_MCU_ON_MASK                                    0x1
 668 #define IRQ2_MCU_ON_MASK_SFT                                (0x1 << 1)
 669 #define IRQ1_MCU_ON_SFT                                     0
 670 #define IRQ1_MCU_ON_MASK                                    0x1
 671 #define IRQ1_MCU_ON_MASK_SFT                                (0x1 << 0)
 672 
 673 /* AFE_IRQ_MCU_EN */
 674 #define AFE_IRQ_CM4_EN_SFT                                  16
 675 #define AFE_IRQ_CM4_EN_MASK                                 0x7f
 676 #define AFE_IRQ_CM4_EN_MASK_SFT                             (0x7f << 16)
 677 #define AFE_IRQ_MD32_EN_SFT                                 8
 678 #define AFE_IRQ_MD32_EN_MASK                                0x7f
 679 #define AFE_IRQ_MD32_EN_MASK_SFT                            (0x7f << 8)
 680 #define AFE_IRQ_MCU_EN_SFT                                  0
 681 #define AFE_IRQ_MCU_EN_MASK                                 0x7f
 682 #define AFE_IRQ_MCU_EN_MASK_SFT                             (0x7f << 0)
 683 
 684 /* AFE_IRQ_MCU_CLR */
 685 #define IRQ7_MCU_CLR_SFT                                    6
 686 #define IRQ7_MCU_CLR_MASK                                   0x1
 687 #define IRQ7_MCU_CLR_MASK_SFT                               (0x1 << 6)
 688 #define IRQ5_MCU_CLR_SFT                                    4
 689 #define IRQ5_MCU_CLR_MASK                                   0x1
 690 #define IRQ5_MCU_CLR_MASK_SFT                               (0x1 << 4)
 691 #define IRQ4_MCU_CLR_SFT                                    3
 692 #define IRQ4_MCU_CLR_MASK                                   0x1
 693 #define IRQ4_MCU_CLR_MASK_SFT                               (0x1 << 3)
 694 #define IRQ3_MCU_CLR_SFT                                    2
 695 #define IRQ3_MCU_CLR_MASK                                   0x1
 696 #define IRQ3_MCU_CLR_MASK_SFT                               (0x1 << 2)
 697 #define IRQ2_MCU_CLR_SFT                                    1
 698 #define IRQ2_MCU_CLR_MASK                                   0x1
 699 #define IRQ2_MCU_CLR_MASK_SFT                               (0x1 << 1)
 700 #define IRQ1_MCU_CLR_SFT                                    0
 701 #define IRQ1_MCU_CLR_MASK                                   0x1
 702 #define IRQ1_MCU_CLR_MASK_SFT                               (0x1 << 0)
 703 
 704 /* AFE_IRQ_MCU_CNT1 */
 705 #define AFE_IRQ_MCU_CNT1_SFT                                0
 706 #define AFE_IRQ_MCU_CNT1_MASK                               0x3ffff
 707 #define AFE_IRQ_MCU_CNT1_MASK_SFT                           (0x3ffff << 0)
 708 
 709 /* AFE_IRQ_MCU_CNT2 */
 710 #define AFE_IRQ_MCU_CNT2_SFT                                0
 711 #define AFE_IRQ_MCU_CNT2_MASK                               0x3ffff
 712 #define AFE_IRQ_MCU_CNT2_MASK_SFT                           (0x3ffff << 0)
 713 
 714 /* AFE_IRQ_MCU_CNT3 */
 715 #define AFE_IRQ_MCU_CNT3_SFT                                0
 716 #define AFE_IRQ_MCU_CNT3_MASK                               0x3ffff
 717 #define AFE_IRQ_MCU_CNT3_MASK_SFT                           (0x3ffff << 0)
 718 
 719 /* AFE_IRQ_MCU_CNT4 */
 720 #define AFE_IRQ_MCU_CNT4_SFT                                0
 721 #define AFE_IRQ_MCU_CNT4_MASK                               0x3ffff
 722 #define AFE_IRQ_MCU_CNT4_MASK_SFT                           (0x3ffff << 0)
 723 
 724 /* AFE_IRQ_MCU_CNT5 */
 725 #define AFE_IRQ_MCU_CNT5_SFT                                0
 726 #define AFE_IRQ_MCU_CNT5_MASK                               0x3ffff
 727 #define AFE_IRQ_MCU_CNT5_MASK_SFT                           (0x3ffff << 0)
 728 
 729 /* AFE_IRQ_MCU_CNT7 */
 730 #define AFE_IRQ_MCU_CNT7_SFT                                0
 731 #define AFE_IRQ_MCU_CNT7_MASK                               0x3ffff
 732 #define AFE_IRQ_MCU_CNT7_MASK_SFT                           (0x3ffff << 0)
 733 
 734 /* AFE_MEMIF_MSB */
 735 #define CPU_COMPACT_MODE_SFT                                23
 736 #define CPU_COMPACT_MODE_MASK                               0x1
 737 #define CPU_COMPACT_MODE_MASK_SFT                           (0x1 << 23)
 738 #define CPU_HD_ALIGN_SFT                                    22
 739 #define CPU_HD_ALIGN_MASK                                   0x1
 740 #define CPU_HD_ALIGN_MASK_SFT                               (0x1 << 22)
 741 
 742 /* AFE_MEMIF_HD_MODE */
 743 #define HDMI_HD_SFT                                         20
 744 #define HDMI_HD_MASK                                        0x3
 745 #define HDMI_HD_MASK_SFT                                    (0x3 << 20)
 746 #define MOD_DAI_HD_SFT                                      18
 747 #define MOD_DAI_HD_MASK                                     0x3
 748 #define MOD_DAI_HD_MASK_SFT                                 (0x3 << 18)
 749 #define DAI_HD_SFT                                          16
 750 #define DAI_HD_MASK                                         0x3
 751 #define DAI_HD_MASK_SFT                                     (0x3 << 16)
 752 #define VUL_DATA2_HD_SFT                                    12
 753 #define VUL_DATA2_HD_MASK                                   0x3
 754 #define VUL_DATA2_HD_MASK_SFT                               (0x3 << 12)
 755 #define VUL_HD_SFT                                          10
 756 #define VUL_HD_MASK                                         0x3
 757 #define VUL_HD_MASK_SFT                                     (0x3 << 10)
 758 #define AWB_HD_SFT                                          8
 759 #define AWB_HD_MASK                                         0x3
 760 #define AWB_HD_MASK_SFT                                     (0x3 << 8)
 761 #define DL3_HD_SFT                                          6
 762 #define DL3_HD_MASK                                         0x3
 763 #define DL3_HD_MASK_SFT                                     (0x3 << 6)
 764 #define DL2_HD_SFT                                          4
 765 #define DL2_HD_MASK                                         0x3
 766 #define DL2_HD_MASK_SFT                                     (0x3 << 4)
 767 #define DL1_DATA2_HD_SFT                                    2
 768 #define DL1_DATA2_HD_MASK                                   0x3
 769 #define DL1_DATA2_HD_MASK_SFT                               (0x3 << 2)
 770 #define DL1_HD_SFT                                          0
 771 #define DL1_HD_MASK                                         0x3
 772 #define DL1_HD_MASK_SFT                                     (0x3 << 0)
 773 
 774 /* AFE_MEMIF_HDALIGN */
 775 #define HDMI_NORMAL_MODE_SFT                                26
 776 #define HDMI_NORMAL_MODE_MASK                               0x1
 777 #define HDMI_NORMAL_MODE_MASK_SFT                           (0x1 << 26)
 778 #define MOD_DAI_NORMAL_MODE_SFT                             25
 779 #define MOD_DAI_NORMAL_MODE_MASK                            0x1
 780 #define MOD_DAI_NORMAL_MODE_MASK_SFT                        (0x1 << 25)
 781 #define DAI_NORMAL_MODE_SFT                                 24
 782 #define DAI_NORMAL_MODE_MASK                                0x1
 783 #define DAI_NORMAL_MODE_MASK_SFT                            (0x1 << 24)
 784 #define VUL_DATA2_NORMAL_MODE_SFT                           22
 785 #define VUL_DATA2_NORMAL_MODE_MASK                          0x1
 786 #define VUL_DATA2_NORMAL_MODE_MASK_SFT                      (0x1 << 22)
 787 #define VUL_NORMAL_MODE_SFT                                 21
 788 #define VUL_NORMAL_MODE_MASK                                0x1
 789 #define VUL_NORMAL_MODE_MASK_SFT                            (0x1 << 21)
 790 #define AWB_NORMAL_MODE_SFT                                 20
 791 #define AWB_NORMAL_MODE_MASK                                0x1
 792 #define AWB_NORMAL_MODE_MASK_SFT                            (0x1 << 20)
 793 #define DL3_NORMAL_MODE_SFT                                 19
 794 #define DL3_NORMAL_MODE_MASK                                0x1
 795 #define DL3_NORMAL_MODE_MASK_SFT                            (0x1 << 19)
 796 #define DL2_NORMAL_MODE_SFT                                 18
 797 #define DL2_NORMAL_MODE_MASK                                0x1
 798 #define DL2_NORMAL_MODE_MASK_SFT                            (0x1 << 18)
 799 #define DL1_DATA2_NORMAL_MODE_SFT                           17
 800 #define DL1_DATA2_NORMAL_MODE_MASK                          0x1
 801 #define DL1_DATA2_NORMAL_MODE_MASK_SFT                      (0x1 << 17)
 802 #define DL1_NORMAL_MODE_SFT                                 16
 803 #define DL1_NORMAL_MODE_MASK                                0x1
 804 #define DL1_NORMAL_MODE_MASK_SFT                            (0x1 << 16)
 805 #define HDMI_HD_ALIGN_SFT                                   10
 806 #define HDMI_HD_ALIGN_MASK                                  0x1
 807 #define HDMI_HD_ALIGN_MASK_SFT                              (0x1 << 10)
 808 #define MOD_DAI_HD_ALIGN_SFT                                9
 809 #define MOD_DAI_HD_ALIGN_MASK                               0x1
 810 #define MOD_DAI_HD_ALIGN_MASK_SFT                           (0x1 << 9)
 811 #define DAI_ALIGN_SFT                                       8
 812 #define DAI_ALIGN_MASK                                      0x1
 813 #define DAI_ALIGN_MASK_SFT                                  (0x1 << 8)
 814 #define VUL2_HD_ALIGN_SFT                                   7
 815 #define VUL2_HD_ALIGN_MASK                                  0x1
 816 #define VUL2_HD_ALIGN_MASK_SFT                              (0x1 << 7)
 817 #define VUL_DATA2_HD_ALIGN_SFT                              6
 818 #define VUL_DATA2_HD_ALIGN_MASK                             0x1
 819 #define VUL_DATA2_HD_ALIGN_MASK_SFT                         (0x1 << 6)
 820 #define VUL_HD_ALIGN_SFT                                    5
 821 #define VUL_HD_ALIGN_MASK                                   0x1
 822 #define VUL_HD_ALIGN_MASK_SFT                               (0x1 << 5)
 823 #define AWB_HD_ALIGN_SFT                                    4
 824 #define AWB_HD_ALIGN_MASK                                   0x1
 825 #define AWB_HD_ALIGN_MASK_SFT                               (0x1 << 4)
 826 #define DL3_HD_ALIGN_SFT                                    3
 827 #define DL3_HD_ALIGN_MASK                                   0x1
 828 #define DL3_HD_ALIGN_MASK_SFT                               (0x1 << 3)
 829 #define DL2_HD_ALIGN_SFT                                    2
 830 #define DL2_HD_ALIGN_MASK                                   0x1
 831 #define DL2_HD_ALIGN_MASK_SFT                               (0x1 << 2)
 832 #define DL1_DATA2_HD_ALIGN_SFT                              1
 833 #define DL1_DATA2_HD_ALIGN_MASK                             0x1
 834 #define DL1_DATA2_HD_ALIGN_MASK_SFT                         (0x1 << 1)
 835 #define DL1_HD_ALIGN_SFT                                    0
 836 #define DL1_HD_ALIGN_MASK                                   0x1
 837 #define DL1_HD_ALIGN_MASK_SFT                               (0x1 << 0)
 838 
 839 /* PCM_INTF_CON1 */
 840 #define PCM_FIX_VALUE_SEL_SFT                               31
 841 #define PCM_FIX_VALUE_SEL_MASK                              0x1
 842 #define PCM_FIX_VALUE_SEL_MASK_SFT                          (0x1 << 31)
 843 #define PCM_BUFFER_LOOPBACK_SFT                             30
 844 #define PCM_BUFFER_LOOPBACK_MASK                            0x1
 845 #define PCM_BUFFER_LOOPBACK_MASK_SFT                        (0x1 << 30)
 846 #define PCM_PARALLEL_LOOPBACK_SFT                           29
 847 #define PCM_PARALLEL_LOOPBACK_MASK                          0x1
 848 #define PCM_PARALLEL_LOOPBACK_MASK_SFT                      (0x1 << 29)
 849 #define PCM_SERIAL_LOOPBACK_SFT                             28
 850 #define PCM_SERIAL_LOOPBACK_MASK                            0x1
 851 #define PCM_SERIAL_LOOPBACK_MASK_SFT                        (0x1 << 28)
 852 #define PCM_DAI_PCM_LOOPBACK_SFT                            27
 853 #define PCM_DAI_PCM_LOOPBACK_MASK                           0x1
 854 #define PCM_DAI_PCM_LOOPBACK_MASK_SFT                       (0x1 << 27)
 855 #define PCM_I2S_PCM_LOOPBACK_SFT                            26
 856 #define PCM_I2S_PCM_LOOPBACK_MASK                           0x1
 857 #define PCM_I2S_PCM_LOOPBACK_MASK_SFT                       (0x1 << 26)
 858 #define PCM_SYNC_DELSEL_SFT                                 25
 859 #define PCM_SYNC_DELSEL_MASK                                0x1
 860 #define PCM_SYNC_DELSEL_MASK_SFT                            (0x1 << 25)
 861 #define PCM_TX_LR_SWAP_SFT                                  24
 862 #define PCM_TX_LR_SWAP_MASK                                 0x1
 863 #define PCM_TX_LR_SWAP_MASK_SFT                             (0x1 << 24)
 864 #define PCM_SYNC_OUT_INV_SFT                                23
 865 #define PCM_SYNC_OUT_INV_MASK                               0x1
 866 #define PCM_SYNC_OUT_INV_MASK_SFT                           (0x1 << 23)
 867 #define PCM_BCLK_OUT_INV_SFT                                22
 868 #define PCM_BCLK_OUT_INV_MASK                               0x1
 869 #define PCM_BCLK_OUT_INV_MASK_SFT                           (0x1 << 22)
 870 #define PCM_SYNC_IN_INV_SFT                                 21
 871 #define PCM_SYNC_IN_INV_MASK                                0x1
 872 #define PCM_SYNC_IN_INV_MASK_SFT                            (0x1 << 21)
 873 #define PCM_BCLK_IN_INV_SFT                                 20
 874 #define PCM_BCLK_IN_INV_MASK                                0x1
 875 #define PCM_BCLK_IN_INV_MASK_SFT                            (0x1 << 20)
 876 #define PCM_TX_LCH_RPT_SFT                                  19
 877 #define PCM_TX_LCH_RPT_MASK                                 0x1
 878 #define PCM_TX_LCH_RPT_MASK_SFT                             (0x1 << 19)
 879 #define PCM_VBT_16K_MODE_SFT                                18
 880 #define PCM_VBT_16K_MODE_MASK                               0x1
 881 #define PCM_VBT_16K_MODE_MASK_SFT                           (0x1 << 18)
 882 #define PCM_EXT_MODEM_SFT                                   17
 883 #define PCM_EXT_MODEM_MASK                                  0x1
 884 #define PCM_EXT_MODEM_MASK_SFT                              (0x1 << 17)
 885 #define PCM_24BIT_SFT                                       16
 886 #define PCM_24BIT_MASK                                      0x1
 887 #define PCM_24BIT_MASK_SFT                                  (0x1 << 16)
 888 #define PCM_WLEN_SFT                                        14
 889 #define PCM_WLEN_MASK                                       0x3
 890 #define PCM_WLEN_MASK_SFT                                   (0x3 << 14)
 891 #define PCM_SYNC_LENGTH_SFT                                 9
 892 #define PCM_SYNC_LENGTH_MASK                                0x1f
 893 #define PCM_SYNC_LENGTH_MASK_SFT                            (0x1f << 9)
 894 #define PCM_SYNC_TYPE_SFT                                   8
 895 #define PCM_SYNC_TYPE_MASK                                  0x1
 896 #define PCM_SYNC_TYPE_MASK_SFT                              (0x1 << 8)
 897 #define PCM_BT_MODE_SFT                                     7
 898 #define PCM_BT_MODE_MASK                                    0x1
 899 #define PCM_BT_MODE_MASK_SFT                                (0x1 << 7)
 900 #define PCM_BYP_ASRC_SFT                                    6
 901 #define PCM_BYP_ASRC_MASK                                   0x1
 902 #define PCM_BYP_ASRC_MASK_SFT                               (0x1 << 6)
 903 #define PCM_SLAVE_SFT                                       5
 904 #define PCM_SLAVE_MASK                                      0x1
 905 #define PCM_SLAVE_MASK_SFT                                  (0x1 << 5)
 906 #define PCM_MODE_SFT                                        3
 907 #define PCM_MODE_MASK                                       0x3
 908 #define PCM_MODE_MASK_SFT                                   (0x3 << 3)
 909 #define PCM_FMT_SFT                                         1
 910 #define PCM_FMT_MASK                                        0x3
 911 #define PCM_FMT_MASK_SFT                                    (0x3 << 1)
 912 #define PCM_EN_SFT                                          0
 913 #define PCM_EN_MASK                                         0x1
 914 #define PCM_EN_MASK_SFT                                     (0x1 << 0)
 915 
 916 /* PCM_INTF_CON2 */
 917 #define PCM1_TX_FIFO_OV_SFT                                 31
 918 #define PCM1_TX_FIFO_OV_MASK                                0x1
 919 #define PCM1_TX_FIFO_OV_MASK_SFT                            (0x1 << 31)
 920 #define PCM1_RX_FIFO_OV_SFT                                 30
 921 #define PCM1_RX_FIFO_OV_MASK                                0x1
 922 #define PCM1_RX_FIFO_OV_MASK_SFT                            (0x1 << 30)
 923 #define PCM2_TX_FIFO_OV_SFT                                 29
 924 #define PCM2_TX_FIFO_OV_MASK                                0x1
 925 #define PCM2_TX_FIFO_OV_MASK_SFT                            (0x1 << 29)
 926 #define PCM2_RX_FIFO_OV_SFT                                 28
 927 #define PCM2_RX_FIFO_OV_MASK                                0x1
 928 #define PCM2_RX_FIFO_OV_MASK_SFT                            (0x1 << 28)
 929 #define PCM1_SYNC_GLITCH_SFT                                27
 930 #define PCM1_SYNC_GLITCH_MASK                               0x1
 931 #define PCM1_SYNC_GLITCH_MASK_SFT                           (0x1 << 27)
 932 #define PCM2_SYNC_GLITCH_SFT                                26
 933 #define PCM2_SYNC_GLITCH_MASK                               0x1
 934 #define PCM2_SYNC_GLITCH_MASK_SFT                           (0x1 << 26)
 935 #define PCM1_PCM2_LOOPBACK_SFT                              15
 936 #define PCM1_PCM2_LOOPBACK_MASK                             0x1
 937 #define PCM1_PCM2_LOOPBACK_MASK_SFT                         (0x1 << 15)
 938 #define DAI_PCM_LOOPBACK_CH_SFT                             13
 939 #define DAI_PCM_LOOPBACK_CH_MASK                            0x1
 940 #define DAI_PCM_LOOPBACK_CH_MASK_SFT                        (0x1 << 13)
 941 #define I2S_PCM_LOOPBACK_CH_SFT                             12
 942 #define I2S_PCM_LOOPBACK_CH_MASK                            0x1
 943 #define I2S_PCM_LOOPBACK_CH_MASK_SFT                        (0x1 << 12)
 944 #define PCM_USE_MD3_SFT                                     8
 945 #define PCM_USE_MD3_MASK                                    0x1
 946 #define PCM_USE_MD3_MASK_SFT                                (0x1 << 8)
 947 #define TX_FIX_VALUE_SFT                                    0
 948 #define TX_FIX_VALUE_MASK                                   0xff
 949 #define TX_FIX_VALUE_MASK_SFT                               (0xff << 0)
 950 
 951 /* PCM2_INTF_CON */
 952 #define PCM2_TX_FIX_VALUE_SFT                                24
 953 #define PCM2_TX_FIX_VALUE_MASK                               0xff
 954 #define PCM2_TX_FIX_VALUE_MASK_SFT                           (0xff << 24)
 955 #define PCM2_FIX_VALUE_SEL_SFT                               23
 956 #define PCM2_FIX_VALUE_SEL_MASK                              0x1
 957 #define PCM2_FIX_VALUE_SEL_MASK_SFT                          (0x1 << 23)
 958 #define PCM2_BUFFER_LOOPBACK_SFT                             22
 959 #define PCM2_BUFFER_LOOPBACK_MASK                            0x1
 960 #define PCM2_BUFFER_LOOPBACK_MASK_SFT                        (0x1 << 22)
 961 #define PCM2_PARALLEL_LOOPBACK_SFT                           21
 962 #define PCM2_PARALLEL_LOOPBACK_MASK                          0x1
 963 #define PCM2_PARALLEL_LOOPBACK_MASK_SFT                      (0x1 << 21)
 964 #define PCM2_SERIAL_LOOPBACK_SFT                             20
 965 #define PCM2_SERIAL_LOOPBACK_MASK                            0x1
 966 #define PCM2_SERIAL_LOOPBACK_MASK_SFT                        (0x1 << 20)
 967 #define PCM2_DAI_PCM_LOOPBACK_SFT                            19
 968 #define PCM2_DAI_PCM_LOOPBACK_MASK                           0x1
 969 #define PCM2_DAI_PCM_LOOPBACK_MASK_SFT                       (0x1 << 19)
 970 #define PCM2_I2S_PCM_LOOPBACK_SFT                            18
 971 #define PCM2_I2S_PCM_LOOPBACK_MASK                           0x1
 972 #define PCM2_I2S_PCM_LOOPBACK_MASK_SFT                       (0x1 << 18)
 973 #define PCM2_SYNC_DELSEL_SFT                                 17
 974 #define PCM2_SYNC_DELSEL_MASK                                0x1
 975 #define PCM2_SYNC_DELSEL_MASK_SFT                            (0x1 << 17)
 976 #define PCM2_TX_LR_SWAP_SFT                                  16
 977 #define PCM2_TX_LR_SWAP_MASK                                 0x1
 978 #define PCM2_TX_LR_SWAP_MASK_SFT                             (0x1 << 16)
 979 #define PCM2_SYNC_IN_INV_SFT                                 15
 980 #define PCM2_SYNC_IN_INV_MASK                                0x1
 981 #define PCM2_SYNC_IN_INV_MASK_SFT                            (0x1 << 15)
 982 #define PCM2_BCLK_IN_INV_SFT                                 14
 983 #define PCM2_BCLK_IN_INV_MASK                                0x1
 984 #define PCM2_BCLK_IN_INV_MASK_SFT                            (0x1 << 14)
 985 #define PCM2_TX_LCH_RPT_SFT                                  13
 986 #define PCM2_TX_LCH_RPT_MASK                                 0x1
 987 #define PCM2_TX_LCH_RPT_MASK_SFT                             (0x1 << 13)
 988 #define PCM2_VBT_16K_MODE_SFT                                12
 989 #define PCM2_VBT_16K_MODE_MASK                               0x1
 990 #define PCM2_VBT_16K_MODE_MASK_SFT                           (0x1 << 12)
 991 #define PCM2_LOOPBACK_CH_SEL_SFT                             10
 992 #define PCM2_LOOPBACK_CH_SEL_MASK                            0x3
 993 #define PCM2_LOOPBACK_CH_SEL_MASK_SFT                        (0x3 << 10)
 994 #define PCM2_TX2_BT_MODE_SFT                                 8
 995 #define PCM2_TX2_BT_MODE_MASK                                0x1
 996 #define PCM2_TX2_BT_MODE_MASK_SFT                            (0x1 << 8)
 997 #define PCM2_BT_MODE_SFT                                     7
 998 #define PCM2_BT_MODE_MASK                                    0x1
 999 #define PCM2_BT_MODE_MASK_SFT                                (0x1 << 7)
1000 #define PCM2_AFIFO_SFT                                       6
1001 #define PCM2_AFIFO_MASK                                      0x1
1002 #define PCM2_AFIFO_MASK_SFT                                  (0x1 << 6)
1003 #define PCM2_WLEN_SFT                                        5
1004 #define PCM2_WLEN_MASK                                       0x1
1005 #define PCM2_WLEN_MASK_SFT                                   (0x1 << 5)
1006 #define PCM2_MODE_SFT                                        3
1007 #define PCM2_MODE_MASK                                       0x3
1008 #define PCM2_MODE_MASK_SFT                                   (0x3 << 3)
1009 #define PCM2_FMT_SFT                                         1
1010 #define PCM2_FMT_MASK                                        0x3
1011 #define PCM2_FMT_MASK_SFT                                    (0x3 << 1)
1012 #define PCM2_EN_SFT                                          0
1013 #define PCM2_EN_MASK                                         0x1
1014 #define PCM2_EN_MASK_SFT                                     (0x1 << 0)
1015 #endif

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