This source file includes following definitions.
- mt2701_dai_num_to_i2s
- mt2701_afe_i2s_fs
- mt2701_afe_i2s_startup
- mt2701_afe_i2s_path_disable
- mt2701_afe_i2s_shutdown
- mt2701_i2s_path_enable
- mt2701_afe_i2s_prepare
- mt2701_afe_i2s_set_sysclk
- mt2701_btmrg_startup
- mt2701_btmrg_hw_params
- mt2701_btmrg_shutdown
- mt2701_simple_fe_startup
- mt2701_simple_fe_hw_params
- mt2701_dlm_fe_startup
- mt2701_dlm_fe_shutdown
- mt2701_dlm_fe_hw_params
- mt2701_dlm_fe_trigger
- mt2701_memif_fs
- mt2701_irq_fs
- mt2701_afe_pcm_probe
- mt2701_asys_isr
- mt2701_afe_runtime_suspend
- mt2701_afe_runtime_resume
- mt2701_afe_pcm_dev_probe
- mt2701_afe_pcm_dev_remove
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11 #include <linux/delay.h>
12 #include <linux/module.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/pm_runtime.h>
18
19 #include "mt2701-afe-common.h"
20 #include "mt2701-afe-clock-ctrl.h"
21 #include "../common/mtk-afe-platform-driver.h"
22 #include "../common/mtk-afe-fe-dai.h"
23
24 static const struct snd_pcm_hardware mt2701_afe_hardware = {
25 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
26 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
27 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE
28 | SNDRV_PCM_FMTBIT_S32_LE,
29 .period_bytes_min = 1024,
30 .period_bytes_max = 1024 * 256,
31 .periods_min = 4,
32 .periods_max = 1024,
33 .buffer_bytes_max = 1024 * 1024,
34 .fifo_size = 0,
35 };
36
37 struct mt2701_afe_rate {
38 unsigned int rate;
39 unsigned int regvalue;
40 };
41
42 static const struct mt2701_afe_rate mt2701_afe_i2s_rates[] = {
43 { .rate = 8000, .regvalue = 0 },
44 { .rate = 12000, .regvalue = 1 },
45 { .rate = 16000, .regvalue = 2 },
46 { .rate = 24000, .regvalue = 3 },
47 { .rate = 32000, .regvalue = 4 },
48 { .rate = 48000, .regvalue = 5 },
49 { .rate = 96000, .regvalue = 6 },
50 { .rate = 192000, .regvalue = 7 },
51 { .rate = 384000, .regvalue = 8 },
52 { .rate = 7350, .regvalue = 16 },
53 { .rate = 11025, .regvalue = 17 },
54 { .rate = 14700, .regvalue = 18 },
55 { .rate = 22050, .regvalue = 19 },
56 { .rate = 29400, .regvalue = 20 },
57 { .rate = 44100, .regvalue = 21 },
58 { .rate = 88200, .regvalue = 22 },
59 { .rate = 176400, .regvalue = 23 },
60 { .rate = 352800, .regvalue = 24 },
61 };
62
63 static const unsigned int mt2701_afe_backup_list[] = {
64 AUDIO_TOP_CON0,
65 AUDIO_TOP_CON4,
66 AUDIO_TOP_CON5,
67 ASYS_TOP_CON,
68 AFE_CONN0,
69 AFE_CONN1,
70 AFE_CONN2,
71 AFE_CONN3,
72 AFE_CONN15,
73 AFE_CONN16,
74 AFE_CONN17,
75 AFE_CONN18,
76 AFE_CONN19,
77 AFE_CONN20,
78 AFE_CONN21,
79 AFE_CONN22,
80 AFE_DAC_CON0,
81 AFE_MEMIF_PBUF_SIZE,
82 };
83
84 static int mt2701_dai_num_to_i2s(struct mtk_base_afe *afe, int num)
85 {
86 struct mt2701_afe_private *afe_priv = afe->platform_priv;
87 int val = num - MT2701_IO_I2S;
88
89 if (val < 0 || val >= afe_priv->soc->i2s_num) {
90 dev_err(afe->dev, "%s, num not available, num %d, val %d\n",
91 __func__, num, val);
92 return -EINVAL;
93 }
94 return val;
95 }
96
97 static int mt2701_afe_i2s_fs(unsigned int sample_rate)
98 {
99 int i;
100
101 for (i = 0; i < ARRAY_SIZE(mt2701_afe_i2s_rates); i++)
102 if (mt2701_afe_i2s_rates[i].rate == sample_rate)
103 return mt2701_afe_i2s_rates[i].regvalue;
104
105 return -EINVAL;
106 }
107
108 static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream,
109 struct snd_soc_dai *dai)
110 {
111 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
112 struct mt2701_afe_private *afe_priv = afe->platform_priv;
113 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
114 bool mode = afe_priv->soc->has_one_heart_mode;
115
116 if (i2s_num < 0)
117 return i2s_num;
118
119 return mt2701_afe_enable_mclk(afe, mode ? 1 : i2s_num);
120 }
121
122 static int mt2701_afe_i2s_path_disable(struct mtk_base_afe *afe,
123 struct mt2701_i2s_path *i2s_path,
124 int stream_dir)
125 {
126 const struct mt2701_i2s_data *i2s_data = i2s_path->i2s_data[stream_dir];
127
128 if (--i2s_path->on[stream_dir] < 0)
129 i2s_path->on[stream_dir] = 0;
130
131 if (i2s_path->on[stream_dir])
132 return 0;
133
134
135 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
136 ASYS_I2S_CON_I2S_EN, 0);
137
138 mt2701_afe_disable_i2s(afe, i2s_path, stream_dir);
139
140 return 0;
141 }
142
143 static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
144 struct snd_soc_dai *dai)
145 {
146 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
147 struct mt2701_afe_private *afe_priv = afe->platform_priv;
148 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
149 struct mt2701_i2s_path *i2s_path;
150 bool mode = afe_priv->soc->has_one_heart_mode;
151
152 if (i2s_num < 0)
153 return;
154
155 i2s_path = &afe_priv->i2s_path[i2s_num];
156
157 if (i2s_path->occupied[substream->stream])
158 i2s_path->occupied[substream->stream] = 0;
159 else
160 goto exit;
161
162 mt2701_afe_i2s_path_disable(afe, i2s_path, substream->stream);
163
164
165 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
166 mt2701_afe_i2s_path_disable(afe, i2s_path, !substream->stream);
167
168 exit:
169
170 mt2701_afe_disable_mclk(afe, mode ? 1 : i2s_num);
171 }
172
173 static int mt2701_i2s_path_enable(struct mtk_base_afe *afe,
174 struct mt2701_i2s_path *i2s_path,
175 int stream_dir, int rate)
176 {
177 const struct mt2701_i2s_data *i2s_data = i2s_path->i2s_data[stream_dir];
178 struct mt2701_afe_private *afe_priv = afe->platform_priv;
179 int reg, fs, w_len = 1;
180 unsigned int mask, val;
181
182
183 if (++i2s_path->on[stream_dir] != 1)
184 return 0;
185
186 fs = mt2701_afe_i2s_fs(rate);
187
188 mask = ASYS_I2S_CON_FS |
189 ASYS_I2S_CON_I2S_COUPLE_MODE |
190 ASYS_I2S_CON_I2S_MODE |
191 ASYS_I2S_CON_WIDE_MODE;
192
193 val = ASYS_I2S_CON_FS_SET(fs) |
194 ASYS_I2S_CON_I2S_MODE |
195 ASYS_I2S_CON_WIDE_MODE_SET(w_len);
196
197 if (stream_dir == SNDRV_PCM_STREAM_CAPTURE) {
198 mask |= ASYS_I2S_IN_PHASE_FIX;
199 val |= ASYS_I2S_IN_PHASE_FIX;
200 reg = ASMI_TIMING_CON1;
201 } else {
202 if (afe_priv->soc->has_one_heart_mode) {
203 mask |= ASYS_I2S_CON_ONE_HEART_MODE;
204 val |= ASYS_I2S_CON_ONE_HEART_MODE;
205 }
206 reg = ASMO_TIMING_CON1;
207 }
208
209 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, mask, val);
210
211 regmap_update_bits(afe->regmap, reg,
212 i2s_data->i2s_asrc_fs_mask
213 << i2s_data->i2s_asrc_fs_shift,
214 fs << i2s_data->i2s_asrc_fs_shift);
215
216
217 mt2701_afe_enable_i2s(afe, i2s_path, stream_dir);
218
219
220 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
221 ASYS_I2S_CON_RESET, ASYS_I2S_CON_RESET);
222 udelay(1);
223 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
224 ASYS_I2S_CON_RESET, 0);
225 udelay(1);
226 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
227 ASYS_I2S_CON_I2S_EN, ASYS_I2S_CON_I2S_EN);
228 return 0;
229 }
230
231 static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream,
232 struct snd_soc_dai *dai)
233 {
234 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
235 struct mt2701_afe_private *afe_priv = afe->platform_priv;
236 int ret, i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
237 struct mt2701_i2s_path *i2s_path;
238 bool mode = afe_priv->soc->has_one_heart_mode;
239
240 if (i2s_num < 0)
241 return i2s_num;
242
243 i2s_path = &afe_priv->i2s_path[i2s_num];
244
245 if (i2s_path->occupied[substream->stream])
246 return -EBUSY;
247
248 ret = mt2701_mclk_configuration(afe, mode ? 1 : i2s_num);
249 if (ret)
250 return ret;
251
252 i2s_path->occupied[substream->stream] = 1;
253
254
255 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
256 mt2701_i2s_path_enable(afe, i2s_path, !substream->stream,
257 substream->runtime->rate);
258
259 mt2701_i2s_path_enable(afe, i2s_path, substream->stream,
260 substream->runtime->rate);
261
262 return 0;
263 }
264
265 static int mt2701_afe_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
266 unsigned int freq, int dir)
267 {
268 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
269 struct mt2701_afe_private *afe_priv = afe->platform_priv;
270 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
271 bool mode = afe_priv->soc->has_one_heart_mode;
272
273 if (i2s_num < 0)
274 return i2s_num;
275
276
277 if (dir == SND_SOC_CLOCK_IN) {
278 dev_warn(dai->dev, "The SoCs doesn't support mclk input\n");
279 return -EINVAL;
280 }
281
282 afe_priv->i2s_path[mode ? 1 : i2s_num].mclk_rate = freq;
283
284 return 0;
285 }
286
287 static int mt2701_btmrg_startup(struct snd_pcm_substream *substream,
288 struct snd_soc_dai *dai)
289 {
290 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
291 struct mt2701_afe_private *afe_priv = afe->platform_priv;
292 int ret;
293
294 ret = mt2701_enable_btmrg_clk(afe);
295 if (ret)
296 return ret;
297
298 afe_priv->mrg_enable[substream->stream] = 1;
299
300 return 0;
301 }
302
303 static int mt2701_btmrg_hw_params(struct snd_pcm_substream *substream,
304 struct snd_pcm_hw_params *params,
305 struct snd_soc_dai *dai)
306 {
307 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
308 int stream_fs;
309 u32 val, msk;
310
311 stream_fs = params_rate(params);
312
313 if (stream_fs != 8000 && stream_fs != 16000) {
314 dev_err(afe->dev, "unsupported rate %d\n", stream_fs);
315 return -EINVAL;
316 }
317
318 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
319 AFE_MRGIF_CON_I2S_MODE_MASK,
320 AFE_MRGIF_CON_I2S_MODE_32K);
321
322 val = AFE_DAIBT_CON0_BT_FUNC_EN | AFE_DAIBT_CON0_BT_FUNC_RDY
323 | AFE_DAIBT_CON0_MRG_USE;
324 msk = val;
325
326 if (stream_fs == 16000)
327 val |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
328
329 msk |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
330
331 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0, msk, val);
332
333 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
334 AFE_DAIBT_CON0_DAIBT_EN,
335 AFE_DAIBT_CON0_DAIBT_EN);
336 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
337 AFE_MRGIF_CON_MRG_I2S_EN,
338 AFE_MRGIF_CON_MRG_I2S_EN);
339 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
340 AFE_MRGIF_CON_MRG_EN,
341 AFE_MRGIF_CON_MRG_EN);
342 return 0;
343 }
344
345 static void mt2701_btmrg_shutdown(struct snd_pcm_substream *substream,
346 struct snd_soc_dai *dai)
347 {
348 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
349 struct mt2701_afe_private *afe_priv = afe->platform_priv;
350
351
352 if (!afe_priv->mrg_enable[!substream->stream]) {
353 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
354 AFE_DAIBT_CON0_DAIBT_EN, 0);
355 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
356 AFE_MRGIF_CON_MRG_EN, 0);
357 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
358 AFE_MRGIF_CON_MRG_I2S_EN, 0);
359 mt2701_disable_btmrg_clk(afe);
360 }
361
362 afe_priv->mrg_enable[substream->stream] = 0;
363 }
364
365 static int mt2701_simple_fe_startup(struct snd_pcm_substream *substream,
366 struct snd_soc_dai *dai)
367 {
368 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
369 struct mtk_base_afe_memif *memif_tmp;
370 int stream_dir = substream->stream;
371
372
373 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) {
374 memif_tmp = &afe->memif[MT2701_MEMIF_DLM];
375 if (memif_tmp->substream) {
376 dev_warn(afe->dev, "memif is not available");
377 return -EBUSY;
378 }
379 }
380
381 return mtk_afe_fe_startup(substream, dai);
382 }
383
384 static int mt2701_simple_fe_hw_params(struct snd_pcm_substream *substream,
385 struct snd_pcm_hw_params *params,
386 struct snd_soc_dai *dai)
387 {
388 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
389 int stream_dir = substream->stream;
390
391
392 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
393 regmap_update_bits(afe->regmap,
394 AFE_MEMIF_PBUF_SIZE,
395 AFE_MEMIF_PBUF_SIZE_DLM_MASK,
396 AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE);
397
398 return mtk_afe_fe_hw_params(substream, params, dai);
399 }
400
401 static int mt2701_dlm_fe_startup(struct snd_pcm_substream *substream,
402 struct snd_soc_dai *dai)
403 {
404 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
405 struct mtk_base_afe_memif *memif_tmp;
406 const struct mtk_base_memif_data *memif_data;
407 int i;
408
409 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
410 memif_tmp = &afe->memif[i];
411 if (memif_tmp->substream)
412 return -EBUSY;
413 }
414
415
416 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
417 memif_data = afe->memif[i].data;
418 regmap_update_bits(afe->regmap,
419 memif_data->agent_disable_reg,
420 1 << memif_data->agent_disable_shift,
421 0 << memif_data->agent_disable_shift);
422 }
423
424 return mtk_afe_fe_startup(substream, dai);
425 }
426
427 static void mt2701_dlm_fe_shutdown(struct snd_pcm_substream *substream,
428 struct snd_soc_dai *dai)
429 {
430 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
431 const struct mtk_base_memif_data *memif_data;
432 int i;
433
434 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
435 memif_data = afe->memif[i].data;
436 regmap_update_bits(afe->regmap,
437 memif_data->agent_disable_reg,
438 1 << memif_data->agent_disable_shift,
439 1 << memif_data->agent_disable_shift);
440 }
441
442 return mtk_afe_fe_shutdown(substream, dai);
443 }
444
445 static int mt2701_dlm_fe_hw_params(struct snd_pcm_substream *substream,
446 struct snd_pcm_hw_params *params,
447 struct snd_soc_dai *dai)
448 {
449 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
450 int channels = params_channels(params);
451
452 regmap_update_bits(afe->regmap,
453 AFE_MEMIF_PBUF_SIZE,
454 AFE_MEMIF_PBUF_SIZE_DLM_MASK,
455 AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE);
456 regmap_update_bits(afe->regmap,
457 AFE_MEMIF_PBUF_SIZE,
458 AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK,
459 AFE_MEMIF_PBUF_SIZE_DLM_32BYTES);
460 regmap_update_bits(afe->regmap,
461 AFE_MEMIF_PBUF_SIZE,
462 AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK,
463 AFE_MEMIF_PBUF_SIZE_DLM_CH(channels));
464
465 return mtk_afe_fe_hw_params(substream, params, dai);
466 }
467
468 static int mt2701_dlm_fe_trigger(struct snd_pcm_substream *substream,
469 int cmd, struct snd_soc_dai *dai)
470 {
471 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
472 struct mtk_base_afe_memif *memif_tmp = &afe->memif[MT2701_MEMIF_DL1];
473
474 switch (cmd) {
475 case SNDRV_PCM_TRIGGER_START:
476 case SNDRV_PCM_TRIGGER_RESUME:
477 regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
478 1 << memif_tmp->data->enable_shift,
479 1 << memif_tmp->data->enable_shift);
480 mtk_afe_fe_trigger(substream, cmd, dai);
481 return 0;
482 case SNDRV_PCM_TRIGGER_STOP:
483 case SNDRV_PCM_TRIGGER_SUSPEND:
484 mtk_afe_fe_trigger(substream, cmd, dai);
485 regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
486 1 << memif_tmp->data->enable_shift, 0);
487
488 return 0;
489 default:
490 return -EINVAL;
491 }
492 }
493
494 static int mt2701_memif_fs(struct snd_pcm_substream *substream,
495 unsigned int rate)
496 {
497 struct snd_soc_pcm_runtime *rtd = substream->private_data;
498 int fs;
499
500 if (rtd->cpu_dai->id != MT2701_MEMIF_ULBT)
501 fs = mt2701_afe_i2s_fs(rate);
502 else
503 fs = (rate == 16000 ? 1 : 0);
504
505 return fs;
506 }
507
508 static int mt2701_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
509 {
510 return mt2701_afe_i2s_fs(rate);
511 }
512
513
514 static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = {
515 .startup = mt2701_simple_fe_startup,
516 .shutdown = mtk_afe_fe_shutdown,
517 .hw_params = mt2701_simple_fe_hw_params,
518 .hw_free = mtk_afe_fe_hw_free,
519 .prepare = mtk_afe_fe_prepare,
520 .trigger = mtk_afe_fe_trigger,
521 };
522
523 static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
524 .startup = mt2701_dlm_fe_startup,
525 .shutdown = mt2701_dlm_fe_shutdown,
526 .hw_params = mt2701_dlm_fe_hw_params,
527 .hw_free = mtk_afe_fe_hw_free,
528 .prepare = mtk_afe_fe_prepare,
529 .trigger = mt2701_dlm_fe_trigger,
530 };
531
532
533 static const struct snd_soc_dai_ops mt2701_afe_i2s_ops = {
534 .startup = mt2701_afe_i2s_startup,
535 .shutdown = mt2701_afe_i2s_shutdown,
536 .prepare = mt2701_afe_i2s_prepare,
537 .set_sysclk = mt2701_afe_i2s_set_sysclk,
538 };
539
540
541 static const struct snd_soc_dai_ops mt2701_btmrg_ops = {
542 .startup = mt2701_btmrg_startup,
543 .shutdown = mt2701_btmrg_shutdown,
544 .hw_params = mt2701_btmrg_hw_params,
545 };
546
547 static struct snd_soc_dai_driver mt2701_afe_pcm_dais[] = {
548
549 {
550 .name = "PCMO0",
551 .id = MT2701_MEMIF_DL1,
552 .suspend = mtk_afe_dai_suspend,
553 .resume = mtk_afe_dai_resume,
554 .playback = {
555 .stream_name = "DL1",
556 .channels_min = 1,
557 .channels_max = 2,
558 .rates = SNDRV_PCM_RATE_8000_192000,
559 .formats = (SNDRV_PCM_FMTBIT_S16_LE
560 | SNDRV_PCM_FMTBIT_S24_LE
561 | SNDRV_PCM_FMTBIT_S32_LE)
562 },
563 .ops = &mt2701_single_memif_dai_ops,
564 },
565 {
566 .name = "PCM_multi",
567 .id = MT2701_MEMIF_DLM,
568 .suspend = mtk_afe_dai_suspend,
569 .resume = mtk_afe_dai_resume,
570 .playback = {
571 .stream_name = "DLM",
572 .channels_min = 1,
573 .channels_max = 8,
574 .rates = SNDRV_PCM_RATE_8000_192000,
575 .formats = (SNDRV_PCM_FMTBIT_S16_LE
576 | SNDRV_PCM_FMTBIT_S24_LE
577 | SNDRV_PCM_FMTBIT_S32_LE)
578
579 },
580 .ops = &mt2701_dlm_memif_dai_ops,
581 },
582 {
583 .name = "PCM0",
584 .id = MT2701_MEMIF_UL1,
585 .suspend = mtk_afe_dai_suspend,
586 .resume = mtk_afe_dai_resume,
587 .capture = {
588 .stream_name = "UL1",
589 .channels_min = 1,
590 .channels_max = 2,
591 .rates = SNDRV_PCM_RATE_8000_48000,
592 .formats = (SNDRV_PCM_FMTBIT_S16_LE
593 | SNDRV_PCM_FMTBIT_S24_LE
594 | SNDRV_PCM_FMTBIT_S32_LE)
595 },
596 .ops = &mt2701_single_memif_dai_ops,
597 },
598 {
599 .name = "PCM1",
600 .id = MT2701_MEMIF_UL2,
601 .suspend = mtk_afe_dai_suspend,
602 .resume = mtk_afe_dai_resume,
603 .capture = {
604 .stream_name = "UL2",
605 .channels_min = 1,
606 .channels_max = 2,
607 .rates = SNDRV_PCM_RATE_8000_192000,
608 .formats = (SNDRV_PCM_FMTBIT_S16_LE
609 | SNDRV_PCM_FMTBIT_S24_LE
610 | SNDRV_PCM_FMTBIT_S32_LE)
611
612 },
613 .ops = &mt2701_single_memif_dai_ops,
614 },
615 {
616 .name = "PCM_BT_DL",
617 .id = MT2701_MEMIF_DLBT,
618 .suspend = mtk_afe_dai_suspend,
619 .resume = mtk_afe_dai_resume,
620 .playback = {
621 .stream_name = "DLBT",
622 .channels_min = 1,
623 .channels_max = 1,
624 .rates = (SNDRV_PCM_RATE_8000
625 | SNDRV_PCM_RATE_16000),
626 .formats = SNDRV_PCM_FMTBIT_S16_LE,
627 },
628 .ops = &mt2701_single_memif_dai_ops,
629 },
630 {
631 .name = "PCM_BT_UL",
632 .id = MT2701_MEMIF_ULBT,
633 .suspend = mtk_afe_dai_suspend,
634 .resume = mtk_afe_dai_resume,
635 .capture = {
636 .stream_name = "ULBT",
637 .channels_min = 1,
638 .channels_max = 1,
639 .rates = (SNDRV_PCM_RATE_8000
640 | SNDRV_PCM_RATE_16000),
641 .formats = SNDRV_PCM_FMTBIT_S16_LE,
642 },
643 .ops = &mt2701_single_memif_dai_ops,
644 },
645
646 {
647 .name = "I2S0",
648 .id = MT2701_IO_I2S,
649 .playback = {
650 .stream_name = "I2S0 Playback",
651 .channels_min = 1,
652 .channels_max = 2,
653 .rates = SNDRV_PCM_RATE_8000_192000,
654 .formats = (SNDRV_PCM_FMTBIT_S16_LE
655 | SNDRV_PCM_FMTBIT_S24_LE
656 | SNDRV_PCM_FMTBIT_S32_LE)
657
658 },
659 .capture = {
660 .stream_name = "I2S0 Capture",
661 .channels_min = 1,
662 .channels_max = 2,
663 .rates = SNDRV_PCM_RATE_8000_192000,
664 .formats = (SNDRV_PCM_FMTBIT_S16_LE
665 | SNDRV_PCM_FMTBIT_S24_LE
666 | SNDRV_PCM_FMTBIT_S32_LE)
667
668 },
669 .ops = &mt2701_afe_i2s_ops,
670 .symmetric_rates = 1,
671 },
672 {
673 .name = "I2S1",
674 .id = MT2701_IO_2ND_I2S,
675 .playback = {
676 .stream_name = "I2S1 Playback",
677 .channels_min = 1,
678 .channels_max = 2,
679 .rates = SNDRV_PCM_RATE_8000_192000,
680 .formats = (SNDRV_PCM_FMTBIT_S16_LE
681 | SNDRV_PCM_FMTBIT_S24_LE
682 | SNDRV_PCM_FMTBIT_S32_LE)
683 },
684 .capture = {
685 .stream_name = "I2S1 Capture",
686 .channels_min = 1,
687 .channels_max = 2,
688 .rates = SNDRV_PCM_RATE_8000_192000,
689 .formats = (SNDRV_PCM_FMTBIT_S16_LE
690 | SNDRV_PCM_FMTBIT_S24_LE
691 | SNDRV_PCM_FMTBIT_S32_LE)
692 },
693 .ops = &mt2701_afe_i2s_ops,
694 .symmetric_rates = 1,
695 },
696 {
697 .name = "I2S2",
698 .id = MT2701_IO_3RD_I2S,
699 .playback = {
700 .stream_name = "I2S2 Playback",
701 .channels_min = 1,
702 .channels_max = 2,
703 .rates = SNDRV_PCM_RATE_8000_192000,
704 .formats = (SNDRV_PCM_FMTBIT_S16_LE
705 | SNDRV_PCM_FMTBIT_S24_LE
706 | SNDRV_PCM_FMTBIT_S32_LE)
707 },
708 .capture = {
709 .stream_name = "I2S2 Capture",
710 .channels_min = 1,
711 .channels_max = 2,
712 .rates = SNDRV_PCM_RATE_8000_192000,
713 .formats = (SNDRV_PCM_FMTBIT_S16_LE
714 | SNDRV_PCM_FMTBIT_S24_LE
715 | SNDRV_PCM_FMTBIT_S32_LE)
716 },
717 .ops = &mt2701_afe_i2s_ops,
718 .symmetric_rates = 1,
719 },
720 {
721 .name = "I2S3",
722 .id = MT2701_IO_4TH_I2S,
723 .playback = {
724 .stream_name = "I2S3 Playback",
725 .channels_min = 1,
726 .channels_max = 2,
727 .rates = SNDRV_PCM_RATE_8000_192000,
728 .formats = (SNDRV_PCM_FMTBIT_S16_LE
729 | SNDRV_PCM_FMTBIT_S24_LE
730 | SNDRV_PCM_FMTBIT_S32_LE)
731 },
732 .capture = {
733 .stream_name = "I2S3 Capture",
734 .channels_min = 1,
735 .channels_max = 2,
736 .rates = SNDRV_PCM_RATE_8000_192000,
737 .formats = (SNDRV_PCM_FMTBIT_S16_LE
738 | SNDRV_PCM_FMTBIT_S24_LE
739 | SNDRV_PCM_FMTBIT_S32_LE)
740 },
741 .ops = &mt2701_afe_i2s_ops,
742 .symmetric_rates = 1,
743 },
744 {
745 .name = "MRG BT",
746 .id = MT2701_IO_MRG,
747 .playback = {
748 .stream_name = "BT Playback",
749 .channels_min = 1,
750 .channels_max = 1,
751 .rates = (SNDRV_PCM_RATE_8000
752 | SNDRV_PCM_RATE_16000),
753 .formats = SNDRV_PCM_FMTBIT_S16_LE,
754 },
755 .capture = {
756 .stream_name = "BT Capture",
757 .channels_min = 1,
758 .channels_max = 1,
759 .rates = (SNDRV_PCM_RATE_8000
760 | SNDRV_PCM_RATE_16000),
761 .formats = SNDRV_PCM_FMTBIT_S16_LE,
762 },
763 .ops = &mt2701_btmrg_ops,
764 .symmetric_rates = 1,
765 }
766 };
767
768 static const struct snd_kcontrol_new mt2701_afe_o00_mix[] = {
769 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN0, 0, 1, 0),
770 };
771
772 static const struct snd_kcontrol_new mt2701_afe_o01_mix[] = {
773 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN1, 1, 1, 0),
774 };
775
776 static const struct snd_kcontrol_new mt2701_afe_o02_mix[] = {
777 SOC_DAPM_SINGLE_AUTODISABLE("I02 Switch", AFE_CONN2, 2, 1, 0),
778 };
779
780 static const struct snd_kcontrol_new mt2701_afe_o03_mix[] = {
781 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 3, 1, 0),
782 };
783
784 static const struct snd_kcontrol_new mt2701_afe_o14_mix[] = {
785 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN14, 26, 1, 0),
786 };
787
788 static const struct snd_kcontrol_new mt2701_afe_o15_mix[] = {
789 SOC_DAPM_SINGLE_AUTODISABLE("I12 Switch", AFE_CONN15, 12, 1, 0),
790 };
791
792 static const struct snd_kcontrol_new mt2701_afe_o16_mix[] = {
793 SOC_DAPM_SINGLE_AUTODISABLE("I13 Switch", AFE_CONN16, 13, 1, 0),
794 };
795
796 static const struct snd_kcontrol_new mt2701_afe_o17_mix[] = {
797 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN17, 14, 1, 0),
798 };
799
800 static const struct snd_kcontrol_new mt2701_afe_o18_mix[] = {
801 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN18, 15, 1, 0),
802 };
803
804 static const struct snd_kcontrol_new mt2701_afe_o19_mix[] = {
805 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN19, 16, 1, 0),
806 };
807
808 static const struct snd_kcontrol_new mt2701_afe_o20_mix[] = {
809 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN20, 17, 1, 0),
810 };
811
812 static const struct snd_kcontrol_new mt2701_afe_o21_mix[] = {
813 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN21, 18, 1, 0),
814 };
815
816 static const struct snd_kcontrol_new mt2701_afe_o22_mix[] = {
817 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN22, 19, 1, 0),
818 };
819
820 static const struct snd_kcontrol_new mt2701_afe_o31_mix[] = {
821 SOC_DAPM_SINGLE_AUTODISABLE("I35 Switch", AFE_CONN41, 9, 1, 0),
822 };
823
824 static const struct snd_kcontrol_new mt2701_afe_i02_mix[] = {
825 SOC_DAPM_SINGLE("I2S0 Switch", SND_SOC_NOPM, 0, 1, 0),
826 };
827
828 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s0[] = {
829 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S0 Out Switch",
830 ASYS_I2SO1_CON, 26, 1, 0),
831 };
832
833 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s1[] = {
834 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S1 Out Switch",
835 ASYS_I2SO2_CON, 26, 1, 0),
836 };
837
838 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s2[] = {
839 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S2 Out Switch",
840 PWR2_TOP_CON, 17, 1, 0),
841 };
842
843 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s3[] = {
844 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S3 Out Switch",
845 PWR2_TOP_CON, 18, 1, 0),
846 };
847
848 static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
849
850 SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
851 SND_SOC_DAPM_MIXER("I01", SND_SOC_NOPM, 0, 0, NULL, 0),
852 SND_SOC_DAPM_MIXER("I02", SND_SOC_NOPM, 0, 0, mt2701_afe_i02_mix,
853 ARRAY_SIZE(mt2701_afe_i02_mix)),
854 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
855 SND_SOC_DAPM_MIXER("I12", SND_SOC_NOPM, 0, 0, NULL, 0),
856 SND_SOC_DAPM_MIXER("I13", SND_SOC_NOPM, 0, 0, NULL, 0),
857 SND_SOC_DAPM_MIXER("I14", SND_SOC_NOPM, 0, 0, NULL, 0),
858 SND_SOC_DAPM_MIXER("I15", SND_SOC_NOPM, 0, 0, NULL, 0),
859 SND_SOC_DAPM_MIXER("I16", SND_SOC_NOPM, 0, 0, NULL, 0),
860 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
861 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
862 SND_SOC_DAPM_MIXER("I19", SND_SOC_NOPM, 0, 0, NULL, 0),
863 SND_SOC_DAPM_MIXER("I26", SND_SOC_NOPM, 0, 0, NULL, 0),
864 SND_SOC_DAPM_MIXER("I35", SND_SOC_NOPM, 0, 0, NULL, 0),
865
866 SND_SOC_DAPM_MIXER("O00", SND_SOC_NOPM, 0, 0, mt2701_afe_o00_mix,
867 ARRAY_SIZE(mt2701_afe_o00_mix)),
868 SND_SOC_DAPM_MIXER("O01", SND_SOC_NOPM, 0, 0, mt2701_afe_o01_mix,
869 ARRAY_SIZE(mt2701_afe_o01_mix)),
870 SND_SOC_DAPM_MIXER("O02", SND_SOC_NOPM, 0, 0, mt2701_afe_o02_mix,
871 ARRAY_SIZE(mt2701_afe_o02_mix)),
872 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, mt2701_afe_o03_mix,
873 ARRAY_SIZE(mt2701_afe_o03_mix)),
874 SND_SOC_DAPM_MIXER("O14", SND_SOC_NOPM, 0, 0, mt2701_afe_o14_mix,
875 ARRAY_SIZE(mt2701_afe_o14_mix)),
876 SND_SOC_DAPM_MIXER("O15", SND_SOC_NOPM, 0, 0, mt2701_afe_o15_mix,
877 ARRAY_SIZE(mt2701_afe_o15_mix)),
878 SND_SOC_DAPM_MIXER("O16", SND_SOC_NOPM, 0, 0, mt2701_afe_o16_mix,
879 ARRAY_SIZE(mt2701_afe_o16_mix)),
880 SND_SOC_DAPM_MIXER("O17", SND_SOC_NOPM, 0, 0, mt2701_afe_o17_mix,
881 ARRAY_SIZE(mt2701_afe_o17_mix)),
882 SND_SOC_DAPM_MIXER("O18", SND_SOC_NOPM, 0, 0, mt2701_afe_o18_mix,
883 ARRAY_SIZE(mt2701_afe_o18_mix)),
884 SND_SOC_DAPM_MIXER("O19", SND_SOC_NOPM, 0, 0, mt2701_afe_o19_mix,
885 ARRAY_SIZE(mt2701_afe_o19_mix)),
886 SND_SOC_DAPM_MIXER("O20", SND_SOC_NOPM, 0, 0, mt2701_afe_o20_mix,
887 ARRAY_SIZE(mt2701_afe_o20_mix)),
888 SND_SOC_DAPM_MIXER("O21", SND_SOC_NOPM, 0, 0, mt2701_afe_o21_mix,
889 ARRAY_SIZE(mt2701_afe_o21_mix)),
890 SND_SOC_DAPM_MIXER("O22", SND_SOC_NOPM, 0, 0, mt2701_afe_o22_mix,
891 ARRAY_SIZE(mt2701_afe_o22_mix)),
892 SND_SOC_DAPM_MIXER("O31", SND_SOC_NOPM, 0, 0, mt2701_afe_o31_mix,
893 ARRAY_SIZE(mt2701_afe_o31_mix)),
894
895 SND_SOC_DAPM_MIXER("I12I13", SND_SOC_NOPM, 0, 0,
896 mt2701_afe_multi_ch_out_i2s0,
897 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s0)),
898 SND_SOC_DAPM_MIXER("I14I15", SND_SOC_NOPM, 0, 0,
899 mt2701_afe_multi_ch_out_i2s1,
900 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s1)),
901 SND_SOC_DAPM_MIXER("I16I17", SND_SOC_NOPM, 0, 0,
902 mt2701_afe_multi_ch_out_i2s2,
903 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s2)),
904 SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
905 mt2701_afe_multi_ch_out_i2s3,
906 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
907 };
908
909 static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
910 {"I12", NULL, "DL1"},
911 {"I13", NULL, "DL1"},
912 {"I35", NULL, "DLBT"},
913
914 {"I2S0 Playback", NULL, "O15"},
915 {"I2S0 Playback", NULL, "O16"},
916 {"I2S1 Playback", NULL, "O17"},
917 {"I2S1 Playback", NULL, "O18"},
918 {"I2S2 Playback", NULL, "O19"},
919 {"I2S2 Playback", NULL, "O20"},
920 {"I2S3 Playback", NULL, "O21"},
921 {"I2S3 Playback", NULL, "O22"},
922 {"BT Playback", NULL, "O31"},
923
924 {"UL1", NULL, "O00"},
925 {"UL1", NULL, "O01"},
926 {"UL2", NULL, "O02"},
927 {"UL2", NULL, "O03"},
928 {"ULBT", NULL, "O14"},
929
930 {"I00", NULL, "I2S0 Capture"},
931 {"I01", NULL, "I2S0 Capture"},
932 {"I02", NULL, "I2S1 Capture"},
933 {"I03", NULL, "I2S1 Capture"},
934
935 {"I02", "I2S0 Switch", "I2S0 Capture"},
936
937 {"I26", NULL, "BT Capture"},
938
939 {"I12I13", "Multich I2S0 Out Switch", "DLM"},
940 {"I14I15", "Multich I2S1 Out Switch", "DLM"},
941 {"I16I17", "Multich I2S2 Out Switch", "DLM"},
942 {"I18I19", "Multich I2S3 Out Switch", "DLM"},
943
944 { "I12", NULL, "I12I13" },
945 { "I13", NULL, "I12I13" },
946 { "I14", NULL, "I14I15" },
947 { "I15", NULL, "I14I15" },
948 { "I16", NULL, "I16I17" },
949 { "I17", NULL, "I16I17" },
950 { "I18", NULL, "I18I19" },
951 { "I19", NULL, "I18I19" },
952
953 { "O00", "I00 Switch", "I00" },
954 { "O01", "I01 Switch", "I01" },
955 { "O02", "I02 Switch", "I02" },
956 { "O03", "I03 Switch", "I03" },
957 { "O14", "I26 Switch", "I26" },
958 { "O15", "I12 Switch", "I12" },
959 { "O16", "I13 Switch", "I13" },
960 { "O17", "I14 Switch", "I14" },
961 { "O18", "I15 Switch", "I15" },
962 { "O19", "I16 Switch", "I16" },
963 { "O20", "I17 Switch", "I17" },
964 { "O21", "I18 Switch", "I18" },
965 { "O22", "I19 Switch", "I19" },
966 { "O31", "I35 Switch", "I35" },
967 };
968
969 static int mt2701_afe_pcm_probe(struct snd_soc_component *component)
970 {
971 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
972
973 snd_soc_component_init_regmap(component, afe->regmap);
974
975 return 0;
976 }
977
978 static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
979 .probe = mt2701_afe_pcm_probe,
980 .name = "mt2701-afe-pcm-dai",
981 .dapm_widgets = mt2701_afe_pcm_widgets,
982 .num_dapm_widgets = ARRAY_SIZE(mt2701_afe_pcm_widgets),
983 .dapm_routes = mt2701_afe_pcm_routes,
984 .num_dapm_routes = ARRAY_SIZE(mt2701_afe_pcm_routes),
985 };
986
987 static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
988 {
989 .name = "DL1",
990 .id = MT2701_MEMIF_DL1,
991 .reg_ofs_base = AFE_DL1_BASE,
992 .reg_ofs_cur = AFE_DL1_CUR,
993 .fs_reg = AFE_DAC_CON1,
994 .fs_shift = 0,
995 .fs_maskbit = 0x1f,
996 .mono_reg = AFE_DAC_CON3,
997 .mono_shift = 16,
998 .enable_reg = AFE_DAC_CON0,
999 .enable_shift = 1,
1000 .hd_reg = AFE_MEMIF_HD_CON0,
1001 .hd_shift = 0,
1002 .agent_disable_reg = AUDIO_TOP_CON5,
1003 .agent_disable_shift = 6,
1004 .msb_reg = -1,
1005 },
1006 {
1007 .name = "DL2",
1008 .id = MT2701_MEMIF_DL2,
1009 .reg_ofs_base = AFE_DL2_BASE,
1010 .reg_ofs_cur = AFE_DL2_CUR,
1011 .fs_reg = AFE_DAC_CON1,
1012 .fs_shift = 5,
1013 .fs_maskbit = 0x1f,
1014 .mono_reg = AFE_DAC_CON3,
1015 .mono_shift = 17,
1016 .enable_reg = AFE_DAC_CON0,
1017 .enable_shift = 2,
1018 .hd_reg = AFE_MEMIF_HD_CON0,
1019 .hd_shift = 2,
1020 .agent_disable_reg = AUDIO_TOP_CON5,
1021 .agent_disable_shift = 7,
1022 .msb_reg = -1,
1023 },
1024 {
1025 .name = "DL3",
1026 .id = MT2701_MEMIF_DL3,
1027 .reg_ofs_base = AFE_DL3_BASE,
1028 .reg_ofs_cur = AFE_DL3_CUR,
1029 .fs_reg = AFE_DAC_CON1,
1030 .fs_shift = 10,
1031 .fs_maskbit = 0x1f,
1032 .mono_reg = AFE_DAC_CON3,
1033 .mono_shift = 18,
1034 .enable_reg = AFE_DAC_CON0,
1035 .enable_shift = 3,
1036 .hd_reg = AFE_MEMIF_HD_CON0,
1037 .hd_shift = 4,
1038 .agent_disable_reg = AUDIO_TOP_CON5,
1039 .agent_disable_shift = 8,
1040 .msb_reg = -1,
1041 },
1042 {
1043 .name = "DL4",
1044 .id = MT2701_MEMIF_DL4,
1045 .reg_ofs_base = AFE_DL4_BASE,
1046 .reg_ofs_cur = AFE_DL4_CUR,
1047 .fs_reg = AFE_DAC_CON1,
1048 .fs_shift = 15,
1049 .fs_maskbit = 0x1f,
1050 .mono_reg = AFE_DAC_CON3,
1051 .mono_shift = 19,
1052 .enable_reg = AFE_DAC_CON0,
1053 .enable_shift = 4,
1054 .hd_reg = AFE_MEMIF_HD_CON0,
1055 .hd_shift = 6,
1056 .agent_disable_reg = AUDIO_TOP_CON5,
1057 .agent_disable_shift = 9,
1058 .msb_reg = -1,
1059 },
1060 {
1061 .name = "DL5",
1062 .id = MT2701_MEMIF_DL5,
1063 .reg_ofs_base = AFE_DL5_BASE,
1064 .reg_ofs_cur = AFE_DL5_CUR,
1065 .fs_reg = AFE_DAC_CON1,
1066 .fs_shift = 20,
1067 .fs_maskbit = 0x1f,
1068 .mono_reg = AFE_DAC_CON3,
1069 .mono_shift = 20,
1070 .enable_reg = AFE_DAC_CON0,
1071 .enable_shift = 5,
1072 .hd_reg = AFE_MEMIF_HD_CON0,
1073 .hd_shift = 8,
1074 .agent_disable_reg = AUDIO_TOP_CON5,
1075 .agent_disable_shift = 10,
1076 .msb_reg = -1,
1077 },
1078 {
1079 .name = "DLM",
1080 .id = MT2701_MEMIF_DLM,
1081 .reg_ofs_base = AFE_DLMCH_BASE,
1082 .reg_ofs_cur = AFE_DLMCH_CUR,
1083 .fs_reg = AFE_DAC_CON1,
1084 .fs_shift = 0,
1085 .fs_maskbit = 0x1f,
1086 .mono_reg = -1,
1087 .mono_shift = -1,
1088 .enable_reg = AFE_DAC_CON0,
1089 .enable_shift = 7,
1090 .hd_reg = AFE_MEMIF_PBUF_SIZE,
1091 .hd_shift = 28,
1092 .agent_disable_reg = AUDIO_TOP_CON5,
1093 .agent_disable_shift = 12,
1094 .msb_reg = -1,
1095 },
1096 {
1097 .name = "UL1",
1098 .id = MT2701_MEMIF_UL1,
1099 .reg_ofs_base = AFE_VUL_BASE,
1100 .reg_ofs_cur = AFE_VUL_CUR,
1101 .fs_reg = AFE_DAC_CON2,
1102 .fs_shift = 0,
1103 .fs_maskbit = 0x1f,
1104 .mono_reg = AFE_DAC_CON4,
1105 .mono_shift = 0,
1106 .enable_reg = AFE_DAC_CON0,
1107 .enable_shift = 10,
1108 .hd_reg = AFE_MEMIF_HD_CON1,
1109 .hd_shift = 0,
1110 .agent_disable_reg = AUDIO_TOP_CON5,
1111 .agent_disable_shift = 0,
1112 .msb_reg = -1,
1113 },
1114 {
1115 .name = "UL2",
1116 .id = MT2701_MEMIF_UL2,
1117 .reg_ofs_base = AFE_UL2_BASE,
1118 .reg_ofs_cur = AFE_UL2_CUR,
1119 .fs_reg = AFE_DAC_CON2,
1120 .fs_shift = 5,
1121 .fs_maskbit = 0x1f,
1122 .mono_reg = AFE_DAC_CON4,
1123 .mono_shift = 2,
1124 .enable_reg = AFE_DAC_CON0,
1125 .enable_shift = 11,
1126 .hd_reg = AFE_MEMIF_HD_CON1,
1127 .hd_shift = 2,
1128 .agent_disable_reg = AUDIO_TOP_CON5,
1129 .agent_disable_shift = 1,
1130 .msb_reg = -1,
1131 },
1132 {
1133 .name = "UL3",
1134 .id = MT2701_MEMIF_UL3,
1135 .reg_ofs_base = AFE_UL3_BASE,
1136 .reg_ofs_cur = AFE_UL3_CUR,
1137 .fs_reg = AFE_DAC_CON2,
1138 .fs_shift = 10,
1139 .fs_maskbit = 0x1f,
1140 .mono_reg = AFE_DAC_CON4,
1141 .mono_shift = 4,
1142 .enable_reg = AFE_DAC_CON0,
1143 .enable_shift = 12,
1144 .hd_reg = AFE_MEMIF_HD_CON0,
1145 .hd_shift = 0,
1146 .agent_disable_reg = AUDIO_TOP_CON5,
1147 .agent_disable_shift = 2,
1148 .msb_reg = -1,
1149 },
1150 {
1151 .name = "UL4",
1152 .id = MT2701_MEMIF_UL4,
1153 .reg_ofs_base = AFE_UL4_BASE,
1154 .reg_ofs_cur = AFE_UL4_CUR,
1155 .fs_reg = AFE_DAC_CON2,
1156 .fs_shift = 15,
1157 .fs_maskbit = 0x1f,
1158 .mono_reg = AFE_DAC_CON4,
1159 .mono_shift = 6,
1160 .enable_reg = AFE_DAC_CON0,
1161 .enable_shift = 13,
1162 .hd_reg = AFE_MEMIF_HD_CON0,
1163 .hd_shift = 6,
1164 .agent_disable_reg = AUDIO_TOP_CON5,
1165 .agent_disable_shift = 3,
1166 .msb_reg = -1,
1167 },
1168 {
1169 .name = "UL5",
1170 .id = MT2701_MEMIF_UL5,
1171 .reg_ofs_base = AFE_UL5_BASE,
1172 .reg_ofs_cur = AFE_UL5_CUR,
1173 .fs_reg = AFE_DAC_CON2,
1174 .fs_shift = 20,
1175 .mono_reg = AFE_DAC_CON4,
1176 .mono_shift = 8,
1177 .fs_maskbit = 0x1f,
1178 .enable_reg = AFE_DAC_CON0,
1179 .enable_shift = 14,
1180 .hd_reg = AFE_MEMIF_HD_CON0,
1181 .hd_shift = 8,
1182 .agent_disable_reg = AUDIO_TOP_CON5,
1183 .agent_disable_shift = 4,
1184 .msb_reg = -1,
1185 },
1186 {
1187 .name = "DLBT",
1188 .id = MT2701_MEMIF_DLBT,
1189 .reg_ofs_base = AFE_ARB1_BASE,
1190 .reg_ofs_cur = AFE_ARB1_CUR,
1191 .fs_reg = AFE_DAC_CON3,
1192 .fs_shift = 10,
1193 .fs_maskbit = 0x1f,
1194 .mono_reg = AFE_DAC_CON3,
1195 .mono_shift = 22,
1196 .enable_reg = AFE_DAC_CON0,
1197 .enable_shift = 8,
1198 .hd_reg = AFE_MEMIF_HD_CON0,
1199 .hd_shift = 14,
1200 .agent_disable_reg = AUDIO_TOP_CON5,
1201 .agent_disable_shift = 13,
1202 .msb_reg = -1,
1203 },
1204 {
1205 .name = "ULBT",
1206 .id = MT2701_MEMIF_ULBT,
1207 .reg_ofs_base = AFE_DAI_BASE,
1208 .reg_ofs_cur = AFE_DAI_CUR,
1209 .fs_reg = AFE_DAC_CON2,
1210 .fs_shift = 30,
1211 .fs_maskbit = 0x1,
1212 .mono_reg = -1,
1213 .mono_shift = -1,
1214 .enable_reg = AFE_DAC_CON0,
1215 .enable_shift = 17,
1216 .hd_reg = AFE_MEMIF_HD_CON1,
1217 .hd_shift = 20,
1218 .agent_disable_reg = AUDIO_TOP_CON5,
1219 .agent_disable_shift = 16,
1220 .msb_reg = -1,
1221 },
1222 };
1223
1224 static const struct mtk_base_irq_data irq_data[MT2701_IRQ_ASYS_END] = {
1225 {
1226 .id = MT2701_IRQ_ASYS_IRQ1,
1227 .irq_cnt_reg = ASYS_IRQ1_CON,
1228 .irq_cnt_shift = 0,
1229 .irq_cnt_maskbit = 0xffffff,
1230 .irq_fs_reg = ASYS_IRQ1_CON,
1231 .irq_fs_shift = 24,
1232 .irq_fs_maskbit = 0x1f,
1233 .irq_en_reg = ASYS_IRQ1_CON,
1234 .irq_en_shift = 31,
1235 .irq_clr_reg = ASYS_IRQ_CLR,
1236 .irq_clr_shift = 0,
1237 },
1238 {
1239 .id = MT2701_IRQ_ASYS_IRQ2,
1240 .irq_cnt_reg = ASYS_IRQ2_CON,
1241 .irq_cnt_shift = 0,
1242 .irq_cnt_maskbit = 0xffffff,
1243 .irq_fs_reg = ASYS_IRQ2_CON,
1244 .irq_fs_shift = 24,
1245 .irq_fs_maskbit = 0x1f,
1246 .irq_en_reg = ASYS_IRQ2_CON,
1247 .irq_en_shift = 31,
1248 .irq_clr_reg = ASYS_IRQ_CLR,
1249 .irq_clr_shift = 1,
1250 },
1251 {
1252 .id = MT2701_IRQ_ASYS_IRQ3,
1253 .irq_cnt_reg = ASYS_IRQ3_CON,
1254 .irq_cnt_shift = 0,
1255 .irq_cnt_maskbit = 0xffffff,
1256 .irq_fs_reg = ASYS_IRQ3_CON,
1257 .irq_fs_shift = 24,
1258 .irq_fs_maskbit = 0x1f,
1259 .irq_en_reg = ASYS_IRQ3_CON,
1260 .irq_en_shift = 31,
1261 .irq_clr_reg = ASYS_IRQ_CLR,
1262 .irq_clr_shift = 2,
1263 }
1264 };
1265
1266 static const struct mt2701_i2s_data mt2701_i2s_data[][2] = {
1267 {
1268 { ASYS_I2SO1_CON, 0, 0x1f },
1269 { ASYS_I2SIN1_CON, 0, 0x1f },
1270 },
1271 {
1272 { ASYS_I2SO2_CON, 5, 0x1f },
1273 { ASYS_I2SIN2_CON, 5, 0x1f },
1274 },
1275 {
1276 { ASYS_I2SO3_CON, 10, 0x1f },
1277 { ASYS_I2SIN3_CON, 10, 0x1f },
1278 },
1279 {
1280 { ASYS_I2SO4_CON, 15, 0x1f },
1281 { ASYS_I2SIN4_CON, 15, 0x1f },
1282 },
1283
1284 };
1285
1286 static irqreturn_t mt2701_asys_isr(int irq_id, void *dev)
1287 {
1288 int id;
1289 struct mtk_base_afe *afe = dev;
1290 struct mtk_base_afe_memif *memif;
1291 struct mtk_base_afe_irq *irq;
1292 u32 status;
1293
1294 regmap_read(afe->regmap, ASYS_IRQ_STATUS, &status);
1295 regmap_write(afe->regmap, ASYS_IRQ_CLR, status);
1296
1297 for (id = 0; id < MT2701_MEMIF_NUM; ++id) {
1298 memif = &afe->memif[id];
1299 if (memif->irq_usage < 0)
1300 continue;
1301
1302 irq = &afe->irqs[memif->irq_usage];
1303 if (status & 1 << irq->irq_data->irq_clr_shift)
1304 snd_pcm_period_elapsed(memif->substream);
1305 }
1306
1307 return IRQ_HANDLED;
1308 }
1309
1310 static int mt2701_afe_runtime_suspend(struct device *dev)
1311 {
1312 struct mtk_base_afe *afe = dev_get_drvdata(dev);
1313
1314 return mt2701_afe_disable_clock(afe);
1315 }
1316
1317 static int mt2701_afe_runtime_resume(struct device *dev)
1318 {
1319 struct mtk_base_afe *afe = dev_get_drvdata(dev);
1320
1321 return mt2701_afe_enable_clock(afe);
1322 }
1323
1324 static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
1325 {
1326 struct mtk_base_afe *afe;
1327 struct mt2701_afe_private *afe_priv;
1328 struct device *dev;
1329 int i, irq_id, ret;
1330
1331 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1332 if (!afe)
1333 return -ENOMEM;
1334
1335 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1336 GFP_KERNEL);
1337 if (!afe->platform_priv)
1338 return -ENOMEM;
1339
1340 afe_priv = afe->platform_priv;
1341 afe_priv->soc = of_device_get_match_data(&pdev->dev);
1342 afe->dev = &pdev->dev;
1343 dev = afe->dev;
1344
1345 afe_priv->i2s_path = devm_kcalloc(dev,
1346 afe_priv->soc->i2s_num,
1347 sizeof(struct mt2701_i2s_path),
1348 GFP_KERNEL);
1349 if (!afe_priv->i2s_path)
1350 return -ENOMEM;
1351
1352 irq_id = platform_get_irq_byname(pdev, "asys");
1353 if (irq_id < 0)
1354 return irq_id;
1355
1356 ret = devm_request_irq(dev, irq_id, mt2701_asys_isr,
1357 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
1358 if (ret) {
1359 dev_err(dev, "could not request_irq for asys-isr\n");
1360 return ret;
1361 }
1362
1363 afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
1364 if (IS_ERR(afe->regmap)) {
1365 dev_err(dev, "could not get regmap from parent\n");
1366 return PTR_ERR(afe->regmap);
1367 }
1368
1369 mutex_init(&afe->irq_alloc_lock);
1370
1371
1372 afe->memif_size = MT2701_MEMIF_NUM;
1373 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
1374 GFP_KERNEL);
1375 if (!afe->memif)
1376 return -ENOMEM;
1377
1378 for (i = 0; i < afe->memif_size; i++) {
1379 afe->memif[i].data = &memif_data[i];
1380 afe->memif[i].irq_usage = -1;
1381 }
1382
1383
1384 afe->irqs_size = MT2701_IRQ_ASYS_END;
1385 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
1386 GFP_KERNEL);
1387 if (!afe->irqs)
1388 return -ENOMEM;
1389
1390 for (i = 0; i < afe->irqs_size; i++)
1391 afe->irqs[i].irq_data = &irq_data[i];
1392
1393
1394 for (i = 0; i < afe_priv->soc->i2s_num; i++) {
1395 afe_priv->i2s_path[i].i2s_data[SNDRV_PCM_STREAM_PLAYBACK] =
1396 &mt2701_i2s_data[i][SNDRV_PCM_STREAM_PLAYBACK];
1397 afe_priv->i2s_path[i].i2s_data[SNDRV_PCM_STREAM_CAPTURE] =
1398 &mt2701_i2s_data[i][SNDRV_PCM_STREAM_CAPTURE];
1399 }
1400
1401 afe->mtk_afe_hardware = &mt2701_afe_hardware;
1402 afe->memif_fs = mt2701_memif_fs;
1403 afe->irq_fs = mt2701_irq_fs;
1404 afe->reg_back_up_list = mt2701_afe_backup_list;
1405 afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
1406 afe->runtime_resume = mt2701_afe_runtime_resume;
1407 afe->runtime_suspend = mt2701_afe_runtime_suspend;
1408
1409
1410 ret = mt2701_init_clock(afe);
1411 if (ret) {
1412 dev_err(dev, "init clock error\n");
1413 return ret;
1414 }
1415
1416 platform_set_drvdata(pdev, afe);
1417
1418 pm_runtime_enable(dev);
1419 if (!pm_runtime_enabled(dev)) {
1420 ret = mt2701_afe_runtime_resume(dev);
1421 if (ret)
1422 goto err_pm_disable;
1423 }
1424 pm_runtime_get_sync(dev);
1425
1426 ret = devm_snd_soc_register_component(&pdev->dev, &mtk_afe_pcm_platform,
1427 NULL, 0);
1428 if (ret) {
1429 dev_warn(dev, "err_platform\n");
1430 goto err_platform;
1431 }
1432
1433 ret = devm_snd_soc_register_component(&pdev->dev,
1434 &mt2701_afe_pcm_dai_component,
1435 mt2701_afe_pcm_dais,
1436 ARRAY_SIZE(mt2701_afe_pcm_dais));
1437 if (ret) {
1438 dev_warn(dev, "err_dai_component\n");
1439 goto err_platform;
1440 }
1441
1442 return 0;
1443
1444 err_platform:
1445 pm_runtime_put_sync(dev);
1446 err_pm_disable:
1447 pm_runtime_disable(dev);
1448
1449 return ret;
1450 }
1451
1452 static int mt2701_afe_pcm_dev_remove(struct platform_device *pdev)
1453 {
1454 pm_runtime_put_sync(&pdev->dev);
1455 pm_runtime_disable(&pdev->dev);
1456 if (!pm_runtime_status_suspended(&pdev->dev))
1457 mt2701_afe_runtime_suspend(&pdev->dev);
1458
1459 return 0;
1460 }
1461
1462 static const struct mt2701_soc_variants mt2701_soc_v1 = {
1463 .i2s_num = 4,
1464 };
1465
1466 static const struct mt2701_soc_variants mt2701_soc_v2 = {
1467 .has_one_heart_mode = true,
1468 .i2s_num = 4,
1469 };
1470
1471 static const struct of_device_id mt2701_afe_pcm_dt_match[] = {
1472 { .compatible = "mediatek,mt2701-audio", .data = &mt2701_soc_v1 },
1473 { .compatible = "mediatek,mt7622-audio", .data = &mt2701_soc_v2 },
1474 {},
1475 };
1476 MODULE_DEVICE_TABLE(of, mt2701_afe_pcm_dt_match);
1477
1478 static const struct dev_pm_ops mt2701_afe_pm_ops = {
1479 SET_RUNTIME_PM_OPS(mt2701_afe_runtime_suspend,
1480 mt2701_afe_runtime_resume, NULL)
1481 };
1482
1483 static struct platform_driver mt2701_afe_pcm_driver = {
1484 .driver = {
1485 .name = "mt2701-audio",
1486 .of_match_table = mt2701_afe_pcm_dt_match,
1487 #ifdef CONFIG_PM
1488 .pm = &mt2701_afe_pm_ops,
1489 #endif
1490 },
1491 .probe = mt2701_afe_pcm_dev_probe,
1492 .remove = mt2701_afe_pcm_dev_remove,
1493 };
1494
1495 module_platform_driver(mt2701_afe_pcm_driver);
1496
1497 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
1498 MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
1499 MODULE_LICENSE("GPL v2");