root/sound/soc/meson/axg-fifo.c

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DEFINITIONS

This source file includes following definitions.
  1. axg_fifo_dai
  2. axg_fifo_data
  3. axg_fifo_dev
  4. __dma_enable
  5. axg_fifo_pcm_trigger
  6. axg_fifo_pcm_pointer
  7. axg_fifo_pcm_hw_params
  8. g12a_fifo_pcm_hw_params
  9. axg_fifo_pcm_hw_free
  10. axg_fifo_ack_irq
  11. axg_fifo_pcm_irq_block
  12. axg_fifo_pcm_open
  13. axg_fifo_pcm_close
  14. axg_fifo_pcm_new
  15. axg_fifo_probe

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 //
   3 // Copyright (c) 2018 BayLibre, SAS.
   4 // Author: Jerome Brunet <jbrunet@baylibre.com>
   5 
   6 #include <linux/clk.h>
   7 #include <linux/of_irq.h>
   8 #include <linux/of_platform.h>
   9 #include <linux/module.h>
  10 #include <linux/regmap.h>
  11 #include <linux/reset.h>
  12 #include <sound/pcm_params.h>
  13 #include <sound/soc.h>
  14 #include <sound/soc-dai.h>
  15 
  16 #include "axg-fifo.h"
  17 
  18 /*
  19  * This file implements the platform operations common to the playback and
  20  * capture frontend DAI. The logic behind this two types of fifo is very
  21  * similar but some difference exist.
  22  * These differences are handled in the respective DAI drivers
  23  */
  24 
  25 static struct snd_pcm_hardware axg_fifo_hw = {
  26         .info = (SNDRV_PCM_INFO_INTERLEAVED |
  27                  SNDRV_PCM_INFO_MMAP |
  28                  SNDRV_PCM_INFO_MMAP_VALID |
  29                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
  30                  SNDRV_PCM_INFO_PAUSE),
  31 
  32         .formats = AXG_FIFO_FORMATS,
  33         .rate_min = 5512,
  34         .rate_max = 192000,
  35         .channels_min = 1,
  36         .channels_max = AXG_FIFO_CH_MAX,
  37         .period_bytes_min = AXG_FIFO_MIN_DEPTH,
  38         .period_bytes_max = UINT_MAX,
  39         .periods_min = 2,
  40         .periods_max = UINT_MAX,
  41 
  42         /* No real justification for this */
  43         .buffer_bytes_max = 1 * 1024 * 1024,
  44 };
  45 
  46 static struct snd_soc_dai *axg_fifo_dai(struct snd_pcm_substream *ss)
  47 {
  48         struct snd_soc_pcm_runtime *rtd = ss->private_data;
  49 
  50         return rtd->cpu_dai;
  51 }
  52 
  53 static struct axg_fifo *axg_fifo_data(struct snd_pcm_substream *ss)
  54 {
  55         struct snd_soc_dai *dai = axg_fifo_dai(ss);
  56 
  57         return snd_soc_dai_get_drvdata(dai);
  58 }
  59 
  60 static struct device *axg_fifo_dev(struct snd_pcm_substream *ss)
  61 {
  62         struct snd_soc_dai *dai = axg_fifo_dai(ss);
  63 
  64         return dai->dev;
  65 }
  66 
  67 static void __dma_enable(struct axg_fifo *fifo,  bool enable)
  68 {
  69         regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN,
  70                            enable ? CTRL0_DMA_EN : 0);
  71 }
  72 
  73 static int axg_fifo_pcm_trigger(struct snd_pcm_substream *ss, int cmd)
  74 {
  75         struct axg_fifo *fifo = axg_fifo_data(ss);
  76 
  77         switch (cmd) {
  78         case SNDRV_PCM_TRIGGER_START:
  79         case SNDRV_PCM_TRIGGER_RESUME:
  80         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  81                 __dma_enable(fifo, true);
  82                 break;
  83         case SNDRV_PCM_TRIGGER_SUSPEND:
  84         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  85         case SNDRV_PCM_TRIGGER_STOP:
  86                 __dma_enable(fifo, false);
  87                 break;
  88         default:
  89                 return -EINVAL;
  90         }
  91 
  92         return 0;
  93 }
  94 
  95 static snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_pcm_substream *ss)
  96 {
  97         struct axg_fifo *fifo = axg_fifo_data(ss);
  98         struct snd_pcm_runtime *runtime = ss->runtime;
  99         unsigned int addr;
 100 
 101         regmap_read(fifo->map, FIFO_STATUS2, &addr);
 102 
 103         return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr);
 104 }
 105 
 106 static int axg_fifo_pcm_hw_params(struct snd_pcm_substream *ss,
 107                                   struct snd_pcm_hw_params *params)
 108 {
 109         struct snd_pcm_runtime *runtime = ss->runtime;
 110         struct axg_fifo *fifo = axg_fifo_data(ss);
 111         unsigned int burst_num, period, threshold;
 112         dma_addr_t end_ptr;
 113         int ret;
 114 
 115         period = params_period_bytes(params);
 116 
 117         ret = snd_pcm_lib_malloc_pages(ss, params_buffer_bytes(params));
 118         if (ret < 0)
 119                 return ret;
 120 
 121         /* Setup dma memory pointers */
 122         end_ptr = runtime->dma_addr + runtime->dma_bytes - AXG_FIFO_BURST;
 123         regmap_write(fifo->map, FIFO_START_ADDR, runtime->dma_addr);
 124         regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr);
 125 
 126         /* Setup interrupt periodicity */
 127         burst_num = period / AXG_FIFO_BURST;
 128         regmap_write(fifo->map, FIFO_INT_ADDR, burst_num);
 129 
 130         /*
 131          * Start the fifo request on the smallest of the following:
 132          * - Half the fifo size
 133          * - Half the period size
 134          */
 135         threshold = min(period / 2,
 136                         (unsigned int)AXG_FIFO_MIN_DEPTH / 2);
 137 
 138         /*
 139          * With the threshold in bytes, register value is:
 140          * V = (threshold / burst) - 1
 141          */
 142         threshold /= AXG_FIFO_BURST;
 143         regmap_field_write(fifo->field_threshold,
 144                            threshold ? threshold - 1 : 0);
 145 
 146         /* Enable block count irq */
 147         regmap_update_bits(fifo->map, FIFO_CTRL0,
 148                            CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT),
 149                            CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT));
 150 
 151         return 0;
 152 }
 153 
 154 static int g12a_fifo_pcm_hw_params(struct snd_pcm_substream *ss,
 155                                    struct snd_pcm_hw_params *params)
 156 {
 157         struct axg_fifo *fifo = axg_fifo_data(ss);
 158         struct snd_pcm_runtime *runtime = ss->runtime;
 159         int ret;
 160 
 161         ret = axg_fifo_pcm_hw_params(ss, params);
 162         if (ret)
 163                 return ret;
 164 
 165         /* Set the initial memory address of the DMA */
 166         regmap_write(fifo->map, FIFO_INIT_ADDR, runtime->dma_addr);
 167 
 168         return 0;
 169 }
 170 
 171 static int axg_fifo_pcm_hw_free(struct snd_pcm_substream *ss)
 172 {
 173         struct axg_fifo *fifo = axg_fifo_data(ss);
 174 
 175         /* Disable the block count irq */
 176         regmap_update_bits(fifo->map, FIFO_CTRL0,
 177                            CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0);
 178 
 179         return snd_pcm_lib_free_pages(ss);
 180 }
 181 
 182 static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)
 183 {
 184         regmap_update_bits(fifo->map, FIFO_CTRL1,
 185                            CTRL1_INT_CLR(FIFO_INT_MASK),
 186                            CTRL1_INT_CLR(mask));
 187 
 188         /* Clear must also be cleared */
 189         regmap_update_bits(fifo->map, FIFO_CTRL1,
 190                            CTRL1_INT_CLR(FIFO_INT_MASK),
 191                            0);
 192 }
 193 
 194 static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id)
 195 {
 196         struct snd_pcm_substream *ss = dev_id;
 197         struct axg_fifo *fifo = axg_fifo_data(ss);
 198         unsigned int status;
 199 
 200         regmap_read(fifo->map, FIFO_STATUS1, &status);
 201 
 202         status = STATUS1_INT_STS(status) & FIFO_INT_MASK;
 203         if (status & FIFO_INT_COUNT_REPEAT)
 204                 snd_pcm_period_elapsed(ss);
 205         else
 206                 dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n",
 207                         status);
 208 
 209         /* Ack irqs */
 210         axg_fifo_ack_irq(fifo, status);
 211 
 212         return IRQ_RETVAL(status);
 213 }
 214 
 215 static int axg_fifo_pcm_open(struct snd_pcm_substream *ss)
 216 {
 217         struct axg_fifo *fifo = axg_fifo_data(ss);
 218         struct device *dev = axg_fifo_dev(ss);
 219         int ret;
 220 
 221         snd_soc_set_runtime_hwparams(ss, &axg_fifo_hw);
 222 
 223         /*
 224          * Make sure the buffer and period size are multiple of the FIFO
 225          * minimum depth size
 226          */
 227         ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
 228                                          SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 229                                          AXG_FIFO_MIN_DEPTH);
 230         if (ret)
 231                 return ret;
 232 
 233         ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
 234                                          SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 235                                          AXG_FIFO_MIN_DEPTH);
 236         if (ret)
 237                 return ret;
 238 
 239         ret = request_irq(fifo->irq, axg_fifo_pcm_irq_block, 0,
 240                           dev_name(dev), ss);
 241         if (ret)
 242                 return ret;
 243 
 244         /* Enable pclk to access registers and clock the fifo ip */
 245         ret = clk_prepare_enable(fifo->pclk);
 246         if (ret)
 247                 return ret;
 248 
 249         /* Setup status2 so it reports the memory pointer */
 250         regmap_update_bits(fifo->map, FIFO_CTRL1,
 251                            CTRL1_STATUS2_SEL_MASK,
 252                            CTRL1_STATUS2_SEL(STATUS2_SEL_DDR_READ));
 253 
 254         /* Make sure the dma is initially disabled */
 255         __dma_enable(fifo, false);
 256 
 257         /* Disable irqs until params are ready */
 258         regmap_update_bits(fifo->map, FIFO_CTRL0,
 259                            CTRL0_INT_EN(FIFO_INT_MASK), 0);
 260 
 261         /* Clear any pending interrupt */
 262         axg_fifo_ack_irq(fifo, FIFO_INT_MASK);
 263 
 264         /* Take memory arbitror out of reset */
 265         ret = reset_control_deassert(fifo->arb);
 266         if (ret)
 267                 clk_disable_unprepare(fifo->pclk);
 268 
 269         return ret;
 270 }
 271 
 272 static int axg_fifo_pcm_close(struct snd_pcm_substream *ss)
 273 {
 274         struct axg_fifo *fifo = axg_fifo_data(ss);
 275         int ret;
 276 
 277         /* Put the memory arbitror back in reset */
 278         ret = reset_control_assert(fifo->arb);
 279 
 280         /* Disable fifo ip and register access */
 281         clk_disable_unprepare(fifo->pclk);
 282 
 283         /* remove IRQ */
 284         free_irq(fifo->irq, ss);
 285 
 286         return ret;
 287 }
 288 
 289 const struct snd_pcm_ops axg_fifo_pcm_ops = {
 290         .open =         axg_fifo_pcm_open,
 291         .close =        axg_fifo_pcm_close,
 292         .ioctl =        snd_pcm_lib_ioctl,
 293         .hw_params =    axg_fifo_pcm_hw_params,
 294         .hw_free =      axg_fifo_pcm_hw_free,
 295         .pointer =      axg_fifo_pcm_pointer,
 296         .trigger =      axg_fifo_pcm_trigger,
 297 };
 298 EXPORT_SYMBOL_GPL(axg_fifo_pcm_ops);
 299 
 300 const struct snd_pcm_ops g12a_fifo_pcm_ops = {
 301         .open =         axg_fifo_pcm_open,
 302         .close =        axg_fifo_pcm_close,
 303         .ioctl =        snd_pcm_lib_ioctl,
 304         .hw_params =    g12a_fifo_pcm_hw_params,
 305         .hw_free =      axg_fifo_pcm_hw_free,
 306         .pointer =      axg_fifo_pcm_pointer,
 307         .trigger =      axg_fifo_pcm_trigger,
 308 };
 309 EXPORT_SYMBOL_GPL(g12a_fifo_pcm_ops);
 310 
 311 int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type)
 312 {
 313         struct snd_card *card = rtd->card->snd_card;
 314         size_t size = axg_fifo_hw.buffer_bytes_max;
 315 
 316         snd_pcm_lib_preallocate_pages(rtd->pcm->streams[type].substream,
 317                                       SNDRV_DMA_TYPE_DEV, card->dev,
 318                                       size, size);
 319         return 0;
 320 }
 321 EXPORT_SYMBOL_GPL(axg_fifo_pcm_new);
 322 
 323 static const struct regmap_config axg_fifo_regmap_cfg = {
 324         .reg_bits       = 32,
 325         .val_bits       = 32,
 326         .reg_stride     = 4,
 327         .max_register   = FIFO_CTRL2,
 328 };
 329 
 330 int axg_fifo_probe(struct platform_device *pdev)
 331 {
 332         struct device *dev = &pdev->dev;
 333         const struct axg_fifo_match_data *data;
 334         struct axg_fifo *fifo;
 335         void __iomem *regs;
 336 
 337         data = of_device_get_match_data(dev);
 338         if (!data) {
 339                 dev_err(dev, "failed to match device\n");
 340                 return -ENODEV;
 341         }
 342 
 343         fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
 344         if (!fifo)
 345                 return -ENOMEM;
 346         platform_set_drvdata(pdev, fifo);
 347 
 348         regs = devm_platform_ioremap_resource(pdev, 0);
 349         if (IS_ERR(regs))
 350                 return PTR_ERR(regs);
 351 
 352         fifo->map = devm_regmap_init_mmio(dev, regs, &axg_fifo_regmap_cfg);
 353         if (IS_ERR(fifo->map)) {
 354                 dev_err(dev, "failed to init regmap: %ld\n",
 355                         PTR_ERR(fifo->map));
 356                 return PTR_ERR(fifo->map);
 357         }
 358 
 359         fifo->pclk = devm_clk_get(dev, NULL);
 360         if (IS_ERR(fifo->pclk)) {
 361                 if (PTR_ERR(fifo->pclk) != -EPROBE_DEFER)
 362                         dev_err(dev, "failed to get pclk: %ld\n",
 363                                 PTR_ERR(fifo->pclk));
 364                 return PTR_ERR(fifo->pclk);
 365         }
 366 
 367         fifo->arb = devm_reset_control_get_exclusive(dev, NULL);
 368         if (IS_ERR(fifo->arb)) {
 369                 if (PTR_ERR(fifo->arb) != -EPROBE_DEFER)
 370                         dev_err(dev, "failed to get arb reset: %ld\n",
 371                                 PTR_ERR(fifo->arb));
 372                 return PTR_ERR(fifo->arb);
 373         }
 374 
 375         fifo->irq = of_irq_get(dev->of_node, 0);
 376         if (fifo->irq <= 0) {
 377                 dev_err(dev, "failed to get irq: %d\n", fifo->irq);
 378                 return fifo->irq;
 379         }
 380 
 381         fifo->field_threshold =
 382                 devm_regmap_field_alloc(dev, fifo->map, data->field_threshold);
 383         if (IS_ERR(fifo->field_threshold))
 384                 return PTR_ERR(fifo->field_threshold);
 385 
 386         return devm_snd_soc_register_component(dev, data->component_drv,
 387                                                data->dai_drv, 1);
 388 }
 389 EXPORT_SYMBOL_GPL(axg_fifo_probe);
 390 
 391 MODULE_DESCRIPTION("Amlogic AXG/G12A fifo driver");
 392 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
 393 MODULE_LICENSE("GPL v2");

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