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7 #ifndef _MESON_AXG_FIFO_H
8 #define _MESON_AXG_FIFO_H
9
10 struct clk;
11 struct platform_device;
12 struct reg_field;
13 struct regmap;
14 struct regmap_field;
15 struct reset_control;
16
17 struct snd_soc_component_driver;
18 struct snd_soc_dai;
19 struct snd_soc_dai_driver;
20 struct snd_pcm_ops;
21 struct snd_soc_pcm_runtime;
22
23 #define AXG_FIFO_CH_MAX 128
24 #define AXG_FIFO_RATES (SNDRV_PCM_RATE_5512 | \
25 SNDRV_PCM_RATE_8000_192000)
26 #define AXG_FIFO_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
27 SNDRV_PCM_FMTBIT_S16_LE | \
28 SNDRV_PCM_FMTBIT_S20_LE | \
29 SNDRV_PCM_FMTBIT_S24_LE | \
30 SNDRV_PCM_FMTBIT_S32_LE | \
31 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
32
33 #define AXG_FIFO_BURST 8
34 #define AXG_FIFO_MIN_CNT 64
35 #define AXG_FIFO_MIN_DEPTH (AXG_FIFO_BURST * AXG_FIFO_MIN_CNT)
36
37 #define FIFO_INT_ADDR_FINISH BIT(0)
38 #define FIFO_INT_ADDR_INT BIT(1)
39 #define FIFO_INT_COUNT_REPEAT BIT(2)
40 #define FIFO_INT_COUNT_ONCE BIT(3)
41 #define FIFO_INT_FIFO_ZERO BIT(4)
42 #define FIFO_INT_FIFO_DEPTH BIT(5)
43 #define FIFO_INT_MASK GENMASK(7, 0)
44
45 #define FIFO_CTRL0 0x00
46 #define CTRL0_DMA_EN BIT(31)
47 #define CTRL0_INT_EN(x) ((x) << 16)
48 #define CTRL0_SEL_MASK GENMASK(2, 0)
49 #define CTRL0_SEL_SHIFT 0
50 #define FIFO_CTRL1 0x04
51 #define CTRL1_INT_CLR(x) ((x) << 0)
52 #define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8)
53 #define CTRL1_STATUS2_SEL(x) ((x) << 8)
54 #define STATUS2_SEL_DDR_READ 0
55 #define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24)
56 #define CTRL1_FRDDR_DEPTH(x) ((x) << 24)
57 #define FIFO_START_ADDR 0x08
58 #define FIFO_FINISH_ADDR 0x0c
59 #define FIFO_INT_ADDR 0x10
60 #define FIFO_STATUS1 0x14
61 #define STATUS1_INT_STS(x) ((x) << 0)
62 #define FIFO_STATUS2 0x18
63 #define FIFO_INIT_ADDR 0x24
64 #define FIFO_CTRL2 0x28
65
66 struct axg_fifo {
67 struct regmap *map;
68 struct clk *pclk;
69 struct reset_control *arb;
70 struct regmap_field *field_threshold;
71 int irq;
72 };
73
74 struct axg_fifo_match_data {
75 const struct snd_soc_component_driver *component_drv;
76 struct snd_soc_dai_driver *dai_drv;
77 struct reg_field field_threshold;
78 };
79
80 extern const struct snd_pcm_ops axg_fifo_pcm_ops;
81 extern const struct snd_pcm_ops g12a_fifo_pcm_ops;
82
83 int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type);
84 int axg_fifo_probe(struct platform_device *pdev);
85
86 #endif