root/sound/soc/fsl/fsl_micfil.h

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INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * PDM Microphone Interface for the NXP i.MX SoC
   4  * Copyright 2018 NXP
   5  */
   6 
   7 #ifndef _FSL_MICFIL_H
   8 #define _FSL_MICFIL_H
   9 
  10 /* MICFIL Register Map */
  11 #define REG_MICFIL_CTRL1                0x00
  12 #define REG_MICFIL_CTRL2                0x04
  13 #define REG_MICFIL_STAT                 0x08
  14 #define REG_MICFIL_FIFO_CTRL            0x10
  15 #define REG_MICFIL_FIFO_STAT            0x14
  16 #define REG_MICFIL_DATACH0              0x24
  17 #define REG_MICFIL_DATACH1              0x28
  18 #define REG_MICFIL_DATACH2              0x2C
  19 #define REG_MICFIL_DATACH3              0x30
  20 #define REG_MICFIL_DATACH4              0x34
  21 #define REG_MICFIL_DATACH5              0x38
  22 #define REG_MICFIL_DATACH6              0x3C
  23 #define REG_MICFIL_DATACH7              0x40
  24 #define REG_MICFIL_DC_CTRL              0x64
  25 #define REG_MICFIL_OUT_CTRL             0x74
  26 #define REG_MICFIL_OUT_STAT             0x7C
  27 #define REG_MICFIL_VAD0_CTRL1           0x90
  28 #define REG_MICFIL_VAD0_CTRL2           0x94
  29 #define REG_MICFIL_VAD0_STAT            0x98
  30 #define REG_MICFIL_VAD0_SCONFIG         0x9C
  31 #define REG_MICFIL_VAD0_NCONFIG         0xA0
  32 #define REG_MICFIL_VAD0_NDATA           0xA4
  33 #define REG_MICFIL_VAD0_ZCD             0xA8
  34 
  35 /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
  36 #define MICFIL_CTRL1_MDIS_SHIFT         31
  37 #define MICFIL_CTRL1_MDIS_MASK          BIT(MICFIL_CTRL1_MDIS_SHIFT)
  38 #define MICFIL_CTRL1_MDIS               BIT(MICFIL_CTRL1_MDIS_SHIFT)
  39 #define MICFIL_CTRL1_DOZEN_SHIFT        30
  40 #define MICFIL_CTRL1_DOZEN_MASK         BIT(MICFIL_CTRL1_DOZEN_SHIFT)
  41 #define MICFIL_CTRL1_DOZEN              BIT(MICFIL_CTRL1_DOZEN_SHIFT)
  42 #define MICFIL_CTRL1_PDMIEN_SHIFT       29
  43 #define MICFIL_CTRL1_PDMIEN_MASK        BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
  44 #define MICFIL_CTRL1_PDMIEN             BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
  45 #define MICFIL_CTRL1_DBG_SHIFT          28
  46 #define MICFIL_CTRL1_DBG_MASK           BIT(MICFIL_CTRL1_DBG_SHIFT)
  47 #define MICFIL_CTRL1_DBG                BIT(MICFIL_CTRL1_DBG_SHIFT)
  48 #define MICFIL_CTRL1_SRES_SHIFT         27
  49 #define MICFIL_CTRL1_SRES_MASK          BIT(MICFIL_CTRL1_SRES_SHIFT)
  50 #define MICFIL_CTRL1_SRES               BIT(MICFIL_CTRL1_SRES_SHIFT)
  51 #define MICFIL_CTRL1_DBGE_SHIFT         26
  52 #define MICFIL_CTRL1_DBGE_MASK          BIT(MICFIL_CTRL1_DBGE_SHIFT)
  53 #define MICFIL_CTRL1_DBGE               BIT(MICFIL_CTRL1_DBGE_SHIFT)
  54 #define MICFIL_CTRL1_DISEL_SHIFT        24
  55 #define MICFIL_CTRL1_DISEL_WIDTH        2
  56 #define MICFIL_CTRL1_DISEL_MASK         ((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \
  57                                          << MICFIL_CTRL1_DISEL_SHIFT)
  58 #define MICFIL_CTRL1_DISEL(v)           (((v) << MICFIL_CTRL1_DISEL_SHIFT) \
  59                                          & MICFIL_CTRL1_DISEL_MASK)
  60 #define MICFIL_CTRL1_ERREN_SHIFT        23
  61 #define MICFIL_CTRL1_ERREN_MASK         BIT(MICFIL_CTRL1_ERREN_SHIFT)
  62 #define MICFIL_CTRL1_ERREN              BIT(MICFIL_CTRL1_ERREN_SHIFT)
  63 #define MICFIL_CTRL1_CHEN_SHIFT         0
  64 #define MICFIL_CTRL1_CHEN_WIDTH         8
  65 #define MICFIL_CTRL1_CHEN_MASK(x)       (BIT(x) << MICFIL_CTRL1_CHEN_SHIFT)
  66 #define MICFIL_CTRL1_CHEN(x)            (MICFIL_CTRL1_CHEN_MASK(x))
  67 
  68 /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
  69 #define MICFIL_CTRL2_QSEL_SHIFT         25
  70 #define MICFIL_CTRL2_QSEL_WIDTH         3
  71 #define MICFIL_CTRL2_QSEL_MASK          ((BIT(MICFIL_CTRL2_QSEL_WIDTH) - 1) \
  72                                          << MICFIL_CTRL2_QSEL_SHIFT)
  73 #define MICFIL_HIGH_QUALITY             BIT(MICFIL_CTRL2_QSEL_SHIFT)
  74 #define MICFIL_MEDIUM_QUALITY           (0 << MICFIL_CTRL2_QSEL_SHIFT)
  75 #define MICFIL_LOW_QUALITY              (7 << MICFIL_CTRL2_QSEL_SHIFT)
  76 #define MICFIL_VLOW0_QUALITY            (6 << MICFIL_CTRL2_QSEL_SHIFT)
  77 #define MICFIL_VLOW1_QUALITY            (5 << MICFIL_CTRL2_QSEL_SHIFT)
  78 #define MICFIL_VLOW2_QUALITY            (4 << MICFIL_CTRL2_QSEL_SHIFT)
  79 
  80 #define MICFIL_CTRL2_CICOSR_SHIFT       16
  81 #define MICFIL_CTRL2_CICOSR_WIDTH       4
  82 #define MICFIL_CTRL2_CICOSR_MASK        ((BIT(MICFIL_CTRL2_CICOSR_WIDTH) - 1) \
  83                                          << MICFIL_CTRL2_CICOSR_SHIFT)
  84 #define MICFIL_CTRL2_CICOSR(v)          (((v) << MICFIL_CTRL2_CICOSR_SHIFT) \
  85                                          & MICFIL_CTRL2_CICOSR_MASK)
  86 #define MICFIL_CTRL2_CLKDIV_SHIFT       0
  87 #define MICFIL_CTRL2_CLKDIV_WIDTH       8
  88 #define MICFIL_CTRL2_CLKDIV_MASK        ((BIT(MICFIL_CTRL2_CLKDIV_WIDTH) - 1) \
  89                                          << MICFIL_CTRL2_CLKDIV_SHIFT)
  90 #define MICFIL_CTRL2_CLKDIV(v)          (((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \
  91                                          & MICFIL_CTRL2_CLKDIV_MASK)
  92 
  93 /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
  94 #define MICFIL_STAT_BSY_FIL_SHIFT       31
  95 #define MICFIL_STAT_BSY_FIL_MASK        BIT(MICFIL_STAT_BSY_FIL_SHIFT)
  96 #define MICFIL_STAT_BSY_FIL             BIT(MICFIL_STAT_BSY_FIL_SHIFT)
  97 #define MICFIL_STAT_FIR_RDY_SHIFT       30
  98 #define MICFIL_STAT_FIR_RDY_MASK        BIT(MICFIL_STAT_FIR_RDY_SHIFT)
  99 #define MICFIL_STAT_FIR_RDY             BIT(MICFIL_STAT_FIR_RDY_SHIFT)
 100 #define MICFIL_STAT_LOWFREQF_SHIFT      29
 101 #define MICFIL_STAT_LOWFREQF_MASK       BIT(MICFIL_STAT_LOWFREQF_SHIFT)
 102 #define MICFIL_STAT_LOWFREQF            BIT(MICFIL_STAT_LOWFREQF_SHIFT)
 103 #define MICFIL_STAT_CHXF_SHIFT(v)       (v)
 104 #define MICFIL_STAT_CHXF_MASK(v)        BIT(MICFIL_STAT_CHXF_SHIFT(v))
 105 #define MICFIL_STAT_CHXF(v)             BIT(MICFIL_STAT_CHXF_SHIFT(v))
 106 
 107 /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
 108 #define MICFIL_FIFO_CTRL_FIFOWMK_SHIFT  0
 109 #define MICFIL_FIFO_CTRL_FIFOWMK_WIDTH  3
 110 #define MICFIL_FIFO_CTRL_FIFOWMK_MASK   ((BIT(MICFIL_FIFO_CTRL_FIFOWMK_WIDTH) - 1) \
 111                                          << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT)
 112 #define MICFIL_FIFO_CTRL_FIFOWMK(v)     (((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \
 113                                          & MICFIL_FIFO_CTRL_FIFOWMK_MASK)
 114 
 115 /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
 116 #define MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v)    (v)
 117 #define MICFIL_FIFO_STAT_FIFOX_OVER_MASK(v)     BIT(MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v))
 118 #define MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v)   ((v) + 8)
 119 #define MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(v)    BIT(MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v))
 120 
 121 /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
 122 #define MICFIL_VAD0_CTRL1_CHSEL_SHIFT   24
 123 #define MICFIL_VAD0_CTRL1_CHSEL_WIDTH   3
 124 #define MICFIL_VAD0_CTRL1_CHSEL_MASK    ((BIT(MICFIL_VAD0_CTRL1_CHSEL_WIDTH) - 1) \
 125                                          << MICFIL_VAD0_CTRL1_CHSEL_SHIFT)
 126 #define MICFIL_VAD0_CTRL1_CHSEL(v)      (((v) << MICFIL_VAD0_CTRL1_CHSEL_SHIFT) \
 127                                          & MICFIL_VAD0_CTRL1_CHSEL_MASK)
 128 #define MICFIL_VAD0_CTRL1_CICOSR_SHIFT  16
 129 #define MICFIL_VAD0_CTRL1_CICOSR_WIDTH  4
 130 #define MICFIL_VAD0_CTRL1_CICOSR_MASK   ((BIT(MICFIL_VAD0_CTRL1_CICOSR_WIDTH) - 1) \
 131                                          << MICFIL_VAD0_CTRL1_CICOSR_SHIFT)
 132 #define MICFIL_VAD0_CTRL1_CICOSR(v)     (((v) << MICFIL_VAD0_CTRL1_CICOSR_SHIFT) \
 133                                          & MICFIL_VAD0_CTRL1_CICOSR_MASK)
 134 #define MICFIL_VAD0_CTRL1_INITT_SHIFT   8
 135 #define MICFIL_VAD0_CTRL1_INITT_WIDTH   5
 136 #define MICFIL_VAD0_CTRL1_INITT_MASK    ((BIT(MICFIL_VAD0_CTRL1_INITT_WIDTH) - 1) \
 137                                          << MICFIL_VAD0_CTRL1_INITT_SHIFT)
 138 #define MICFIL_VAD0_CTRL1_INITT(v)      (((v) << MICFIL_VAD0_CTRL1_INITT_SHIFT) \
 139                                          & MICFIL_VAD0_CTRL1_INITT_MASK)
 140 #define MICFIL_VAD0_CTRL1_ST10_SHIFT    4
 141 #define MICFIL_VAD0_CTRL1_ST10_MASK     BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
 142 #define MICFIL_VAD0_CTRL1_ST10          BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
 143 #define MICFIL_VAD0_CTRL1_ERIE_SHIFT    3
 144 #define MICFIL_VAD0_CTRL1_ERIE_MASK     BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
 145 #define MICFIL_VAD0_CTRL1_ERIE          BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
 146 #define MICFIL_VAD0_CTRL1_IE_SHIFT      2
 147 #define MICFIL_VAD0_CTRL1_IE_MASK       BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
 148 #define MICFIL_VAD0_CTRL1_IE            BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
 149 #define MICFIL_VAD0_CTRL1_RST_SHIFT     1
 150 #define MICFIL_VAD0_CTRL1_RST_MASK      BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
 151 #define MICFIL_VAD0_CTRL1_RST           BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
 152 #define MICFIL_VAD0_CTRL1_EN_SHIFT      0
 153 #define MICFIL_VAD0_CTRL1_EN_MASK       BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
 154 #define MICFIL_VAD0_CTRL1_EN            BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
 155 
 156 /* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
 157 #define MICFIL_VAD0_CTRL2_FRENDIS_SHIFT 31
 158 #define MICFIL_VAD0_CTRL2_FRENDIS_MASK  BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT)
 159 #define MICFIL_VAD0_CTRL2_FRENDIS       BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT)
 160 #define MICFIL_VAD0_CTRL2_PREFEN_SHIFT  30
 161 #define MICFIL_VAD0_CTRL2_PREFEN_MASK   BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT)
 162 #define MICFIL_VAD0_CTRL2_PREFEN        BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT)
 163 #define MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT 28
 164 #define MICFIL_VAD0_CTRL2_FOUTDIS_MASK  BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
 165 #define MICFIL_VAD0_CTRL2_FOUTDIS       BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
 166 #define MICFIL_VAD0_CTRL2_FRAMET_SHIFT  16
 167 #define MICFIL_VAD0_CTRL2_FRAMET_WIDTH  6
 168 #define MICFIL_VAD0_CTRL2_FRAMET_MASK   ((BIT(MICFIL_VAD0_CTRL2_FRAMET_WIDTH) - 1) \
 169                                          << MICFIL_VAD0_CTRL2_FRAMET_SHIFT)
 170 #define MICFIL_VAD0_CTRL2_FRAMET(v)     (((v) << MICFIL_VAD0_CTRL2_FRAMET_SHIFT) \
 171                                          & MICFIL_VAD0_CTRL2_FRAMET_MASK)
 172 #define MICFIL_VAD0_CTRL2_INPGAIN_SHIFT 8
 173 #define MICFIL_VAD0_CTRL2_INPGAIN_WIDTH 4
 174 #define MICFIL_VAD0_CTRL2_INPGAIN_MASK  ((BIT(MICFIL_VAD0_CTRL2_INPGAIN_WIDTH) - 1) \
 175                                          << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT)
 176 #define MICFIL_VAD0_CTRL2_INPGAIN(v)    (((v) << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT) \
 177                                         & MICFIL_VAD0_CTRL2_INPGAIN_MASK)
 178 #define MICFIL_VAD0_CTRL2_HPF_SHIFT     0
 179 #define MICFIL_VAD0_CTRL2_HPF_WIDTH     2
 180 #define MICFIL_VAD0_CTRL2_HPF_MASK      ((BIT(MICFIL_VAD0_CTRL2_HPF_WIDTH) - 1) \
 181                                          << MICFIL_VAD0_CTRL2_HPF_SHIFT)
 182 #define MICFIL_VAD0_CTRL2_HPF(v)        (((v) << MICFIL_VAD0_CTRL2_HPF_SHIFT) \
 183                                          & MICFIL_VAD0_CTRL2_HPF_MASK)
 184 
 185 /* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
 186 #define MICFIL_VAD0_SCONFIG_SFILEN_SHIFT        31
 187 #define MICFIL_VAD0_SCONFIG_SFILEN_MASK         BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT)
 188 #define MICFIL_VAD0_SCONFIG_SFILEN              BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT)
 189 #define MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT        30
 190 #define MICFIL_VAD0_SCONFIG_SMAXEN_MASK         BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
 191 #define MICFIL_VAD0_SCONFIG_SMAXEN              BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
 192 #define MICFIL_VAD0_SCONFIG_SGAIN_SHIFT         0
 193 #define MICFIL_VAD0_SCONFIG_SGAIN_WIDTH         4
 194 #define MICFIL_VAD0_SCONFIG_SGAIN_MASK          ((BIT(MICFIL_VAD0_SCONFIG_SGAIN_WIDTH) - 1) \
 195                                                 << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT)
 196 #define MICFIL_VAD0_SCONFIG_SGAIN(v)            (((v) << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT) \
 197                                                  & MICFIL_VAD0_SCONFIG_SGAIN_MASK)
 198 
 199 /* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
 200 #define MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT       31
 201 #define MICFIL_VAD0_NCONFIG_NFILAUT_MASK        BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT)
 202 #define MICFIL_VAD0_NCONFIG_NFILAUT             BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT)
 203 #define MICFIL_VAD0_NCONFIG_NMINEN_SHIFT        30
 204 #define MICFIL_VAD0_NCONFIG_NMINEN_MASK         BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT)
 205 #define MICFIL_VAD0_NCONFIG_NMINEN              BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT)
 206 #define MICFIL_VAD0_NCONFIG_NDECEN_SHIFT        29
 207 #define MICFIL_VAD0_NCONFIG_NDECEN_MASK         BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
 208 #define MICFIL_VAD0_NCONFIG_NDECEN              BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
 209 #define MICFIL_VAD0_NCONFIG_NOREN_SHIFT         28
 210 #define MICFIL_VAD0_NCONFIG_NOREN               BIT(MICFIL_VAD0_NCONFIG_NOREN_SHIFT)
 211 #define MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT       8
 212 #define MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH       5
 213 #define MICFIL_VAD0_NCONFIG_NFILADJ_MASK        ((BIT(MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH) - 1) \
 214                                                  << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT)
 215 #define MICFIL_VAD0_NCONFIG_NFILADJ(v)          (((v) << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT) \
 216                                                  & MICFIL_VAD0_NCONFIG_NFILADJ_MASK)
 217 #define MICFIL_VAD0_NCONFIG_NGAIN_SHIFT         0
 218 #define MICFIL_VAD0_NCONFIG_NGAIN_WIDTH         4
 219 #define MICFIL_VAD0_NCONFIG_NGAIN_MASK          ((BIT(MICFIL_VAD0_NCONFIG_NGAIN_WIDTH) - 1) \
 220                                                  << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT)
 221 #define MICFIL_VAD0_NCONFIG_NGAIN(v)            (((v) << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT) \
 222                                                  & MICFIL_VAD0_NCONFIG_NGAIN_MASK)
 223 
 224 /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
 225 #define MICFIL_VAD0_ZCD_ZCDTH_SHIFT     16
 226 #define MICFIL_VAD0_ZCD_ZCDTH_WIDTH     10
 227 #define MICFIL_VAD0_ZCD_ZCDTH_MASK      ((BIT(MICFIL_VAD0_ZCD_ZCDTH_WIDTH) - 1) \
 228                                          << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)
 229 #define MICFIL_VAD0_ZCD_ZCDTH(v)        (((v) << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)\
 230                                          & MICFIL_VAD0_ZCD_ZCDTH_MASK)
 231 #define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT    8
 232 #define MICFIL_VAD0_ZCD_ZCDADJ_WIDTH    4
 233 #define MICFIL_VAD0_ZCD_ZCDADJ_MASK     ((BIT(MICFIL_VAD0_ZCD_ZCDADJ_WIDTH) - 1)\
 234                                          << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)
 235 #define MICFIL_VAD0_ZCD_ZCDADJ(v)       (((v) << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)\
 236                                          & MICFIL_VAD0_ZCD_ZCDADJ_MASK)
 237 #define MICFIL_VAD0_ZCD_ZCDAND_SHIFT    4
 238 #define MICFIL_VAD0_ZCD_ZCDAND_MASK     BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
 239 #define MICFIL_VAD0_ZCD_ZCDAND          BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
 240 #define MICFIL_VAD0_ZCD_ZCDAUT_SHIFT    2
 241 #define MICFIL_VAD0_ZCD_ZCDAUT_MASK     BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
 242 #define MICFIL_VAD0_ZCD_ZCDAUT          BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
 243 #define MICFIL_VAD0_ZCD_ZCDEN_SHIFT     0
 244 #define MICFIL_VAD0_ZCD_ZCDEN_MASK      BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
 245 #define MICFIL_VAD0_ZCD_ZCDEN           BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
 246 
 247 /* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
 248 #define MICFIL_VAD0_STAT_INITF_SHIFT    31
 249 #define MICFIL_VAD0_STAT_INITF_MASK     BIT(MICFIL_VAD0_STAT_INITF_SHIFT)
 250 #define MICFIL_VAD0_STAT_INITF          BIT(MICFIL_VAD0_STAT_INITF_SHIFT)
 251 #define MICFIL_VAD0_STAT_INSATF_SHIFT   16
 252 #define MICFIL_VAD0_STAT_INSATF_MASK    BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
 253 #define MICFIL_VAD0_STAT_INSATF         BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
 254 #define MICFIL_VAD0_STAT_EF_SHIFT       15
 255 #define MICFIL_VAD0_STAT_EF_MASK        BIT(MICFIL_VAD0_STAT_EF_SHIFT)
 256 #define MICFIL_VAD0_STAT_EF             BIT(MICFIL_VAD0_STAT_EF_SHIFT)
 257 #define MICFIL_VAD0_STAT_IF_SHIFT       0
 258 #define MICFIL_VAD0_STAT_IF_MASK        BIT(MICFIL_VAD0_STAT_IF_SHIFT)
 259 #define MICFIL_VAD0_STAT_IF             BIT(MICFIL_VAD0_STAT_IF_SHIFT)
 260 
 261 /* MICFIL Output Control Register */
 262 #define MICFIL_OUTGAIN_CHX_SHIFT(v)     (4 * (v))
 263 
 264 /* Constants */
 265 #define MICFIL_DMA_IRQ_DISABLED(v)      ((v) & MICFIL_CTRL1_DISEL_MASK)
 266 #define MICFIL_DMA_ENABLED(v)           ((0x1 << MICFIL_CTRL1_DISEL_SHIFT) \
 267                                          == ((v) & MICFIL_CTRL1_DISEL_MASK))
 268 #define MICFIL_IRQ_ENABLED(v)           ((0x2 << MICFIL_CTRL1_DISEL_SHIFT) \
 269                                          == ((v) & MICFIL_CTRL1_DISEL_MASK))
 270 #define MICFIL_OUTPUT_CHANNELS          8
 271 #define MICFIL_FIFO_NUM                 8
 272 
 273 #define FIFO_PTRWID                     3
 274 #define FIFO_LEN                        BIT(FIFO_PTRWID)
 275 
 276 #define MICFIL_IRQ_LINES                2
 277 #define MICFIL_MAX_RETRY                25
 278 #define MICFIL_SLEEP_MIN                90000 /* in us */
 279 #define MICFIL_SLEEP_MAX                100000 /* in us */
 280 #define MICFIL_DMA_MAXBURST_RX          6
 281 #define MICFIL_CTRL2_OSR_DEFAULT        (0 << MICFIL_CTRL2_CICOSR_SHIFT)
 282 
 283 #endif /* _FSL_MICFIL_H */
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