root/sound/soc/fsl/fsl_dma.h

INCLUDED FROM

DEFINITIONS

1. CCSR_DMA_ECLNDAR_ADDR

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * mpc8610-pcm.h - ALSA PCM interface for the Freescale MPC8610 SoC
   4  */
   5 
   6 #ifndef _MPC8610_PCM_H
   7 #define _MPC8610_PCM_H
   8 
   9 struct ccsr_dma {
  10         u8 res0[0x100];
  11         struct ccsr_dma_channel {
  12                 __be32 mr;      /* Mode register */
  13                 __be32 sr;      /* Status register */
  14                 __be32 eclndar; /* Current link descriptor extended addr reg */
  15                 __be32 clndar;  /* Current link descriptor address register */
  16                 __be32 satr;    /* Source attributes register */
  17                 __be32 sar;     /* Source address register */
  18                 __be32 datr;    /* Destination attributes register */
  19                 __be32 dar;     /* Destination address register */
  20                 __be32 bcr;     /* Byte count register */
  21                 __be32 enlndar; /* Next link descriptor extended address reg */
  22                 __be32 nlndar;  /* Next link descriptor address register */
  23                 u8 res1[4];
  24                 __be32 eclsdar; /* Current list descriptor extended addr reg */
  25                 __be32 clsdar;  /* Current list descriptor address register */
  26                 __be32 enlsdar; /* Next list descriptor extended address reg */
  27                 __be32 nlsdar;  /* Next list descriptor address register */
  28                 __be32 ssr;     /* Source stride register */
  29                 __be32 dsr;     /* Destination stride register */
  30                 u8 res2[0x38];
  31         } channel[4];
  32         __be32 dgsr;
  33 };
  34 
  35 #define CCSR_DMA_MR_BWC_DISABLED        0x0F000000
  36 #define CCSR_DMA_MR_BWC_SHIFT           24
  37 #define CCSR_DMA_MR_BWC_MASK            0x0F000000
  38 #define CCSR_DMA_MR_BWC(x) \
  39         ((ilog2(x) << CCSR_DMA_MR_BWC_SHIFT) & CCSR_DMA_MR_BWC_MASK)
  40 #define CCSR_DMA_MR_EMP_EN              0x00200000
  41 #define CCSR_DMA_MR_EMS_EN              0x00040000
  42 #define CCSR_DMA_MR_DAHTS_MASK          0x00030000
  43 #define CCSR_DMA_MR_DAHTS_1             0x00000000
  44 #define CCSR_DMA_MR_DAHTS_2             0x00010000
  45 #define CCSR_DMA_MR_DAHTS_4             0x00020000
  46 #define CCSR_DMA_MR_DAHTS_8             0x00030000
  47 #define CCSR_DMA_MR_SAHTS_MASK          0x0000C000
  48 #define CCSR_DMA_MR_SAHTS_1             0x00000000
  49 #define CCSR_DMA_MR_SAHTS_2             0x00004000
  50 #define CCSR_DMA_MR_SAHTS_4             0x00008000
  51 #define CCSR_DMA_MR_SAHTS_8             0x0000C000
  52 #define CCSR_DMA_MR_DAHE                0x00002000
  53 #define CCSR_DMA_MR_SAHE                0x00001000
  54 #define CCSR_DMA_MR_SRW                 0x00000400
  55 #define CCSR_DMA_MR_EOSIE               0x00000200
  56 #define CCSR_DMA_MR_EOLNIE              0x00000100
  57 #define CCSR_DMA_MR_EOLSIE              0x00000080
  58 #define CCSR_DMA_MR_EIE                 0x00000040
  59 #define CCSR_DMA_MR_XFE                 0x00000020
  60 #define CCSR_DMA_MR_CDSM_SWSM           0x00000010
  61 #define CCSR_DMA_MR_CA                  0x00000008
  62 #define CCSR_DMA_MR_CTM                 0x00000004
  63 #define CCSR_DMA_MR_CC                  0x00000002
  64 #define CCSR_DMA_MR_CS                  0x00000001
  65 
  66 #define CCSR_DMA_SR_TE                  0x00000080
  67 #define CCSR_DMA_SR_CH                  0x00000020
  68 #define CCSR_DMA_SR_PE                  0x00000010
  69 #define CCSR_DMA_SR_EOLNI               0x00000008
  70 #define CCSR_DMA_SR_CB                  0x00000004
  71 #define CCSR_DMA_SR_EOSI                0x00000002
  72 #define CCSR_DMA_SR_EOLSI               0x00000001
  73 
  74 /* ECLNDAR takes bits 32-36 of the CLNDAR register */
  75 static inline u32 CCSR_DMA_ECLNDAR_ADDR(u64 x)
  76 {
  77         return (x >> 32) & 0xf;
  78 }
  79 
  80 #define CCSR_DMA_CLNDAR_ADDR(x) ((x) & 0xFFFFFFFE)
  81 #define CCSR_DMA_CLNDAR_EOSIE           0x00000008
  82 
  83 /* SATR and DATR, combined */
  84 #define CCSR_DMA_ATR_PBATMU             0x20000000
  85 #define CCSR_DMA_ATR_TFLOWLVL_0         0x00000000
  86 #define CCSR_DMA_ATR_TFLOWLVL_1         0x06000000
  87 #define CCSR_DMA_ATR_TFLOWLVL_2         0x08000000
  88 #define CCSR_DMA_ATR_TFLOWLVL_3         0x0C000000
  89 #define CCSR_DMA_ATR_PCIORDER           0x02000000
  90 #define CCSR_DMA_ATR_SME                0x01000000
  91 #define CCSR_DMA_ATR_NOSNOOP            0x00040000
  92 #define CCSR_DMA_ATR_SNOOP              0x00050000
  93 #define CCSR_DMA_ATR_ESAD_MASK          0x0000000F
  94 
  95 /**
  96  *  List Descriptor for extended chaining mode DMA operations.
  97  *
  98  *  The CLSDAR register points to the first (in a linked-list) List
  99  *  Descriptor.  Each object must be aligned on a 32-byte boundary. Each
 100  *  list descriptor points to a linked-list of link Descriptors.
 101  */
 102 struct fsl_dma_list_descriptor {
 103         __be64 next;            /* Address of next list descriptor */
 104         __be64 first_link;      /* Address of first link descriptor */
 105         __be32 source;          /* Source stride */
 106         __be32 dest;            /* Destination stride */
 107         u8 res[8];              /* Reserved */
 108 } __attribute__ ((aligned(32), packed));
 109 
 110 /**
 111  *  Link Descriptor for basic and extended chaining mode DMA operations.
 112  *
 113  *  A Link Descriptor points to a single DMA buffer.  Each link descriptor
 114  *  must be aligned on a 32-byte boundary.
 115  */
 116 struct fsl_dma_link_descriptor {
 117         __be32 source_attr;     /* Programmed into SATR register */
 118         __be32 source_addr;     /* Programmed into SAR register */
 119         __be32 dest_attr;       /* Programmed into DATR register */
 120         __be32 dest_addr;       /* Programmed into DAR register */
 121         __be64 next;    /* Address of next link descriptor */
 122         __be32 count;   /* Byte count */
 123         u8 res[4];      /* Reserved */
 124 } __attribute__ ((aligned(32), packed));
 125 
 126 #endif