sound/soc/fsl/fsl

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This source file includes following definitions.
fsl_asrc_sel_proc
fsl_asrc_request_pair
fsl_asrc_release_pair
fsl_asrc_set_watermarks
fsl_asrc_cal_asrck_divisor
fsl_asrc_set_ideal_ratio
fsl_asrc_config_pair
fsl_asrc_start_pair
fsl_asrc_stop_pair
fsl_asrc_get_dma_channel
fsl_asrc_dai_startup
fsl_asrc_dai_hw_params
fsl_asrc_dai_hw_free
fsl_asrc_dai_trigger
fsl_asrc_dai_probe
fsl_asrc_readable_reg
fsl_asrc_volatile_reg
fsl_asrc_writeable_reg
fsl_asrc_init
fsl_asrc_isr
fsl_asrc_probe
fsl_asrc_runtime_resume
fsl_asrc_runtime_suspend
fsl_asrc_suspend
fsl_asrc_resume
   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver
   4 //
   5 // Copyright (C) 2014 Freescale Semiconductor, Inc.
   6 //
   7 // Author: Nicolin Chen <nicoleotsuka@gmail.com>
   8 
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/module.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/platform_data/dma-imx.h>
  15 #include <linux/pm_runtime.h>
  16 #include <sound/dmaengine_pcm.h>
  17 #include <sound/pcm_params.h>
  18 
  19 #include "fsl_asrc.h"
  20 
  21 #define IDEAL_RATIO_DECIMAL_DEPTH 26
  22 
  23 #define pair_err(fmt, ...) \
  24         dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
  25 
  26 #define pair_dbg(fmt, ...) \
  27         dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
  28 
  29 /* Corresponding to process_option */
  30 static unsigned int supported_asrc_rate[] = {
  31         5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
  32         64000, 88200, 96000, 128000, 176400, 192000,
  33 };
  34 
  35 static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = {
  36         .count = ARRAY_SIZE(supported_asrc_rate),
  37         .list = supported_asrc_rate,
  38 };
  39 
  40 /**
  41  * The following tables map the relationship between asrc_inclk/asrc_outclk in
  42  * fsl_asrc.h and the registers of ASRCSR
  43  */
  44 static unsigned char input_clk_map_imx35[] = {
  45         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
  46 };
  47 
  48 static unsigned char output_clk_map_imx35[] = {
  49         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
  50 };
  51 
  52 /* i.MX53 uses the same map for input and output */
  53 static unsigned char input_clk_map_imx53[] = {
  54 /*      0x0  0x1  0x2  0x3  0x4  0x5  0x6  0x7  0x8  0x9  0xa  0xb  0xc  0xd  0xe  0xf */
  55         0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
  56 };
  57 
  58 static unsigned char output_clk_map_imx53[] = {
  59 /*      0x0  0x1  0x2  0x3  0x4  0x5  0x6  0x7  0x8  0x9  0xa  0xb  0xc  0xd  0xe  0xf */
  60         0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
  61 };
  62 
  63 static unsigned char *clk_map[2];
  64 
  65 /**
  66  * Select the pre-processing and post-processing options
  67  * Make sure to exclude following unsupported cases before
  68  * calling this function:
  69  * 1) inrate > 8.125 * outrate
  70  * 2) inrate > 16.125 * outrate
  71  *
  72  * inrate: input sample rate
  73  * outrate: output sample rate
  74  * pre_proc: return value for pre-processing option
  75  * post_proc: return value for post-processing option
  76  */
  77 static void fsl_asrc_sel_proc(int inrate, int outrate,
  78                              int *pre_proc, int *post_proc)
  79 {
  80         bool post_proc_cond2;
  81         bool post_proc_cond0;
  82 
  83         /* select pre_proc between [0, 2] */
  84         if (inrate * 8 > 33 * outrate)
  85                 *pre_proc = 2;
  86         else if (inrate * 8 > 15 * outrate) {
  87                 if (inrate > 152000)
  88                         *pre_proc = 2;
  89                 else
  90                         *pre_proc = 1;
  91         } else if (inrate < 76000)
  92                 *pre_proc = 0;
  93         else if (inrate > 152000)
  94                 *pre_proc = 2;
  95         else
  96                 *pre_proc = 1;
  97 
  98         /* Condition for selection of post-processing */
  99         post_proc_cond2 = (inrate * 15 > outrate * 16 && outrate < 56000) ||
 100                           (inrate > 56000 && outrate < 56000);
 101         post_proc_cond0 = inrate * 23 < outrate * 8;
 102 
 103         if (post_proc_cond2)
 104                 *post_proc = 2;
 105         else if (post_proc_cond0)
 106                 *post_proc = 0;
 107         else
 108                 *post_proc = 1;
 109 }
 110 
 111 /**
 112  * Request ASRC pair
 113  *
 114  * It assigns pair by the order of A->C->B because allocation of pair B,
 115  * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
 116  * while pair A and pair C are comparatively independent.
 117  */
 118 static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
 119 {
 120         enum asrc_pair_index index = ASRC_INVALID_PAIR;
 121         struct fsl_asrc *asrc_priv = pair->asrc_priv;
 122         struct device *dev = &asrc_priv->pdev->dev;
 123         unsigned long lock_flags;
 124         int i, ret = 0;
 125 
 126         spin_lock_irqsave(&asrc_priv->lock, lock_flags);
 127 
 128         for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
 129                 if (asrc_priv->pair[i] != NULL)
 130                         continue;
 131 
 132                 index = i;
 133 
 134                 if (i != ASRC_PAIR_B)
 135                         break;
 136         }
 137 
 138         if (index == ASRC_INVALID_PAIR) {
 139                 dev_err(dev, "all pairs are busy now\n");
 140                 ret = -EBUSY;
 141         } else if (asrc_priv->channel_avail < channels) {
 142                 dev_err(dev, "can't afford required channels: %d\n", channels);
 143                 ret = -EINVAL;
 144         } else {
 145                 asrc_priv->channel_avail -= channels;
 146                 asrc_priv->pair[index] = pair;
 147                 pair->channels = channels;
 148                 pair->index = index;
 149         }
 150 
 151         spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
 152 
 153         return ret;
 154 }
 155 
 156 /**
 157  * Release ASRC pair
 158  *
 159  * It clears the resource from asrc_priv and releases the occupied channels.
 160  */
 161 static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
 162 {
 163         struct fsl_asrc *asrc_priv = pair->asrc_priv;
 164         enum asrc_pair_index index = pair->index;
 165         unsigned long lock_flags;
 166 
 167         /* Make sure the pair is disabled */
 168         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
 169                            ASRCTR_ASRCEi_MASK(index), 0);
 170 
 171         spin_lock_irqsave(&asrc_priv->lock, lock_flags);
 172 
 173         asrc_priv->channel_avail += pair->channels;
 174         asrc_priv->pair[index] = NULL;
 175         pair->error = 0;
 176 
 177         spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
 178 }
 179 
 180 /**
 181  * Configure input and output thresholds
 182  */
 183 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
 184 {
 185         struct fsl_asrc *asrc_priv = pair->asrc_priv;
 186         enum asrc_pair_index index = pair->index;
 187 
 188         regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
 189                            ASRMCRi_EXTTHRSHi_MASK |
 190                            ASRMCRi_INFIFO_THRESHOLD_MASK |
 191                            ASRMCRi_OUTFIFO_THRESHOLD_MASK,
 192                            ASRMCRi_EXTTHRSHi |
 193                            ASRMCRi_INFIFO_THRESHOLD(in) |
 194                            ASRMCRi_OUTFIFO_THRESHOLD(out));
 195 }
 196 
 197 /**
 198  * Calculate the total divisor between asrck clock rate and sample rate
 199  *
 200  * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
 201  */
 202 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
 203 {
 204         u32 ps;
 205 
 206         /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */
 207         for (ps = 0; div > 8; ps++)
 208                 div >>= 1;
 209 
 210         return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps;
 211 }
 212 
 213 /**
 214  * Calculate and set the ratio for Ideal Ratio mode only
 215  *
 216  * The ratio is a 32-bit fixed point value with 26 fractional bits.
 217  */
 218 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
 219                                     int inrate, int outrate)
 220 {
 221         struct fsl_asrc *asrc_priv = pair->asrc_priv;
 222         enum asrc_pair_index index = pair->index;
 223         unsigned long ratio;
 224         int i;
 225 
 226         if (!outrate) {
 227                 pair_err("output rate should not be zero\n");
 228                 return -EINVAL;
 229         }
 230 
 231         /* Calculate the intergal part of the ratio */
 232         ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH;
 233 
 234         /* ... and then the 26 depth decimal part */
 235         inrate %= outrate;
 236 
 237         for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) {
 238                 inrate <<= 1;
 239 
 240                 if (inrate < outrate)
 241                         continue;
 242 
 243                 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i);
 244                 inrate -= outrate;
 245 
 246                 if (!inrate)
 247                         break;
 248         }
 249 
 250         regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio);
 251         regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24);
 252 
 253         return 0;
 254 }
 255 
 256 /**
 257  * Configure the assigned ASRC pair
 258  *
 259  * It configures those ASRC registers according to a configuration instance
 260  * of struct asrc_config which includes in/output sample rate, width, channel
 261  * and clock settings.
 262  */
 263 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
 264 {
 265         struct asrc_config *config = pair->config;
 266         struct fsl_asrc *asrc_priv = pair->asrc_priv;
 267         enum asrc_pair_index index = pair->index;
 268         u32 inrate, outrate, indiv, outdiv;
 269         u32 clk_index[2], div[2];
 270         int in, out, channels;
 271         int pre_proc, post_proc;
 272         struct clk *clk;
 273         bool ideal;
 274 
 275         if (!config) {
 276                 pair_err("invalid pair config\n");
 277                 return -EINVAL;
 278         }
 279 
 280         /* Validate channels */
 281         if (config->channel_num < 1 || config->channel_num > 10) {
 282                 pair_err("does not support %d channels\n", config->channel_num);
 283                 return -EINVAL;
 284         }
 285 
 286         /* Validate output width */
 287         if (config->output_word_width == ASRC_WIDTH_8_BIT) {
 288                 pair_err("does not support 8bit width output\n");
 289                 return -EINVAL;
 290         }
 291 
 292         inrate = config->input_sample_rate;
 293         outrate = config->output_sample_rate;
 294         ideal = config->inclk == INCLK_NONE;
 295 
 296         /* Validate input and output sample rates */
 297         for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++)
 298                 if (inrate == supported_asrc_rate[in])
 299                         break;
 300 
 301         if (in == ARRAY_SIZE(supported_asrc_rate)) {
 302                 pair_err("unsupported input sample rate: %dHz\n", inrate);
 303                 return -EINVAL;
 304         }
 305 
 306         for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)
 307                 if (outrate == supported_asrc_rate[out])
 308                         break;
 309 
 310         if (out == ARRAY_SIZE(supported_asrc_rate)) {
 311                 pair_err("unsupported output sample rate: %dHz\n", outrate);
 312                 return -EINVAL;
 313         }
 314 
 315         if ((outrate >= 5512 && outrate <= 30000) &&
 316             (outrate > 24 * inrate || inrate > 8 * outrate)) {
 317                 pair_err("exceed supported ratio range [1/24, 8] for \
 318                                 inrate/outrate: %d/%d\n", inrate, outrate);
 319                 return -EINVAL;
 320         }
 321 
 322         /* Validate input and output clock sources */
 323         clk_index[IN] = clk_map[IN][config->inclk];
 324         clk_index[OUT] = clk_map[OUT][config->outclk];
 325 
 326         /* We only have output clock for ideal ratio mode */
 327         clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
 328 
 329         div[IN] = clk_get_rate(clk) / inrate;
 330         if (div[IN] == 0) {
 331                 pair_err("failed to support input sample rate %dHz by asrck_%x\n",
 332                                 inrate, clk_index[ideal ? OUT : IN]);
 333                 return -EINVAL;
 334         }
 335 
 336         clk = asrc_priv->asrck_clk[clk_index[OUT]];
 337 
 338         /* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */
 339         if (ideal)
 340                 div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE;
 341         else
 342                 div[OUT] = clk_get_rate(clk) / outrate;
 343 
 344         if (div[OUT] == 0) {
 345                 pair_err("failed to support output sample rate %dHz by asrck_%x\n",
 346                                 outrate, clk_index[OUT]);
 347                 return -EINVAL;
 348         }
 349 
 350         /* Set the channel number */
 351         channels = config->channel_num;
 352 
 353         if (asrc_priv->channel_bits < 4)
 354                 channels /= 2;
 355 
 356         /* Update channels for current pair */
 357         regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR,
 358                            ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits),
 359                            ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits));
 360 
 361         /* Default setting: Automatic selection for processing mode */
 362         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
 363                            ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
 364         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
 365                            ASRCTR_USRi_MASK(index), 0);
 366 
 367         /* Set the input and output clock sources */
 368         regmap_update_bits(asrc_priv->regmap, REG_ASRCSR,
 369                            ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
 370                            ASRCSR_AICS(index, clk_index[IN]) |
 371                            ASRCSR_AOCS(index, clk_index[OUT]));
 372 
 373         /* Calculate the input clock divisors */
 374         indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]);
 375         outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
 376 
 377         /* Suppose indiv and outdiv includes prescaler, so add its MASK too */
 378         regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index),
 379                            ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
 380                            ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
 381                            ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
 382 
 383         /* Implement word_width configurations */
 384         regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index),
 385                            ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
 386                            ASRMCR1i_OW16(config->output_word_width) |
 387                            ASRMCR1i_IWD(config->input_word_width));
 388 
 389         /* Enable BUFFER STALL */
 390         regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
 391                            ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
 392 
 393         /* Set default thresholds for input and output FIFO */
 394         fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD,
 395                                 ASRC_INPUTFIFO_THRESHOLD);
 396 
 397         /* Configure the following only for Ideal Ratio mode */
 398         if (!ideal)
 399                 return 0;
 400 
 401         /* Clear ASTSx bit to use Ideal Ratio mode */
 402         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
 403                            ASRCTR_ATSi_MASK(index), 0);
 404 
 405         /* Enable Ideal Ratio mode */
 406         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
 407                            ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
 408                            ASRCTR_IDR(index) | ASRCTR_USR(index));
 409 
 410         fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc);
 411 
 412         /* Apply configurations for pre- and post-processing */
 413         regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
 414                            ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
 415                            ASRCFG_PREMOD(index, pre_proc) |
 416                            ASRCFG_POSTMOD(index, post_proc));
 417 
 418         return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
 419 }
 420 
 421 /**
 422  * Start the assigned ASRC pair
 423  *
 424  * It enables the assigned pair and makes it stopped at the stall level.
 425  */
 426 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
 427 {
 428         struct fsl_asrc *asrc_priv = pair->asrc_priv;
 429         enum asrc_pair_index index = pair->index;
 430         int reg, retry = 10, i;
 431 
 432         /* Enable the current pair */
 433         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
 434                            ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
 435 
 436         /* Wait for status of initialization */
 437         do {
 438                 udelay(5);
 439                 regmap_read(asrc_priv->regmap, REG_ASRCFG, &reg);
 440                 reg &= ASRCFG_INIRQi_MASK(index);
 441         } while (!reg && --retry);
 442 
 443         /* Make the input fifo to ASRC STALL level */
 444         regmap_read(asrc_priv->regmap, REG_ASRCNCR, &reg);
 445         for (i = 0; i < pair->channels * 4; i++)
 446                 regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0);
 447 
 448         /* Enable overload interrupt */
 449         regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE);
 450 }
 451 
 452 /**
 453  * Stop the assigned ASRC pair
 454  */
 455 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
 456 {
 457         struct fsl_asrc *asrc_priv = pair->asrc_priv;
 458         enum asrc_pair_index index = pair->index;
 459 
 460         /* Stop the current pair */
 461         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
 462                            ASRCTR_ASRCEi_MASK(index), 0);
 463 }
 464 
 465 /**
 466  * Get DMA channel according to the pair and direction.
 467  */
 468 struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir)
 469 {
 470         struct fsl_asrc *asrc_priv = pair->asrc_priv;
 471         enum asrc_pair_index index = pair->index;
 472         char name[4];
 473 
 474         sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
 475 
 476         return dma_request_slave_channel(&asrc_priv->pdev->dev, name);
 477 }
 478 EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel);
 479 
 480 static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream,
 481                                 struct snd_soc_dai *dai)
 482 {
 483         struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
 484 
 485         /* Odd channel number is not valid for older ASRC (channel_bits==3) */
 486         if (asrc_priv->channel_bits == 3)
 487                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 488                                            SNDRV_PCM_HW_PARAM_CHANNELS, 2);
 489 
 490 
 491         return snd_pcm_hw_constraint_list(substream->runtime, 0,
 492                         SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints);
 493 }
 494 
 495 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
 496                                   struct snd_pcm_hw_params *params,
 497                                   struct snd_soc_dai *dai)
 498 {
 499         struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
 500         int width = params_width(params);
 501         struct snd_pcm_runtime *runtime = substream->runtime;
 502         struct fsl_asrc_pair *pair = runtime->private_data;
 503         unsigned int channels = params_channels(params);
 504         unsigned int rate = params_rate(params);
 505         struct asrc_config config;
 506         int word_width, ret;
 507 
 508         ret = fsl_asrc_request_pair(channels, pair);
 509         if (ret) {
 510                 dev_err(dai->dev, "fail to request asrc pair\n");
 511                 return ret;
 512         }
 513 
 514         pair->config = &config;
 515 
 516         if (width == 16)
 517                 width = ASRC_WIDTH_16_BIT;
 518         else
 519                 width = ASRC_WIDTH_24_BIT;
 520 
 521         if (asrc_priv->asrc_width == 16)
 522                 word_width = ASRC_WIDTH_16_BIT;
 523         else
 524                 word_width = ASRC_WIDTH_24_BIT;
 525 
 526         config.pair = pair->index;
 527         config.channel_num = channels;
 528         config.inclk = INCLK_NONE;
 529         config.outclk = OUTCLK_ASRCK1_CLK;
 530 
 531         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 532                 config.input_word_width   = width;
 533                 config.output_word_width  = word_width;
 534                 config.input_sample_rate  = rate;
 535                 config.output_sample_rate = asrc_priv->asrc_rate;
 536         } else {
 537                 config.input_word_width   = word_width;
 538                 config.output_word_width  = width;
 539                 config.input_sample_rate  = asrc_priv->asrc_rate;
 540                 config.output_sample_rate = rate;
 541         }
 542 
 543         ret = fsl_asrc_config_pair(pair);
 544         if (ret) {
 545                 dev_err(dai->dev, "fail to config asrc pair\n");
 546                 return ret;
 547         }
 548 
 549         return 0;
 550 }
 551 
 552 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream,
 553                                 struct snd_soc_dai *dai)
 554 {
 555         struct snd_pcm_runtime *runtime = substream->runtime;
 556         struct fsl_asrc_pair *pair = runtime->private_data;
 557 
 558         if (pair)
 559                 fsl_asrc_release_pair(pair);
 560 
 561         return 0;
 562 }
 563 
 564 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 565                                 struct snd_soc_dai *dai)
 566 {
 567         struct snd_pcm_runtime *runtime = substream->runtime;
 568         struct fsl_asrc_pair *pair = runtime->private_data;
 569 
 570         switch (cmd) {
 571         case SNDRV_PCM_TRIGGER_START:
 572         case SNDRV_PCM_TRIGGER_RESUME:
 573         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 574                 fsl_asrc_start_pair(pair);
 575                 break;
 576         case SNDRV_PCM_TRIGGER_STOP:
 577         case SNDRV_PCM_TRIGGER_SUSPEND:
 578         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 579                 fsl_asrc_stop_pair(pair);
 580                 break;
 581         default:
 582                 return -EINVAL;
 583         }
 584 
 585         return 0;
 586 }
 587 
 588 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = {
 589         .startup      = fsl_asrc_dai_startup,
 590         .hw_params    = fsl_asrc_dai_hw_params,
 591         .hw_free      = fsl_asrc_dai_hw_free,
 592         .trigger      = fsl_asrc_dai_trigger,
 593 };
 594 
 595 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
 596 {
 597         struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
 598 
 599         snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx,
 600                                   &asrc_priv->dma_params_rx);
 601 
 602         return 0;
 603 }
 604 
 605 #define FSL_ASRC_FORMATS        (SNDRV_PCM_FMTBIT_S24_LE | \
 606                                  SNDRV_PCM_FMTBIT_S16_LE | \
 607                                  SNDRV_PCM_FMTBIT_S20_3LE)
 608 
 609 static struct snd_soc_dai_driver fsl_asrc_dai = {
 610         .probe = fsl_asrc_dai_probe,
 611         .playback = {
 612                 .stream_name = "ASRC-Playback",
 613                 .channels_min = 1,
 614                 .channels_max = 10,
 615                 .rate_min = 5512,
 616                 .rate_max = 192000,
 617                 .rates = SNDRV_PCM_RATE_KNOT,
 618                 .formats = FSL_ASRC_FORMATS,
 619         },
 620         .capture = {
 621                 .stream_name = "ASRC-Capture",
 622                 .channels_min = 1,
 623                 .channels_max = 10,
 624                 .rate_min = 5512,
 625                 .rate_max = 192000,
 626                 .rates = SNDRV_PCM_RATE_KNOT,
 627                 .formats = FSL_ASRC_FORMATS,
 628         },
 629         .ops = &fsl_asrc_dai_ops,
 630 };
 631 
 632 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg)
 633 {
 634         switch (reg) {
 635         case REG_ASRCTR:
 636         case REG_ASRIER:
 637         case REG_ASRCNCR:
 638         case REG_ASRCFG:
 639         case REG_ASRCSR:
 640         case REG_ASRCDR1:
 641         case REG_ASRCDR2:
 642         case REG_ASRSTR:
 643         case REG_ASRPM1:
 644         case REG_ASRPM2:
 645         case REG_ASRPM3:
 646         case REG_ASRPM4:
 647         case REG_ASRPM5:
 648         case REG_ASRTFR1:
 649         case REG_ASRCCR:
 650         case REG_ASRDOA:
 651         case REG_ASRDOB:
 652         case REG_ASRDOC:
 653         case REG_ASRIDRHA:
 654         case REG_ASRIDRLA:
 655         case REG_ASRIDRHB:
 656         case REG_ASRIDRLB:
 657         case REG_ASRIDRHC:
 658         case REG_ASRIDRLC:
 659         case REG_ASR76K:
 660         case REG_ASR56K:
 661         case REG_ASRMCRA:
 662         case REG_ASRFSTA:
 663         case REG_ASRMCRB:
 664         case REG_ASRFSTB:
 665         case REG_ASRMCRC:
 666         case REG_ASRFSTC:
 667         case REG_ASRMCR1A:
 668         case REG_ASRMCR1B:
 669         case REG_ASRMCR1C:
 670                 return true;
 671         default:
 672                 return false;
 673         }
 674 }
 675 
 676 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg)
 677 {
 678         switch (reg) {
 679         case REG_ASRSTR:
 680         case REG_ASRDIA:
 681         case REG_ASRDIB:
 682         case REG_ASRDIC:
 683         case REG_ASRDOA:
 684         case REG_ASRDOB:
 685         case REG_ASRDOC:
 686         case REG_ASRFSTA:
 687         case REG_ASRFSTB:
 688         case REG_ASRFSTC:
 689         case REG_ASRCFG:
 690                 return true;
 691         default:
 692                 return false;
 693         }
 694 }
 695 
 696 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg)
 697 {
 698         switch (reg) {
 699         case REG_ASRCTR:
 700         case REG_ASRIER:
 701         case REG_ASRCNCR:
 702         case REG_ASRCFG:
 703         case REG_ASRCSR:
 704         case REG_ASRCDR1:
 705         case REG_ASRCDR2:
 706         case REG_ASRSTR:
 707         case REG_ASRPM1:
 708         case REG_ASRPM2:
 709         case REG_ASRPM3:
 710         case REG_ASRPM4:
 711         case REG_ASRPM5:
 712         case REG_ASRTFR1:
 713         case REG_ASRCCR:
 714         case REG_ASRDIA:
 715         case REG_ASRDIB:
 716         case REG_ASRDIC:
 717         case REG_ASRIDRHA:
 718         case REG_ASRIDRLA:
 719         case REG_ASRIDRHB:
 720         case REG_ASRIDRLB:
 721         case REG_ASRIDRHC:
 722         case REG_ASRIDRLC:
 723         case REG_ASR76K:
 724         case REG_ASR56K:
 725         case REG_ASRMCRA:
 726         case REG_ASRMCRB:
 727         case REG_ASRMCRC:
 728         case REG_ASRMCR1A:
 729         case REG_ASRMCR1B:
 730         case REG_ASRMCR1C:
 731                 return true;
 732         default:
 733                 return false;
 734         }
 735 }
 736 
 737 static struct reg_default fsl_asrc_reg[] = {
 738         { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 },
 739         { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 },
 740         { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 },
 741         { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 },
 742         { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 },
 743         { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 },
 744         { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 },
 745         { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 },
 746         { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 },
 747         { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 },
 748         { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 },
 749         { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 },
 750         { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 },
 751         { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 },
 752         { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 },
 753         { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 },
 754         { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 },
 755         { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 },
 756         { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 },
 757         { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 },
 758         { REG_ASRMCR1C, 0x0000 },
 759 };
 760 
 761 static const struct regmap_config fsl_asrc_regmap_config = {
 762         .reg_bits = 32,
 763         .reg_stride = 4,
 764         .val_bits = 32,
 765 
 766         .max_register = REG_ASRMCR1C,
 767         .reg_defaults = fsl_asrc_reg,
 768         .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg),
 769         .readable_reg = fsl_asrc_readable_reg,
 770         .volatile_reg = fsl_asrc_volatile_reg,
 771         .writeable_reg = fsl_asrc_writeable_reg,
 772         .cache_type = REGCACHE_FLAT,
 773 };
 774 
 775 /**
 776  * Initialize ASRC registers with a default configurations
 777  */
 778 static int fsl_asrc_init(struct fsl_asrc *asrc_priv)
 779 {
 780         /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
 781         regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
 782 
 783         /* Disable interrupt by default */
 784         regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0);
 785 
 786         /* Apply recommended settings for parameters from Reference Manual */
 787         regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff);
 788         regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555);
 789         regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280);
 790         regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280);
 791         regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280);
 792 
 793         /* Base address for task queue FIFO. Set to 0x7C */
 794         regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1,
 795                            ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
 796 
 797         /* Set the processing clock for 76KHz to 133M */
 798         regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6);
 799 
 800         /* Set the processing clock for 56KHz to 133M */
 801         return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947);
 802 }
 803 
 804 /**
 805  * Interrupt handler for ASRC
 806  */
 807 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
 808 {
 809         struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id;
 810         struct device *dev = &asrc_priv->pdev->dev;
 811         enum asrc_pair_index index;
 812         u32 status;
 813 
 814         regmap_read(asrc_priv->regmap, REG_ASRSTR, &status);
 815 
 816         /* Clean overload error */
 817         regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE);
 818 
 819         /*
 820          * We here use dev_dbg() for all exceptions because ASRC itself does
 821          * not care if FIFO overflowed or underrun while a warning in the
 822          * interrupt would result a ridged conversion.
 823          */
 824         for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
 825                 if (!asrc_priv->pair[index])
 826                         continue;
 827 
 828                 if (status & ASRSTR_ATQOL) {
 829                         asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
 830                         dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
 831                 }
 832 
 833                 if (status & ASRSTR_AOOL(index)) {
 834                         asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
 835                         pair_dbg("Output Task Overload\n");
 836                 }
 837 
 838                 if (status & ASRSTR_AIOL(index)) {
 839                         asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
 840                         pair_dbg("Input Task Overload\n");
 841                 }
 842 
 843                 if (status & ASRSTR_AODO(index)) {
 844                         asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
 845                         pair_dbg("Output Data Buffer has overflowed\n");
 846                 }
 847 
 848                 if (status & ASRSTR_AIDU(index)) {
 849                         asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
 850                         pair_dbg("Input Data Buffer has underflowed\n");
 851                 }
 852         }
 853 
 854         return IRQ_HANDLED;
 855 }
 856 
 857 static int fsl_asrc_probe(struct platform_device *pdev)
 858 {
 859         struct device_node *np = pdev->dev.of_node;
 860         struct fsl_asrc *asrc_priv;
 861         struct resource *res;
 862         void __iomem *regs;
 863         int irq, ret, i;
 864         char tmp[16];
 865 
 866         asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
 867         if (!asrc_priv)
 868                 return -ENOMEM;
 869 
 870         asrc_priv->pdev = pdev;
 871 
 872         /* Get the addresses and IRQ */
 873         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 874         regs = devm_ioremap_resource(&pdev->dev, res);
 875         if (IS_ERR(regs))
 876                 return PTR_ERR(regs);
 877 
 878         asrc_priv->paddr = res->start;
 879 
 880         asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs,
 881                                                       &fsl_asrc_regmap_config);
 882         if (IS_ERR(asrc_priv->regmap)) {
 883                 dev_err(&pdev->dev, "failed to init regmap\n");
 884                 return PTR_ERR(asrc_priv->regmap);
 885         }
 886 
 887         irq = platform_get_irq(pdev, 0);
 888         if (irq < 0)
 889                 return irq;
 890 
 891         ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
 892                                dev_name(&pdev->dev), asrc_priv);
 893         if (ret) {
 894                 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
 895                 return ret;
 896         }
 897 
 898         asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem");
 899         if (IS_ERR(asrc_priv->mem_clk)) {
 900                 dev_err(&pdev->dev, "failed to get mem clock\n");
 901                 return PTR_ERR(asrc_priv->mem_clk);
 902         }
 903 
 904         asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
 905         if (IS_ERR(asrc_priv->ipg_clk)) {
 906                 dev_err(&pdev->dev, "failed to get ipg clock\n");
 907                 return PTR_ERR(asrc_priv->ipg_clk);
 908         }
 909 
 910         asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba");
 911         if (IS_ERR(asrc_priv->spba_clk))
 912                 dev_warn(&pdev->dev, "failed to get spba clock\n");
 913 
 914         for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
 915                 sprintf(tmp, "asrck_%x", i);
 916                 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
 917                 if (IS_ERR(asrc_priv->asrck_clk[i])) {
 918                         dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
 919                         return PTR_ERR(asrc_priv->asrck_clk[i]);
 920                 }
 921         }
 922 
 923         if (of_device_is_compatible(np, "fsl,imx35-asrc")) {
 924                 asrc_priv->channel_bits = 3;
 925                 clk_map[IN] = input_clk_map_imx35;
 926                 clk_map[OUT] = output_clk_map_imx35;
 927         } else {
 928                 asrc_priv->channel_bits = 4;
 929                 clk_map[IN] = input_clk_map_imx53;
 930                 clk_map[OUT] = output_clk_map_imx53;
 931         }
 932 
 933         ret = fsl_asrc_init(asrc_priv);
 934         if (ret) {
 935                 dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
 936                 return ret;
 937         }
 938 
 939         asrc_priv->channel_avail = 10;
 940 
 941         ret = of_property_read_u32(np, "fsl,asrc-rate",
 942                                    &asrc_priv->asrc_rate);
 943         if (ret) {
 944                 dev_err(&pdev->dev, "failed to get output rate\n");
 945                 return ret;
 946         }
 947 
 948         ret = of_property_read_u32(np, "fsl,asrc-width",
 949                                    &asrc_priv->asrc_width);
 950         if (ret) {
 951                 dev_err(&pdev->dev, "failed to get output width\n");
 952                 return ret;
 953         }
 954 
 955         if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) {
 956                 dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n");
 957                 asrc_priv->asrc_width = 24;
 958         }
 959 
 960         platform_set_drvdata(pdev, asrc_priv);
 961         pm_runtime_enable(&pdev->dev);
 962         spin_lock_init(&asrc_priv->lock);
 963 
 964         ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
 965                                               &fsl_asrc_dai, 1);
 966         if (ret) {
 967                 dev_err(&pdev->dev, "failed to register ASoC DAI\n");
 968                 return ret;
 969         }
 970 
 971         return 0;
 972 }
 973 
 974 #ifdef CONFIG_PM
 975 static int fsl_asrc_runtime_resume(struct device *dev)
 976 {
 977         struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
 978         int i, ret;
 979 
 980         ret = clk_prepare_enable(asrc_priv->mem_clk);
 981         if (ret)
 982                 return ret;
 983         ret = clk_prepare_enable(asrc_priv->ipg_clk);
 984         if (ret)
 985                 goto disable_mem_clk;
 986         if (!IS_ERR(asrc_priv->spba_clk)) {
 987                 ret = clk_prepare_enable(asrc_priv->spba_clk);
 988                 if (ret)
 989                         goto disable_ipg_clk;
 990         }
 991         for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
 992                 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
 993                 if (ret)
 994                         goto disable_asrck_clk;
 995         }
 996 
 997         return 0;
 998 
 999 disable_asrck_clk:
1000         for (i--; i >= 0; i--)
1001                 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
1002         if (!IS_ERR(asrc_priv->spba_clk))
1003                 clk_disable_unprepare(asrc_priv->spba_clk);
1004 disable_ipg_clk:
1005         clk_disable_unprepare(asrc_priv->ipg_clk);
1006 disable_mem_clk:
1007         clk_disable_unprepare(asrc_priv->mem_clk);
1008         return ret;
1009 }
1010 
1011 static int fsl_asrc_runtime_suspend(struct device *dev)
1012 {
1013         struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
1014         int i;
1015 
1016         for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
1017                 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
1018         if (!IS_ERR(asrc_priv->spba_clk))
1019                 clk_disable_unprepare(asrc_priv->spba_clk);
1020         clk_disable_unprepare(asrc_priv->ipg_clk);
1021         clk_disable_unprepare(asrc_priv->mem_clk);
1022 
1023         return 0;
1024 }
1025 #endif /* CONFIG_PM */
1026 
1027 #ifdef CONFIG_PM_SLEEP
1028 static int fsl_asrc_suspend(struct device *dev)
1029 {
1030         struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
1031 
1032         regmap_read(asrc_priv->regmap, REG_ASRCFG,
1033                     &asrc_priv->regcache_cfg);
1034 
1035         regcache_cache_only(asrc_priv->regmap, true);
1036         regcache_mark_dirty(asrc_priv->regmap);
1037 
1038         return 0;
1039 }
1040 
1041 static int fsl_asrc_resume(struct device *dev)
1042 {
1043         struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
1044         u32 asrctr;
1045 
1046         /* Stop all pairs provisionally */
1047         regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr);
1048         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1049                            ASRCTR_ASRCEi_ALL_MASK, 0);
1050 
1051         /* Restore all registers */
1052         regcache_cache_only(asrc_priv->regmap, false);
1053         regcache_sync(asrc_priv->regmap);
1054 
1055         regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
1056                            ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
1057                            ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
1058 
1059         /* Restart enabled pairs */
1060         regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1061                            ASRCTR_ASRCEi_ALL_MASK, asrctr);
1062 
1063         return 0;
1064 }
1065 #endif /* CONFIG_PM_SLEEP */
1066 
1067 static const struct dev_pm_ops fsl_asrc_pm = {
1068         SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
1069         SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume)
1070 };
1071 
1072 static const struct of_device_id fsl_asrc_ids[] = {
1073         { .compatible = "fsl,imx35-asrc", },
1074         { .compatible = "fsl,imx53-asrc", },
1075         {}
1076 };
1077 MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
1078 
1079 static struct platform_driver fsl_asrc_driver = {
1080         .probe = fsl_asrc_probe,
1081         .driver = {
1082                 .name = "fsl-asrc",
1083                 .of_match_table = fsl_asrc_ids,
1084                 .pm = &fsl_asrc_pm,
1085         },
1086 };
1087 module_platform_driver(fsl_asrc_driver);
1088 
1089 MODULE_DESCRIPTION("Freescale ASRC ASoC driver");
1090 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>");
1091 MODULE_ALIAS("platform:fsl-asrc");
1092 MODULE_LICENSE("GPL v2");
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root/sound/soc/fsl/fsl_asrc.c

DEFINITIONS
