root/sound/soc/codecs/rt5670.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * rt5670.h  --  RT5670 ALSA SoC audio driver
   4  *
   5  * Copyright 2014 Realtek Microelectronics
   6  * Author: Bard Liao <bardliao@realtek.com>
   7  */
   8 
   9 #ifndef __RT5670_H__
  10 #define __RT5670_H__
  11 
  12 #include <sound/rt5670.h>
  13 
  14 /* Info */
  15 #define RT5670_RESET                            0x00
  16 #define RT5670_VENDOR_ID                        0xfd
  17 #define RT5670_VENDOR_ID1                       0xfe
  18 #define RT5670_VENDOR_ID2                       0xff
  19 /*  I/O - Output */
  20 #define RT5670_HP_VOL                           0x02
  21 #define RT5670_LOUT1                            0x03
  22 /* I/O - Input */
  23 #define RT5670_CJ_CTRL1                         0x0a
  24 #define RT5670_CJ_CTRL2                         0x0b
  25 #define RT5670_CJ_CTRL3                         0x0c
  26 #define RT5670_IN2                              0x0e
  27 #define RT5670_INL1_INR1_VOL                    0x0f
  28 /* I/O - ADC/DAC/DMIC */
  29 #define RT5670_DAC1_DIG_VOL                     0x19
  30 #define RT5670_DAC2_DIG_VOL                     0x1a
  31 #define RT5670_DAC_CTRL                         0x1b
  32 #define RT5670_STO1_ADC_DIG_VOL                 0x1c
  33 #define RT5670_MONO_ADC_DIG_VOL                 0x1d
  34 #define RT5670_ADC_BST_VOL1                     0x1e
  35 #define RT5670_STO2_ADC_DIG_VOL                 0x1f
  36 /* Mixer - D-D */
  37 #define RT5670_ADC_BST_VOL2                     0x20
  38 #define RT5670_STO2_ADC_MIXER                   0x26
  39 #define RT5670_STO1_ADC_MIXER                   0x27
  40 #define RT5670_MONO_ADC_MIXER                   0x28
  41 #define RT5670_AD_DA_MIXER                      0x29
  42 #define RT5670_STO_DAC_MIXER                    0x2a
  43 #define RT5670_DD_MIXER                         0x2b
  44 #define RT5670_DIG_MIXER                        0x2c
  45 #define RT5670_DSP_PATH1                        0x2d
  46 #define RT5670_DSP_PATH2                        0x2e
  47 #define RT5670_DIG_INF1_DATA                    0x2f
  48 #define RT5670_DIG_INF2_DATA                    0x30
  49 /* Mixer - PDM */
  50 #define RT5670_PDM_OUT_CTRL                     0x31
  51 #define RT5670_PDM_DATA_CTRL1                   0x32
  52 #define RT5670_PDM1_DATA_CTRL2                  0x33
  53 #define RT5670_PDM1_DATA_CTRL3                  0x34
  54 #define RT5670_PDM1_DATA_CTRL4                  0x35
  55 #define RT5670_PDM2_DATA_CTRL2                  0x36
  56 #define RT5670_PDM2_DATA_CTRL3                  0x37
  57 #define RT5670_PDM2_DATA_CTRL4                  0x38
  58 /* Mixer - ADC */
  59 #define RT5670_REC_L1_MIXER                     0x3b
  60 #define RT5670_REC_L2_MIXER                     0x3c
  61 #define RT5670_REC_R1_MIXER                     0x3d
  62 #define RT5670_REC_R2_MIXER                     0x3e
  63 /* Mixer - DAC */
  64 #define RT5670_HPO_MIXER                        0x45
  65 #define RT5670_MONO_MIXER                       0x4c
  66 #define RT5670_OUT_L1_MIXER                     0x4f
  67 #define RT5670_OUT_R1_MIXER                     0x52
  68 #define RT5670_LOUT_MIXER                       0x53
  69 /* Power */
  70 #define RT5670_PWR_DIG1                         0x61
  71 #define RT5670_PWR_DIG2                         0x62
  72 #define RT5670_PWR_ANLG1                        0x63
  73 #define RT5670_PWR_ANLG2                        0x64
  74 #define RT5670_PWR_MIXER                        0x65
  75 #define RT5670_PWR_VOL                          0x66
  76 /* Private Register Control */
  77 #define RT5670_PRIV_INDEX                       0x6a
  78 #define RT5670_PRIV_DATA                        0x6c
  79 /* Format - ADC/DAC */
  80 #define RT5670_I2S4_SDP                         0x6f
  81 #define RT5670_I2S1_SDP                         0x70
  82 #define RT5670_I2S2_SDP                         0x71
  83 #define RT5670_I2S3_SDP                         0x72
  84 #define RT5670_ADDA_CLK1                        0x73
  85 #define RT5670_ADDA_CLK2                        0x74
  86 #define RT5670_DMIC_CTRL1                       0x75
  87 #define RT5670_DMIC_CTRL2                       0x76
  88 /* Format - TDM Control */
  89 #define RT5670_TDM_CTRL_1                       0x77
  90 #define RT5670_TDM_CTRL_2                       0x78
  91 #define RT5670_TDM_CTRL_3                       0x79
  92 
  93 /* Function - Analog */
  94 #define RT5670_DSP_CLK                          0x7f
  95 #define RT5670_GLB_CLK                          0x80
  96 #define RT5670_PLL_CTRL1                        0x81
  97 #define RT5670_PLL_CTRL2                        0x82
  98 #define RT5670_ASRC_1                           0x83
  99 #define RT5670_ASRC_2                           0x84
 100 #define RT5670_ASRC_3                           0x85
 101 #define RT5670_ASRC_4                           0x86
 102 #define RT5670_ASRC_5                           0x87
 103 #define RT5670_ASRC_7                           0x89
 104 #define RT5670_ASRC_8                           0x8a
 105 #define RT5670_ASRC_9                           0x8b
 106 #define RT5670_ASRC_10                          0x8c
 107 #define RT5670_ASRC_11                          0x8d
 108 #define RT5670_DEPOP_M1                         0x8e
 109 #define RT5670_DEPOP_M2                         0x8f
 110 #define RT5670_DEPOP_M3                         0x90
 111 #define RT5670_CHARGE_PUMP                      0x91
 112 #define RT5670_MICBIAS                          0x93
 113 #define RT5670_A_JD_CTRL1                       0x94
 114 #define RT5670_A_JD_CTRL2                       0x95
 115 #define RT5670_ASRC_12                          0x97
 116 #define RT5670_ASRC_13                          0x98
 117 #define RT5670_ASRC_14                          0x99
 118 #define RT5670_VAD_CTRL1                        0x9a
 119 #define RT5670_VAD_CTRL2                        0x9b
 120 #define RT5670_VAD_CTRL3                        0x9c
 121 #define RT5670_VAD_CTRL4                        0x9d
 122 #define RT5670_VAD_CTRL5                        0x9e
 123 /* Function - Digital */
 124 #define RT5670_ADC_EQ_CTRL1                     0xae
 125 #define RT5670_ADC_EQ_CTRL2                     0xaf
 126 #define RT5670_EQ_CTRL1                         0xb0
 127 #define RT5670_EQ_CTRL2                         0xb1
 128 #define RT5670_ALC_DRC_CTRL1                    0xb2
 129 #define RT5670_ALC_DRC_CTRL2                    0xb3
 130 #define RT5670_ALC_CTRL_1                       0xb4
 131 #define RT5670_ALC_CTRL_2                       0xb5
 132 #define RT5670_ALC_CTRL_3                       0xb6
 133 #define RT5670_ALC_CTRL_4                       0xb7
 134 #define RT5670_JD_CTRL                          0xbb
 135 #define RT5670_IRQ_CTRL1                        0xbd
 136 #define RT5670_IRQ_CTRL2                        0xbe
 137 #define RT5670_INT_IRQ_ST                       0xbf
 138 #define RT5670_GPIO_CTRL1                       0xc0
 139 #define RT5670_GPIO_CTRL2                       0xc1
 140 #define RT5670_GPIO_CTRL3                       0xc2
 141 #define RT5670_SCRABBLE_FUN                     0xcd
 142 #define RT5670_SCRABBLE_CTRL                    0xce
 143 #define RT5670_BASE_BACK                        0xcf
 144 #define RT5670_MP3_PLUS1                        0xd0
 145 #define RT5670_MP3_PLUS2                        0xd1
 146 #define RT5670_ADJ_HPF1                         0xd3
 147 #define RT5670_ADJ_HPF2                         0xd4
 148 #define RT5670_HP_CALIB_AMP_DET                 0xd6
 149 #define RT5670_SV_ZCD1                          0xd9
 150 #define RT5670_SV_ZCD2                          0xda
 151 #define RT5670_IL_CMD                           0xdb
 152 #define RT5670_IL_CMD2                          0xdc
 153 #define RT5670_IL_CMD3                          0xdd
 154 #define RT5670_DRC_HL_CTRL1                     0xe6
 155 #define RT5670_DRC_HL_CTRL2                     0xe7
 156 #define RT5670_ADC_MONO_HP_CTRL1                0xec
 157 #define RT5670_ADC_MONO_HP_CTRL2                0xed
 158 #define RT5670_ADC_STO2_HP_CTRL1                0xee
 159 #define RT5670_ADC_STO2_HP_CTRL2                0xef
 160 #define RT5670_JD_CTRL3                         0xf8
 161 #define RT5670_JD_CTRL4                         0xf9
 162 /* General Control */
 163 #define RT5670_DIG_MISC                         0xfa
 164 #define RT5670_GEN_CTRL2                        0xfb
 165 #define RT5670_GEN_CTRL3                        0xfc
 166 
 167 
 168 /* Index of Codec Private Register definition */
 169 #define RT5670_DIG_VOL                          0x00
 170 #define RT5670_PR_ALC_CTRL_1                    0x01
 171 #define RT5670_PR_ALC_CTRL_2                    0x02
 172 #define RT5670_PR_ALC_CTRL_3                    0x03
 173 #define RT5670_PR_ALC_CTRL_4                    0x04
 174 #define RT5670_PR_ALC_CTRL_5                    0x05
 175 #define RT5670_PR_ALC_CTRL_6                    0x06
 176 #define RT5670_BIAS_CUR1                        0x12
 177 #define RT5670_BIAS_CUR3                        0x14
 178 #define RT5670_CLSD_INT_REG1                    0x1c
 179 #define RT5670_MAMP_INT_REG2                    0x37
 180 #define RT5670_CHOP_DAC_ADC                     0x3d
 181 #define RT5670_MIXER_INT_REG                    0x3f
 182 #define RT5670_3D_SPK                           0x63
 183 #define RT5670_WND_1                            0x6c
 184 #define RT5670_WND_2                            0x6d
 185 #define RT5670_WND_3                            0x6e
 186 #define RT5670_WND_4                            0x6f
 187 #define RT5670_WND_5                            0x70
 188 #define RT5670_WND_8                            0x73
 189 #define RT5670_DIP_SPK_INF                      0x75
 190 #define RT5670_HP_DCC_INT1                      0x77
 191 #define RT5670_EQ_BW_LOP                        0xa0
 192 #define RT5670_EQ_GN_LOP                        0xa1
 193 #define RT5670_EQ_FC_BP1                        0xa2
 194 #define RT5670_EQ_BW_BP1                        0xa3
 195 #define RT5670_EQ_GN_BP1                        0xa4
 196 #define RT5670_EQ_FC_BP2                        0xa5
 197 #define RT5670_EQ_BW_BP2                        0xa6
 198 #define RT5670_EQ_GN_BP2                        0xa7
 199 #define RT5670_EQ_FC_BP3                        0xa8
 200 #define RT5670_EQ_BW_BP3                        0xa9
 201 #define RT5670_EQ_GN_BP3                        0xaa
 202 #define RT5670_EQ_FC_BP4                        0xab
 203 #define RT5670_EQ_BW_BP4                        0xac
 204 #define RT5670_EQ_GN_BP4                        0xad
 205 #define RT5670_EQ_FC_HIP1                       0xae
 206 #define RT5670_EQ_GN_HIP1                       0xaf
 207 #define RT5670_EQ_FC_HIP2                       0xb0
 208 #define RT5670_EQ_BW_HIP2                       0xb1
 209 #define RT5670_EQ_GN_HIP2                       0xb2
 210 #define RT5670_EQ_PRE_VOL                       0xb3
 211 #define RT5670_EQ_PST_VOL                       0xb4
 212 
 213 
 214 /* global definition */
 215 #define RT5670_L_MUTE                           (0x1 << 15)
 216 #define RT5670_L_MUTE_SFT                       15
 217 #define RT5670_VOL_L_MUTE                       (0x1 << 14)
 218 #define RT5670_VOL_L_SFT                        14
 219 #define RT5670_R_MUTE                           (0x1 << 7)
 220 #define RT5670_R_MUTE_SFT                       7
 221 #define RT5670_VOL_R_MUTE                       (0x1 << 6)
 222 #define RT5670_VOL_R_SFT                        6
 223 #define RT5670_L_VOL_MASK                       (0x3f << 8)
 224 #define RT5670_L_VOL_SFT                        8
 225 #define RT5670_R_VOL_MASK                       (0x3f)
 226 #define RT5670_R_VOL_SFT                        0
 227 
 228 /* SW Reset & Device ID (0x00) */
 229 #define RT5670_ID_MASK                          (0x3 << 1)
 230 #define RT5670_ID_5670                          (0x0 << 1)
 231 #define RT5670_ID_5672                          (0x1 << 1)
 232 #define RT5670_ID_5671                          (0x2 << 1)
 233 
 234 /* Combo Jack Control 1 (0x0a) */
 235 #define RT5670_CBJ_BST1_MASK                    (0xf << 12)
 236 #define RT5670_CBJ_BST1_SFT                     (12)
 237 #define RT5670_CBJ_JD_HP_EN                     (0x1 << 9)
 238 #define RT5670_CBJ_JD_MIC_EN                    (0x1 << 8)
 239 #define RT5670_CBJ_BST1_EN                      (0x1 << 2)
 240 
 241 /* Combo Jack Control 1 (0x0b) */
 242 #define RT5670_CBJ_MN_JD                        (0x1 << 12)
 243 #define RT5670_CAPLESS_EN                       (0x1 << 11)
 244 #define RT5670_CBJ_DET_MODE                     (0x1 << 7)
 245 
 246 /* IN2 Control (0x0e) */
 247 #define RT5670_BST_MASK1                        (0xf<<12)
 248 #define RT5670_BST_SFT1                         12
 249 #define RT5670_BST_MASK2                        (0xf<<8)
 250 #define RT5670_BST_SFT2                         8
 251 #define RT5670_IN_DF1                           (0x1 << 7)
 252 #define RT5670_IN_SFT1                          7
 253 #define RT5670_IN_DF2                           (0x1 << 6)
 254 #define RT5670_IN_SFT2                          6
 255 
 256 /* INL and INR Volume Control (0x0f) */
 257 #define RT5670_INL_SEL_MASK                     (0x1 << 15)
 258 #define RT5670_INL_SEL_SFT                      15
 259 #define RT5670_INL_SEL_IN4P                     (0x0 << 15)
 260 #define RT5670_INL_SEL_MONOP                    (0x1 << 15)
 261 #define RT5670_INL_VOL_MASK                     (0x1f << 8)
 262 #define RT5670_INL_VOL_SFT                      8
 263 #define RT5670_INR_SEL_MASK                     (0x1 << 7)
 264 #define RT5670_INR_SEL_SFT                      7
 265 #define RT5670_INR_SEL_IN4N                     (0x0 << 7)
 266 #define RT5670_INR_SEL_MONON                    (0x1 << 7)
 267 #define RT5670_INR_VOL_MASK                     (0x1f)
 268 #define RT5670_INR_VOL_SFT                      0
 269 
 270 /* Sidetone Control (0x18) */
 271 #define RT5670_ST_SEL_MASK                      (0x7 << 9)
 272 #define RT5670_ST_SEL_SFT                       9
 273 #define RT5670_M_ST_DACR2                       (0x1 << 8)
 274 #define RT5670_M_ST_DACR2_SFT                   8
 275 #define RT5670_M_ST_DACL2                       (0x1 << 7)
 276 #define RT5670_M_ST_DACL2_SFT                   7
 277 #define RT5670_ST_EN                            (0x1 << 6)
 278 #define RT5670_ST_EN_SFT                        6
 279 
 280 /* DAC1 Digital Volume (0x19) */
 281 #define RT5670_DAC_L1_VOL_MASK                  (0xff << 8)
 282 #define RT5670_DAC_L1_VOL_SFT                   8
 283 #define RT5670_DAC_R1_VOL_MASK                  (0xff)
 284 #define RT5670_DAC_R1_VOL_SFT                   0
 285 
 286 /* DAC2 Digital Volume (0x1a) */
 287 #define RT5670_DAC_L2_VOL_MASK                  (0xff << 8)
 288 #define RT5670_DAC_L2_VOL_SFT                   8
 289 #define RT5670_DAC_R2_VOL_MASK                  (0xff)
 290 #define RT5670_DAC_R2_VOL_SFT                   0
 291 
 292 /* DAC2 Control (0x1b) */
 293 #define RT5670_M_DAC_L2_VOL                     (0x1 << 13)
 294 #define RT5670_M_DAC_L2_VOL_SFT                 13
 295 #define RT5670_M_DAC_R2_VOL                     (0x1 << 12)
 296 #define RT5670_M_DAC_R2_VOL_SFT                 12
 297 #define RT5670_DAC2_L_SEL_MASK                  (0x7 << 4)
 298 #define RT5670_DAC2_L_SEL_SFT                   4
 299 #define RT5670_DAC2_R_SEL_MASK                  (0x7 << 0)
 300 #define RT5670_DAC2_R_SEL_SFT                   0
 301 
 302 /* ADC Digital Volume Control (0x1c) */
 303 #define RT5670_ADC_L_VOL_MASK                   (0x7f << 8)
 304 #define RT5670_ADC_L_VOL_SFT                    8
 305 #define RT5670_ADC_R_VOL_MASK                   (0x7f)
 306 #define RT5670_ADC_R_VOL_SFT                    0
 307 
 308 /* Mono ADC Digital Volume Control (0x1d) */
 309 #define RT5670_MONO_ADC_L_VOL_MASK              (0x7f << 8)
 310 #define RT5670_MONO_ADC_L_VOL_SFT               8
 311 #define RT5670_MONO_ADC_R_VOL_MASK              (0x7f)
 312 #define RT5670_MONO_ADC_R_VOL_SFT               0
 313 
 314 /* ADC Boost Volume Control (0x1e) */
 315 #define RT5670_STO1_ADC_L_BST_MASK              (0x3 << 14)
 316 #define RT5670_STO1_ADC_L_BST_SFT               14
 317 #define RT5670_STO1_ADC_R_BST_MASK              (0x3 << 12)
 318 #define RT5670_STO1_ADC_R_BST_SFT               12
 319 #define RT5670_STO1_ADC_COMP_MASK               (0x3 << 10)
 320 #define RT5670_STO1_ADC_COMP_SFT                10
 321 #define RT5670_STO2_ADC_L_BST_MASK              (0x3 << 8)
 322 #define RT5670_STO2_ADC_L_BST_SFT               8
 323 #define RT5670_STO2_ADC_R_BST_MASK              (0x3 << 6)
 324 #define RT5670_STO2_ADC_R_BST_SFT               6
 325 #define RT5670_STO2_ADC_COMP_MASK               (0x3 << 4)
 326 #define RT5670_STO2_ADC_COMP_SFT                4
 327 
 328 /* Stereo2 ADC Mixer Control (0x26) */
 329 #define RT5670_STO2_ADC_SRC_MASK                (0x1 << 15)
 330 #define RT5670_STO2_ADC_SRC_SFT                 15
 331 
 332 /* Stereo ADC Mixer Control (0x26 0x27) */
 333 #define RT5670_M_ADC_L1                         (0x1 << 14)
 334 #define RT5670_M_ADC_L1_SFT                     14
 335 #define RT5670_M_ADC_L2                         (0x1 << 13)
 336 #define RT5670_M_ADC_L2_SFT                     13
 337 #define RT5670_ADC_1_SRC_MASK                   (0x1 << 12)
 338 #define RT5670_ADC_1_SRC_SFT                    12
 339 #define RT5670_ADC_1_SRC_ADC                    (0x1 << 12)
 340 #define RT5670_ADC_1_SRC_DACMIX                 (0x0 << 12)
 341 #define RT5670_ADC_2_SRC_MASK                   (0x1 << 11)
 342 #define RT5670_ADC_2_SRC_SFT                    11
 343 #define RT5670_ADC_SRC_MASK                     (0x1 << 10)
 344 #define RT5670_ADC_SRC_SFT                      10
 345 #define RT5670_DMIC_SRC_MASK                    (0x3 << 8)
 346 #define RT5670_DMIC_SRC_SFT                     8
 347 #define RT5670_M_ADC_R1                         (0x1 << 6)
 348 #define RT5670_M_ADC_R1_SFT                     6
 349 #define RT5670_M_ADC_R2                         (0x1 << 5)
 350 #define RT5670_M_ADC_R2_SFT                     5
 351 #define RT5670_DMIC3_SRC_MASK                   (0x1 << 1)
 352 #define RT5670_DMIC3_SRC_SFT                    0
 353 
 354 /* Mono ADC Mixer Control (0x28) */
 355 #define RT5670_M_MONO_ADC_L1                    (0x1 << 14)
 356 #define RT5670_M_MONO_ADC_L1_SFT                14
 357 #define RT5670_M_MONO_ADC_L2                    (0x1 << 13)
 358 #define RT5670_M_MONO_ADC_L2_SFT                13
 359 #define RT5670_MONO_ADC_L1_SRC_MASK             (0x1 << 12)
 360 #define RT5670_MONO_ADC_L1_SRC_SFT              12
 361 #define RT5670_MONO_ADC_L1_SRC_DACMIXL          (0x0 << 12)
 362 #define RT5670_MONO_ADC_L1_SRC_ADCL             (0x1 << 12)
 363 #define RT5670_MONO_ADC_L2_SRC_MASK             (0x1 << 11)
 364 #define RT5670_MONO_ADC_L2_SRC_SFT              11
 365 #define RT5670_MONO_ADC_L_SRC_MASK              (0x1 << 10)
 366 #define RT5670_MONO_ADC_L_SRC_SFT               10
 367 #define RT5670_MONO_DMIC_L_SRC_MASK             (0x3 << 8)
 368 #define RT5670_MONO_DMIC_L_SRC_SFT              8
 369 #define RT5670_M_MONO_ADC_R1                    (0x1 << 6)
 370 #define RT5670_M_MONO_ADC_R1_SFT                6
 371 #define RT5670_M_MONO_ADC_R2                    (0x1 << 5)
 372 #define RT5670_M_MONO_ADC_R2_SFT                5
 373 #define RT5670_MONO_ADC_R1_SRC_MASK             (0x1 << 4)
 374 #define RT5670_MONO_ADC_R1_SRC_SFT              4
 375 #define RT5670_MONO_ADC_R1_SRC_ADCR             (0x1 << 4)
 376 #define RT5670_MONO_ADC_R1_SRC_DACMIXR          (0x0 << 4)
 377 #define RT5670_MONO_ADC_R2_SRC_MASK             (0x1 << 3)
 378 #define RT5670_MONO_ADC_R2_SRC_SFT              3
 379 #define RT5670_MONO_DMIC_R_SRC_MASK             (0x3)
 380 #define RT5670_MONO_DMIC_R_SRC_SFT              0
 381 
 382 /* ADC Mixer to DAC Mixer Control (0x29) */
 383 #define RT5670_M_ADCMIX_L                       (0x1 << 15)
 384 #define RT5670_M_ADCMIX_L_SFT                   15
 385 #define RT5670_M_DAC1_L                         (0x1 << 14)
 386 #define RT5670_M_DAC1_L_SFT                     14
 387 #define RT5670_DAC1_R_SEL_MASK                  (0x3 << 10)
 388 #define RT5670_DAC1_R_SEL_SFT                   10
 389 #define RT5670_DAC1_R_SEL_IF1                   (0x0 << 10)
 390 #define RT5670_DAC1_R_SEL_IF2                   (0x1 << 10)
 391 #define RT5670_DAC1_R_SEL_IF3                   (0x2 << 10)
 392 #define RT5670_DAC1_R_SEL_IF4                   (0x3 << 10)
 393 #define RT5670_DAC1_L_SEL_MASK                  (0x3 << 8)
 394 #define RT5670_DAC1_L_SEL_SFT                   8
 395 #define RT5670_DAC1_L_SEL_IF1                   (0x0 << 8)
 396 #define RT5670_DAC1_L_SEL_IF2                   (0x1 << 8)
 397 #define RT5670_DAC1_L_SEL_IF3                   (0x2 << 8)
 398 #define RT5670_DAC1_L_SEL_IF4                   (0x3 << 8)
 399 #define RT5670_M_ADCMIX_R                       (0x1 << 7)
 400 #define RT5670_M_ADCMIX_R_SFT                   7
 401 #define RT5670_M_DAC1_R                         (0x1 << 6)
 402 #define RT5670_M_DAC1_R_SFT                     6
 403 
 404 /* Stereo DAC Mixer Control (0x2a) */
 405 #define RT5670_M_DAC_L1                         (0x1 << 14)
 406 #define RT5670_M_DAC_L1_SFT                     14
 407 #define RT5670_DAC_L1_STO_L_VOL_MASK            (0x1 << 13)
 408 #define RT5670_DAC_L1_STO_L_VOL_SFT             13
 409 #define RT5670_M_DAC_L2                         (0x1 << 12)
 410 #define RT5670_M_DAC_L2_SFT                     12
 411 #define RT5670_DAC_L2_STO_L_VOL_MASK            (0x1 << 11)
 412 #define RT5670_DAC_L2_STO_L_VOL_SFT             11
 413 #define RT5670_M_DAC_R1_STO_L                   (0x1 << 9)
 414 #define RT5670_M_DAC_R1_STO_L_SFT               9
 415 #define RT5670_DAC_R1_STO_L_VOL_MASK            (0x1 << 8)
 416 #define RT5670_DAC_R1_STO_L_VOL_SFT             8
 417 #define RT5670_M_DAC_R1                         (0x1 << 6)
 418 #define RT5670_M_DAC_R1_SFT                     6
 419 #define RT5670_DAC_R1_STO_R_VOL_MASK            (0x1 << 5)
 420 #define RT5670_DAC_R1_STO_R_VOL_SFT             5
 421 #define RT5670_M_DAC_R2                         (0x1 << 4)
 422 #define RT5670_M_DAC_R2_SFT                     4
 423 #define RT5670_DAC_R2_STO_R_VOL_MASK            (0x1 << 3)
 424 #define RT5670_DAC_R2_STO_R_VOL_SFT             3
 425 #define RT5670_M_DAC_L1_STO_R                   (0x1 << 1)
 426 #define RT5670_M_DAC_L1_STO_R_SFT               1
 427 #define RT5670_DAC_L1_STO_R_VOL_MASK            (0x1)
 428 #define RT5670_DAC_L1_STO_R_VOL_SFT             0
 429 
 430 /* Mono DAC Mixer Control (0x2b) */
 431 #define RT5670_M_DAC_L1_MONO_L                  (0x1 << 14)
 432 #define RT5670_M_DAC_L1_MONO_L_SFT              14
 433 #define RT5670_DAC_L1_MONO_L_VOL_MASK           (0x1 << 13)
 434 #define RT5670_DAC_L1_MONO_L_VOL_SFT            13
 435 #define RT5670_M_DAC_L2_MONO_L                  (0x1 << 12)
 436 #define RT5670_M_DAC_L2_MONO_L_SFT              12
 437 #define RT5670_DAC_L2_MONO_L_VOL_MASK           (0x1 << 11)
 438 #define RT5670_DAC_L2_MONO_L_VOL_SFT            11
 439 #define RT5670_M_DAC_R2_MONO_L                  (0x1 << 10)
 440 #define RT5670_M_DAC_R2_MONO_L_SFT              10
 441 #define RT5670_DAC_R2_MONO_L_VOL_MASK           (0x1 << 9)
 442 #define RT5670_DAC_R2_MONO_L_VOL_SFT            9
 443 #define RT5670_M_DAC_R1_MONO_R                  (0x1 << 6)
 444 #define RT5670_M_DAC_R1_MONO_R_SFT              6
 445 #define RT5670_DAC_R1_MONO_R_VOL_MASK           (0x1 << 5)
 446 #define RT5670_DAC_R1_MONO_R_VOL_SFT            5
 447 #define RT5670_M_DAC_R2_MONO_R                  (0x1 << 4)
 448 #define RT5670_M_DAC_R2_MONO_R_SFT              4
 449 #define RT5670_DAC_R2_MONO_R_VOL_MASK           (0x1 << 3)
 450 #define RT5670_DAC_R2_MONO_R_VOL_SFT            3
 451 #define RT5670_M_DAC_L2_MONO_R                  (0x1 << 2)
 452 #define RT5670_M_DAC_L2_MONO_R_SFT              2
 453 #define RT5670_DAC_L2_MONO_R_VOL_MASK           (0x1 << 1)
 454 #define RT5670_DAC_L2_MONO_R_VOL_SFT            1
 455 
 456 /* Digital Mixer Control (0x2c) */
 457 #define RT5670_M_STO_L_DAC_L                    (0x1 << 15)
 458 #define RT5670_M_STO_L_DAC_L_SFT                15
 459 #define RT5670_STO_L_DAC_L_VOL_MASK             (0x1 << 14)
 460 #define RT5670_STO_L_DAC_L_VOL_SFT              14
 461 #define RT5670_M_DAC_L2_DAC_L                   (0x1 << 13)
 462 #define RT5670_M_DAC_L2_DAC_L_SFT               13
 463 #define RT5670_DAC_L2_DAC_L_VOL_MASK            (0x1 << 12)
 464 #define RT5670_DAC_L2_DAC_L_VOL_SFT             12
 465 #define RT5670_M_STO_R_DAC_R                    (0x1 << 11)
 466 #define RT5670_M_STO_R_DAC_R_SFT                11
 467 #define RT5670_STO_R_DAC_R_VOL_MASK             (0x1 << 10)
 468 #define RT5670_STO_R_DAC_R_VOL_SFT              10
 469 #define RT5670_M_DAC_R2_DAC_R                   (0x1 << 9)
 470 #define RT5670_M_DAC_R2_DAC_R_SFT               9
 471 #define RT5670_DAC_R2_DAC_R_VOL_MASK            (0x1 << 8)
 472 #define RT5670_DAC_R2_DAC_R_VOL_SFT             8
 473 #define RT5670_M_DAC_R2_DAC_L                   (0x1 << 7)
 474 #define RT5670_M_DAC_R2_DAC_L_SFT               7
 475 #define RT5670_DAC_R2_DAC_L_VOL_MASK            (0x1 << 6)
 476 #define RT5670_DAC_R2_DAC_L_VOL_SFT             6
 477 #define RT5670_M_DAC_L2_DAC_R                   (0x1 << 5)
 478 #define RT5670_M_DAC_L2_DAC_R_SFT               5
 479 #define RT5670_DAC_L2_DAC_R_VOL_MASK            (0x1 << 4)
 480 #define RT5670_DAC_L2_DAC_R_VOL_SFT             4
 481 
 482 /* DSP Path Control 1 (0x2d) */
 483 #define RT5670_RXDP_SEL_MASK                    (0x7 << 13)
 484 #define RT5670_RXDP_SEL_SFT                     13
 485 #define RT5670_RXDP_SRC_MASK                    (0x3 << 11)
 486 #define RT5670_RXDP_SRC_SFT                     11
 487 #define RT5670_RXDP_SRC_NOR                     (0x0 << 11)
 488 #define RT5670_RXDP_SRC_DIV2                    (0x1 << 11)
 489 #define RT5670_RXDP_SRC_DIV3                    (0x2 << 11)
 490 #define RT5670_TXDP_SRC_MASK                    (0x3 << 4)
 491 #define RT5670_TXDP_SRC_SFT                     4
 492 #define RT5670_TXDP_SRC_NOR                     (0x0 << 4)
 493 #define RT5670_TXDP_SRC_DIV2                    (0x1 << 4)
 494 #define RT5670_TXDP_SRC_DIV3                    (0x2 << 4)
 495 #define RT5670_TXDP_SLOT_SEL_MASK               (0x3 << 2)
 496 #define RT5670_TXDP_SLOT_SEL_SFT                2
 497 #define RT5670_DSP_UL_SEL                       (0x1 << 1)
 498 #define RT5670_DSP_UL_SFT                       1
 499 #define RT5670_DSP_DL_SEL                       0x1
 500 #define RT5670_DSP_DL_SFT                       0
 501 
 502 /* DSP Path Control 2 (0x2e) */
 503 #define RT5670_TXDP_L_VOL_MASK                  (0x7f << 8)
 504 #define RT5670_TXDP_L_VOL_SFT                   8
 505 #define RT5670_TXDP_R_VOL_MASK                  (0x7f)
 506 #define RT5670_TXDP_R_VOL_SFT                   0
 507 
 508 /* Digital Interface Data Control (0x2f) */
 509 #define RT5670_IF1_ADC2_IN_SEL                  (0x1 << 15)
 510 #define RT5670_IF1_ADC2_IN_SFT                  15
 511 #define RT5670_IF2_ADC_IN_MASK                  (0x7 << 12)
 512 #define RT5670_IF2_ADC_IN_SFT                   12
 513 #define RT5670_IF2_DAC_SEL_MASK                 (0x3 << 10)
 514 #define RT5670_IF2_DAC_SEL_SFT                  10
 515 #define RT5670_IF2_ADC_SEL_MASK                 (0x3 << 8)
 516 #define RT5670_IF2_ADC_SEL_SFT                  8
 517 
 518 /* Digital Interface Data Control (0x30) */
 519 #define RT5670_IF4_ADC_IN_MASK                  (0x3 << 4)
 520 #define RT5670_IF4_ADC_IN_SFT                   4
 521 
 522 /* PDM Output Control (0x31) */
 523 #define RT5670_PDM1_L_MASK                      (0x1 << 15)
 524 #define RT5670_PDM1_L_SFT                       15
 525 #define RT5670_M_PDM1_L                         (0x1 << 14)
 526 #define RT5670_M_PDM1_L_SFT                     14
 527 #define RT5670_PDM1_R_MASK                      (0x1 << 13)
 528 #define RT5670_PDM1_R_SFT                       13
 529 #define RT5670_M_PDM1_R                         (0x1 << 12)
 530 #define RT5670_M_PDM1_R_SFT                     12
 531 #define RT5670_PDM2_L_MASK                      (0x1 << 11)
 532 #define RT5670_PDM2_L_SFT                       11
 533 #define RT5670_M_PDM2_L                         (0x1 << 10)
 534 #define RT5670_M_PDM2_L_SFT                     10
 535 #define RT5670_PDM2_R_MASK                      (0x1 << 9)
 536 #define RT5670_PDM2_R_SFT                       9
 537 #define RT5670_M_PDM2_R                         (0x1 << 8)
 538 #define RT5670_M_PDM2_R_SFT                     8
 539 #define RT5670_PDM2_BUSY                        (0x1 << 7)
 540 #define RT5670_PDM1_BUSY                        (0x1 << 6)
 541 #define RT5670_PDM_PATTERN                      (0x1 << 5)
 542 #define RT5670_PDM_GAIN                         (0x1 << 4)
 543 #define RT5670_PDM_DIV_MASK                     (0x3)
 544 
 545 /* REC Left Mixer Control 1 (0x3b) */
 546 #define RT5670_G_HP_L_RM_L_MASK                 (0x7 << 13)
 547 #define RT5670_G_HP_L_RM_L_SFT                  13
 548 #define RT5670_G_IN_L_RM_L_MASK                 (0x7 << 10)
 549 #define RT5670_G_IN_L_RM_L_SFT                  10
 550 #define RT5670_G_BST4_RM_L_MASK                 (0x7 << 7)
 551 #define RT5670_G_BST4_RM_L_SFT                  7
 552 #define RT5670_G_BST3_RM_L_MASK                 (0x7 << 4)
 553 #define RT5670_G_BST3_RM_L_SFT                  4
 554 #define RT5670_G_BST2_RM_L_MASK                 (0x7 << 1)
 555 #define RT5670_G_BST2_RM_L_SFT                  1
 556 
 557 /* REC Left Mixer Control 2 (0x3c) */
 558 #define RT5670_G_BST1_RM_L_MASK                 (0x7 << 13)
 559 #define RT5670_G_BST1_RM_L_SFT                  13
 560 #define RT5670_M_IN_L_RM_L                      (0x1 << 5)
 561 #define RT5670_M_IN_L_RM_L_SFT                  5
 562 #define RT5670_M_BST2_RM_L                      (0x1 << 3)
 563 #define RT5670_M_BST2_RM_L_SFT                  3
 564 #define RT5670_M_BST1_RM_L                      (0x1 << 1)
 565 #define RT5670_M_BST1_RM_L_SFT                  1
 566 
 567 /* REC Right Mixer Control 1 (0x3d) */
 568 #define RT5670_G_HP_R_RM_R_MASK                 (0x7 << 13)
 569 #define RT5670_G_HP_R_RM_R_SFT                  13
 570 #define RT5670_G_IN_R_RM_R_MASK                 (0x7 << 10)
 571 #define RT5670_G_IN_R_RM_R_SFT                  10
 572 #define RT5670_G_BST4_RM_R_MASK                 (0x7 << 7)
 573 #define RT5670_G_BST4_RM_R_SFT                  7
 574 #define RT5670_G_BST3_RM_R_MASK                 (0x7 << 4)
 575 #define RT5670_G_BST3_RM_R_SFT                  4
 576 #define RT5670_G_BST2_RM_R_MASK                 (0x7 << 1)
 577 #define RT5670_G_BST2_RM_R_SFT                  1
 578 
 579 /* REC Right Mixer Control 2 (0x3e) */
 580 #define RT5670_G_BST1_RM_R_MASK                 (0x7 << 13)
 581 #define RT5670_G_BST1_RM_R_SFT                  13
 582 #define RT5670_M_IN_R_RM_R                      (0x1 << 5)
 583 #define RT5670_M_IN_R_RM_R_SFT                  5
 584 #define RT5670_M_BST2_RM_R                      (0x1 << 3)
 585 #define RT5670_M_BST2_RM_R_SFT                  3
 586 #define RT5670_M_BST1_RM_R                      (0x1 << 1)
 587 #define RT5670_M_BST1_RM_R_SFT                  1
 588 
 589 /* HPMIX Control (0x45) */
 590 #define RT5670_M_DAC2_HM                        (0x1 << 15)
 591 #define RT5670_M_DAC2_HM_SFT                    15
 592 #define RT5670_M_HPVOL_HM                       (0x1 << 14)
 593 #define RT5670_M_HPVOL_HM_SFT                   14
 594 #define RT5670_M_DAC1_HM                        (0x1 << 13)
 595 #define RT5670_M_DAC1_HM_SFT                    13
 596 #define RT5670_G_HPOMIX_MASK                    (0x1 << 12)
 597 #define RT5670_G_HPOMIX_SFT                     12
 598 #define RT5670_M_INR1_HMR                       (0x1 << 3)
 599 #define RT5670_M_INR1_HMR_SFT                   3
 600 #define RT5670_M_DACR1_HMR                      (0x1 << 2)
 601 #define RT5670_M_DACR1_HMR_SFT                  2
 602 #define RT5670_M_INL1_HML                       (0x1 << 1)
 603 #define RT5670_M_INL1_HML_SFT                   1
 604 #define RT5670_M_DACL1_HML                      (0x1)
 605 #define RT5670_M_DACL1_HML_SFT                  0
 606 
 607 /* Mono Output Mixer Control (0x4c) */
 608 #define RT5670_M_DAC_R2_MA                      (0x1 << 15)
 609 #define RT5670_M_DAC_R2_MA_SFT                  15
 610 #define RT5670_M_DAC_L2_MA                      (0x1 << 14)
 611 #define RT5670_M_DAC_L2_MA_SFT                  14
 612 #define RT5670_M_OV_R_MM                        (0x1 << 13)
 613 #define RT5670_M_OV_R_MM_SFT                    13
 614 #define RT5670_M_OV_L_MM                        (0x1 << 12)
 615 #define RT5670_M_OV_L_MM_SFT                    12
 616 #define RT5670_G_MONOMIX_MASK                   (0x1 << 10)
 617 #define RT5670_G_MONOMIX_SFT                    10
 618 #define RT5670_M_DAC_R2_MM                      (0x1 << 9)
 619 #define RT5670_M_DAC_R2_MM_SFT                  9
 620 #define RT5670_M_DAC_L2_MM                      (0x1 << 8)
 621 #define RT5670_M_DAC_L2_MM_SFT                  8
 622 #define RT5670_M_BST4_MM                        (0x1 << 7)
 623 #define RT5670_M_BST4_MM_SFT                    7
 624 
 625 /* Output Left Mixer Control 1 (0x4d) */
 626 #define RT5670_G_BST3_OM_L_MASK                 (0x7 << 13)
 627 #define RT5670_G_BST3_OM_L_SFT                  13
 628 #define RT5670_G_BST2_OM_L_MASK                 (0x7 << 10)
 629 #define RT5670_G_BST2_OM_L_SFT                  10
 630 #define RT5670_G_BST1_OM_L_MASK                 (0x7 << 7)
 631 #define RT5670_G_BST1_OM_L_SFT                  7
 632 #define RT5670_G_IN_L_OM_L_MASK                 (0x7 << 4)
 633 #define RT5670_G_IN_L_OM_L_SFT                  4
 634 #define RT5670_G_RM_L_OM_L_MASK                 (0x7 << 1)
 635 #define RT5670_G_RM_L_OM_L_SFT                  1
 636 
 637 /* Output Left Mixer Control 2 (0x4e) */
 638 #define RT5670_G_DAC_R2_OM_L_MASK               (0x7 << 13)
 639 #define RT5670_G_DAC_R2_OM_L_SFT                13
 640 #define RT5670_G_DAC_L2_OM_L_MASK               (0x7 << 10)
 641 #define RT5670_G_DAC_L2_OM_L_SFT                10
 642 #define RT5670_G_DAC_L1_OM_L_MASK               (0x7 << 7)
 643 #define RT5670_G_DAC_L1_OM_L_SFT                7
 644 
 645 /* Output Left Mixer Control 3 (0x4f) */
 646 #define RT5670_M_BST1_OM_L                      (0x1 << 5)
 647 #define RT5670_M_BST1_OM_L_SFT                  5
 648 #define RT5670_M_IN_L_OM_L                      (0x1 << 4)
 649 #define RT5670_M_IN_L_OM_L_SFT                  4
 650 #define RT5670_M_DAC_L2_OM_L                    (0x1 << 1)
 651 #define RT5670_M_DAC_L2_OM_L_SFT                1
 652 #define RT5670_M_DAC_L1_OM_L                    (0x1)
 653 #define RT5670_M_DAC_L1_OM_L_SFT                0
 654 
 655 /* Output Right Mixer Control 1 (0x50) */
 656 #define RT5670_G_BST4_OM_R_MASK                 (0x7 << 13)
 657 #define RT5670_G_BST4_OM_R_SFT                  13
 658 #define RT5670_G_BST2_OM_R_MASK                 (0x7 << 10)
 659 #define RT5670_G_BST2_OM_R_SFT                  10
 660 #define RT5670_G_BST1_OM_R_MASK                 (0x7 << 7)
 661 #define RT5670_G_BST1_OM_R_SFT                  7
 662 #define RT5670_G_IN_R_OM_R_MASK                 (0x7 << 4)
 663 #define RT5670_G_IN_R_OM_R_SFT                  4
 664 #define RT5670_G_RM_R_OM_R_MASK                 (0x7 << 1)
 665 #define RT5670_G_RM_R_OM_R_SFT                  1
 666 
 667 /* Output Right Mixer Control 2 (0x51) */
 668 #define RT5670_G_DAC_L2_OM_R_MASK               (0x7 << 13)
 669 #define RT5670_G_DAC_L2_OM_R_SFT                13
 670 #define RT5670_G_DAC_R2_OM_R_MASK               (0x7 << 10)
 671 #define RT5670_G_DAC_R2_OM_R_SFT                10
 672 #define RT5670_G_DAC_R1_OM_R_MASK               (0x7 << 7)
 673 #define RT5670_G_DAC_R1_OM_R_SFT                7
 674 
 675 /* Output Right Mixer Control 3 (0x52) */
 676 #define RT5670_M_BST2_OM_R                      (0x1 << 6)
 677 #define RT5670_M_BST2_OM_R_SFT                  6
 678 #define RT5670_M_IN_R_OM_R                      (0x1 << 4)
 679 #define RT5670_M_IN_R_OM_R_SFT                  4
 680 #define RT5670_M_DAC_R2_OM_R                    (0x1 << 1)
 681 #define RT5670_M_DAC_R2_OM_R_SFT                1
 682 #define RT5670_M_DAC_R1_OM_R                    (0x1)
 683 #define RT5670_M_DAC_R1_OM_R_SFT                0
 684 
 685 /* LOUT Mixer Control (0x53) */
 686 #define RT5670_M_DAC_L1_LM                      (0x1 << 15)
 687 #define RT5670_M_DAC_L1_LM_SFT                  15
 688 #define RT5670_M_DAC_R1_LM                      (0x1 << 14)
 689 #define RT5670_M_DAC_R1_LM_SFT                  14
 690 #define RT5670_M_OV_L_LM                        (0x1 << 13)
 691 #define RT5670_M_OV_L_LM_SFT                    13
 692 #define RT5670_M_OV_R_LM                        (0x1 << 12)
 693 #define RT5670_M_OV_R_LM_SFT                    12
 694 #define RT5670_G_LOUTMIX_MASK                   (0x1 << 11)
 695 #define RT5670_G_LOUTMIX_SFT                    11
 696 
 697 /* Power Management for Digital 1 (0x61) */
 698 #define RT5670_PWR_I2S1                         (0x1 << 15)
 699 #define RT5670_PWR_I2S1_BIT                     15
 700 #define RT5670_PWR_I2S2                         (0x1 << 14)
 701 #define RT5670_PWR_I2S2_BIT                     14
 702 #define RT5670_PWR_DAC_L1                       (0x1 << 12)
 703 #define RT5670_PWR_DAC_L1_BIT                   12
 704 #define RT5670_PWR_DAC_R1                       (0x1 << 11)
 705 #define RT5670_PWR_DAC_R1_BIT                   11
 706 #define RT5670_PWR_DAC_L2                       (0x1 << 7)
 707 #define RT5670_PWR_DAC_L2_BIT                   7
 708 #define RT5670_PWR_DAC_R2                       (0x1 << 6)
 709 #define RT5670_PWR_DAC_R2_BIT                   6
 710 #define RT5670_PWR_ADC_L                        (0x1 << 2)
 711 #define RT5670_PWR_ADC_L_BIT                    2
 712 #define RT5670_PWR_ADC_R                        (0x1 << 1)
 713 #define RT5670_PWR_ADC_R_BIT                    1
 714 #define RT5670_PWR_CLS_D                        (0x1)
 715 #define RT5670_PWR_CLS_D_BIT                    0
 716 
 717 /* Power Management for Digital 2 (0x62) */
 718 #define RT5670_PWR_ADC_S1F                      (0x1 << 15)
 719 #define RT5670_PWR_ADC_S1F_BIT                  15
 720 #define RT5670_PWR_ADC_MF_L                     (0x1 << 14)
 721 #define RT5670_PWR_ADC_MF_L_BIT                 14
 722 #define RT5670_PWR_ADC_MF_R                     (0x1 << 13)
 723 #define RT5670_PWR_ADC_MF_R_BIT                 13
 724 #define RT5670_PWR_I2S_DSP                      (0x1 << 12)
 725 #define RT5670_PWR_I2S_DSP_BIT                  12
 726 #define RT5670_PWR_DAC_S1F                      (0x1 << 11)
 727 #define RT5670_PWR_DAC_S1F_BIT                  11
 728 #define RT5670_PWR_DAC_MF_L                     (0x1 << 10)
 729 #define RT5670_PWR_DAC_MF_L_BIT                 10
 730 #define RT5670_PWR_DAC_MF_R                     (0x1 << 9)
 731 #define RT5670_PWR_DAC_MF_R_BIT                 9
 732 #define RT5670_PWR_ADC_S2F                      (0x1 << 8)
 733 #define RT5670_PWR_ADC_S2F_BIT                  8
 734 #define RT5670_PWR_PDM1                         (0x1 << 7)
 735 #define RT5670_PWR_PDM1_BIT                     7
 736 #define RT5670_PWR_PDM2                         (0x1 << 6)
 737 #define RT5670_PWR_PDM2_BIT                     6
 738 
 739 /* Power Management for Analog 1 (0x63) */
 740 #define RT5670_PWR_VREF1                        (0x1 << 15)
 741 #define RT5670_PWR_VREF1_BIT                    15
 742 #define RT5670_PWR_FV1                          (0x1 << 14)
 743 #define RT5670_PWR_FV1_BIT                      14
 744 #define RT5670_PWR_MB                           (0x1 << 13)
 745 #define RT5670_PWR_MB_BIT                       13
 746 #define RT5670_PWR_LM                           (0x1 << 12)
 747 #define RT5670_PWR_LM_BIT                       12
 748 #define RT5670_PWR_BG                           (0x1 << 11)
 749 #define RT5670_PWR_BG_BIT                       11
 750 #define RT5670_PWR_HP_L                         (0x1 << 7)
 751 #define RT5670_PWR_HP_L_BIT                     7
 752 #define RT5670_PWR_HP_R                         (0x1 << 6)
 753 #define RT5670_PWR_HP_R_BIT                     6
 754 #define RT5670_PWR_HA                           (0x1 << 5)
 755 #define RT5670_PWR_HA_BIT                       5
 756 #define RT5670_PWR_VREF2                        (0x1 << 4)
 757 #define RT5670_PWR_VREF2_BIT                    4
 758 #define RT5670_PWR_FV2                          (0x1 << 3)
 759 #define RT5670_PWR_FV2_BIT                      3
 760 #define RT5670_LDO_SEL_MASK                     (0x3)
 761 #define RT5670_LDO_SEL_SFT                      0
 762 
 763 /* Power Management for Analog 2 (0x64) */
 764 #define RT5670_PWR_BST1                         (0x1 << 15)
 765 #define RT5670_PWR_BST1_BIT                     15
 766 #define RT5670_PWR_BST2                         (0x1 << 13)
 767 #define RT5670_PWR_BST2_BIT                     13
 768 #define RT5670_PWR_MB1                          (0x1 << 11)
 769 #define RT5670_PWR_MB1_BIT                      11
 770 #define RT5670_PWR_MB2                          (0x1 << 10)
 771 #define RT5670_PWR_MB2_BIT                      10
 772 #define RT5670_PWR_PLL                          (0x1 << 9)
 773 #define RT5670_PWR_PLL_BIT                      9
 774 #define RT5670_PWR_BST1_P                       (0x1 << 6)
 775 #define RT5670_PWR_BST1_P_BIT                   6
 776 #define RT5670_PWR_BST2_P                       (0x1 << 4)
 777 #define RT5670_PWR_BST2_P_BIT                   4
 778 #define RT5670_PWR_JD1                          (0x1 << 2)
 779 #define RT5670_PWR_JD1_BIT                      2
 780 #define RT5670_PWR_JD                           (0x1 << 1)
 781 #define RT5670_PWR_JD_BIT                       1
 782 
 783 /* Power Management for Mixer (0x65) */
 784 #define RT5670_PWR_OM_L                         (0x1 << 15)
 785 #define RT5670_PWR_OM_L_BIT                     15
 786 #define RT5670_PWR_OM_R                         (0x1 << 14)
 787 #define RT5670_PWR_OM_R_BIT                     14
 788 #define RT5670_PWR_RM_L                         (0x1 << 11)
 789 #define RT5670_PWR_RM_L_BIT                     11
 790 #define RT5670_PWR_RM_R                         (0x1 << 10)
 791 #define RT5670_PWR_RM_R_BIT                     10
 792 
 793 /* Power Management for Volume (0x66) */
 794 #define RT5670_PWR_HV_L                         (0x1 << 11)
 795 #define RT5670_PWR_HV_L_BIT                     11
 796 #define RT5670_PWR_HV_R                         (0x1 << 10)
 797 #define RT5670_PWR_HV_R_BIT                     10
 798 #define RT5670_PWR_IN_L                         (0x1 << 9)
 799 #define RT5670_PWR_IN_L_BIT                     9
 800 #define RT5670_PWR_IN_R                         (0x1 << 8)
 801 #define RT5670_PWR_IN_R_BIT                     8
 802 #define RT5670_PWR_MIC_DET                      (0x1 << 5)
 803 #define RT5670_PWR_MIC_DET_BIT                  5
 804 
 805 /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
 806 #define RT5670_I2S_MS_MASK                      (0x1 << 15)
 807 #define RT5670_I2S_MS_SFT                       15
 808 #define RT5670_I2S_MS_M                         (0x0 << 15)
 809 #define RT5670_I2S_MS_S                         (0x1 << 15)
 810 #define RT5670_I2S_IF_MASK                      (0x7 << 12)
 811 #define RT5670_I2S_IF_SFT                       12
 812 #define RT5670_I2S_O_CP_MASK                    (0x3 << 10)
 813 #define RT5670_I2S_O_CP_SFT                     10
 814 #define RT5670_I2S_O_CP_OFF                     (0x0 << 10)
 815 #define RT5670_I2S_O_CP_U_LAW                   (0x1 << 10)
 816 #define RT5670_I2S_O_CP_A_LAW                   (0x2 << 10)
 817 #define RT5670_I2S_I_CP_MASK                    (0x3 << 8)
 818 #define RT5670_I2S_I_CP_SFT                     8
 819 #define RT5670_I2S_I_CP_OFF                     (0x0 << 8)
 820 #define RT5670_I2S_I_CP_U_LAW                   (0x1 << 8)
 821 #define RT5670_I2S_I_CP_A_LAW                   (0x2 << 8)
 822 #define RT5670_I2S_BP_MASK                      (0x1 << 7)
 823 #define RT5670_I2S_BP_SFT                       7
 824 #define RT5670_I2S_BP_NOR                       (0x0 << 7)
 825 #define RT5670_I2S_BP_INV                       (0x1 << 7)
 826 #define RT5670_I2S_DL_MASK                      (0x3 << 2)
 827 #define RT5670_I2S_DL_SFT                       2
 828 #define RT5670_I2S_DL_16                        (0x0 << 2)
 829 #define RT5670_I2S_DL_20                        (0x1 << 2)
 830 #define RT5670_I2S_DL_24                        (0x2 << 2)
 831 #define RT5670_I2S_DL_8                         (0x3 << 2)
 832 #define RT5670_I2S_DF_MASK                      (0x3)
 833 #define RT5670_I2S_DF_SFT                       0
 834 #define RT5670_I2S_DF_I2S                       (0x0)
 835 #define RT5670_I2S_DF_LEFT                      (0x1)
 836 #define RT5670_I2S_DF_PCM_A                     (0x2)
 837 #define RT5670_I2S_DF_PCM_B                     (0x3)
 838 
 839 /* I2S2 Audio Serial Data Port Control (0x71) */
 840 #define RT5670_I2S2_SDI_MASK                    (0x1 << 6)
 841 #define RT5670_I2S2_SDI_SFT                     6
 842 #define RT5670_I2S2_SDI_I2S1                    (0x0 << 6)
 843 #define RT5670_I2S2_SDI_I2S2                    (0x1 << 6)
 844 
 845 /* ADC/DAC Clock Control 1 (0x73) */
 846 #define RT5670_I2S_BCLK_MS1_MASK                (0x1 << 15)
 847 #define RT5670_I2S_BCLK_MS1_SFT                 15
 848 #define RT5670_I2S_BCLK_MS1_32                  (0x0 << 15)
 849 #define RT5670_I2S_BCLK_MS1_64                  (0x1 << 15)
 850 #define RT5670_I2S_PD1_MASK                     (0x7 << 12)
 851 #define RT5670_I2S_PD1_SFT                      12
 852 #define RT5670_I2S_PD1_1                        (0x0 << 12)
 853 #define RT5670_I2S_PD1_2                        (0x1 << 12)
 854 #define RT5670_I2S_PD1_3                        (0x2 << 12)
 855 #define RT5670_I2S_PD1_4                        (0x3 << 12)
 856 #define RT5670_I2S_PD1_6                        (0x4 << 12)
 857 #define RT5670_I2S_PD1_8                        (0x5 << 12)
 858 #define RT5670_I2S_PD1_12                       (0x6 << 12)
 859 #define RT5670_I2S_PD1_16                       (0x7 << 12)
 860 #define RT5670_I2S_BCLK_MS2_MASK                (0x1 << 11)
 861 #define RT5670_I2S_BCLK_MS2_SFT                 11
 862 #define RT5670_I2S_BCLK_MS2_32                  (0x0 << 11)
 863 #define RT5670_I2S_BCLK_MS2_64                  (0x1 << 11)
 864 #define RT5670_I2S_PD2_MASK                     (0x7 << 8)
 865 #define RT5670_I2S_PD2_SFT                      8
 866 #define RT5670_I2S_PD2_1                        (0x0 << 8)
 867 #define RT5670_I2S_PD2_2                        (0x1 << 8)
 868 #define RT5670_I2S_PD2_3                        (0x2 << 8)
 869 #define RT5670_I2S_PD2_4                        (0x3 << 8)
 870 #define RT5670_I2S_PD2_6                        (0x4 << 8)
 871 #define RT5670_I2S_PD2_8                        (0x5 << 8)
 872 #define RT5670_I2S_PD2_12                       (0x6 << 8)
 873 #define RT5670_I2S_PD2_16                       (0x7 << 8)
 874 #define RT5670_I2S_BCLK_MS3_MASK                (0x1 << 7)
 875 #define RT5670_I2S_BCLK_MS3_SFT                 7
 876 #define RT5670_I2S_BCLK_MS3_32                  (0x0 << 7)
 877 #define RT5670_I2S_BCLK_MS3_64                  (0x1 << 7)
 878 #define RT5670_I2S_PD3_MASK                     (0x7 << 4)
 879 #define RT5670_I2S_PD3_SFT                      4
 880 #define RT5670_I2S_PD3_1                        (0x0 << 4)
 881 #define RT5670_I2S_PD3_2                        (0x1 << 4)
 882 #define RT5670_I2S_PD3_3                        (0x2 << 4)
 883 #define RT5670_I2S_PD3_4                        (0x3 << 4)
 884 #define RT5670_I2S_PD3_6                        (0x4 << 4)
 885 #define RT5670_I2S_PD3_8                        (0x5 << 4)
 886 #define RT5670_I2S_PD3_12                       (0x6 << 4)
 887 #define RT5670_I2S_PD3_16                       (0x7 << 4)
 888 #define RT5670_DAC_OSR_MASK                     (0x3 << 2)
 889 #define RT5670_DAC_OSR_SFT                      2
 890 #define RT5670_DAC_OSR_128                      (0x0 << 2)
 891 #define RT5670_DAC_OSR_64                       (0x1 << 2)
 892 #define RT5670_DAC_OSR_32                       (0x2 << 2)
 893 #define RT5670_DAC_OSR_16                       (0x3 << 2)
 894 #define RT5670_ADC_OSR_MASK                     (0x3)
 895 #define RT5670_ADC_OSR_SFT                      0
 896 #define RT5670_ADC_OSR_128                      (0x0)
 897 #define RT5670_ADC_OSR_64                       (0x1)
 898 #define RT5670_ADC_OSR_32                       (0x2)
 899 #define RT5670_ADC_OSR_16                       (0x3)
 900 
 901 /* ADC/DAC Clock Control 2 (0x74) */
 902 #define RT5670_DAC_L_OSR_MASK                   (0x3 << 14)
 903 #define RT5670_DAC_L_OSR_SFT                    14
 904 #define RT5670_DAC_L_OSR_128                    (0x0 << 14)
 905 #define RT5670_DAC_L_OSR_64                     (0x1 << 14)
 906 #define RT5670_DAC_L_OSR_32                     (0x2 << 14)
 907 #define RT5670_DAC_L_OSR_16                     (0x3 << 14)
 908 #define RT5670_ADC_R_OSR_MASK                   (0x3 << 12)
 909 #define RT5670_ADC_R_OSR_SFT                    12
 910 #define RT5670_ADC_R_OSR_128                    (0x0 << 12)
 911 #define RT5670_ADC_R_OSR_64                     (0x1 << 12)
 912 #define RT5670_ADC_R_OSR_32                     (0x2 << 12)
 913 #define RT5670_ADC_R_OSR_16                     (0x3 << 12)
 914 #define RT5670_DAHPF_EN                         (0x1 << 11)
 915 #define RT5670_DAHPF_EN_SFT                     11
 916 #define RT5670_ADHPF_EN                         (0x1 << 10)
 917 #define RT5670_ADHPF_EN_SFT                     10
 918 
 919 /* Digital Microphone Control (0x75) */
 920 #define RT5670_DMIC_1_EN_MASK                   (0x1 << 15)
 921 #define RT5670_DMIC_1_EN_SFT                    15
 922 #define RT5670_DMIC_1_DIS                       (0x0 << 15)
 923 #define RT5670_DMIC_1_EN                        (0x1 << 15)
 924 #define RT5670_DMIC_2_EN_MASK                   (0x1 << 14)
 925 #define RT5670_DMIC_2_EN_SFT                    14
 926 #define RT5670_DMIC_2_DIS                       (0x0 << 14)
 927 #define RT5670_DMIC_2_EN                        (0x1 << 14)
 928 #define RT5670_DMIC_1L_LH_MASK                  (0x1 << 13)
 929 #define RT5670_DMIC_1L_LH_SFT                   13
 930 #define RT5670_DMIC_1L_LH_FALLING               (0x0 << 13)
 931 #define RT5670_DMIC_1L_LH_RISING                (0x1 << 13)
 932 #define RT5670_DMIC_1R_LH_MASK                  (0x1 << 12)
 933 #define RT5670_DMIC_1R_LH_SFT                   12
 934 #define RT5670_DMIC_1R_LH_FALLING               (0x0 << 12)
 935 #define RT5670_DMIC_1R_LH_RISING                (0x1 << 12)
 936 #define RT5670_DMIC_2_DP_MASK                   (0x1 << 10)
 937 #define RT5670_DMIC_2_DP_SFT                    10
 938 #define RT5670_DMIC_2_DP_GPIO8                  (0x0 << 10)
 939 #define RT5670_DMIC_2_DP_IN3N                   (0x1 << 10)
 940 #define RT5670_DMIC_2L_LH_MASK                  (0x1 << 9)
 941 #define RT5670_DMIC_2L_LH_SFT                   9
 942 #define RT5670_DMIC_2L_LH_FALLING               (0x0 << 9)
 943 #define RT5670_DMIC_2L_LH_RISING                (0x1 << 9)
 944 #define RT5670_DMIC_2R_LH_MASK                  (0x1 << 8)
 945 #define RT5670_DMIC_2R_LH_SFT                   8
 946 #define RT5670_DMIC_2R_LH_FALLING               (0x0 << 8)
 947 #define RT5670_DMIC_2R_LH_RISING                (0x1 << 8)
 948 #define RT5670_DMIC_CLK_MASK                    (0x7 << 5)
 949 #define RT5670_DMIC_CLK_SFT                     5
 950 #define RT5670_DMIC_3_EN_MASK                   (0x1 << 4)
 951 #define RT5670_DMIC_3_EN_SFT                    4
 952 #define RT5670_DMIC_3_DIS                       (0x0 << 4)
 953 #define RT5670_DMIC_3_EN                        (0x1 << 4)
 954 #define RT5670_DMIC_1_DP_MASK                   (0x3 << 0)
 955 #define RT5670_DMIC_1_DP_SFT                    0
 956 #define RT5670_DMIC_1_DP_GPIO6                  (0x0 << 0)
 957 #define RT5670_DMIC_1_DP_IN2P                   (0x1 << 0)
 958 #define RT5670_DMIC_1_DP_GPIO7                  (0x2 << 0)
 959 
 960 /* Digital Microphone Control2 (0x76) */
 961 #define RT5670_DMIC_3_DP_MASK                   (0x3 << 6)
 962 #define RT5670_DMIC_3_DP_SFT                    6
 963 #define RT5670_DMIC_3_DP_GPIO9                  (0x0 << 6)
 964 #define RT5670_DMIC_3_DP_GPIO10                 (0x1 << 6)
 965 #define RT5670_DMIC_3_DP_GPIO5                  (0x2 << 6)
 966 
 967 /* Global Clock Control (0x80) */
 968 #define RT5670_SCLK_SRC_MASK                    (0x3 << 14)
 969 #define RT5670_SCLK_SRC_SFT                     14
 970 #define RT5670_SCLK_SRC_MCLK                    (0x0 << 14)
 971 #define RT5670_SCLK_SRC_PLL1                    (0x1 << 14)
 972 #define RT5670_SCLK_SRC_RCCLK                   (0x2 << 14) /* 15MHz */
 973 #define RT5670_PLL1_SRC_MASK                    (0x7 << 11)
 974 #define RT5670_PLL1_SRC_SFT                     11
 975 #define RT5670_PLL1_SRC_MCLK                    (0x0 << 11)
 976 #define RT5670_PLL1_SRC_BCLK1                   (0x1 << 11)
 977 #define RT5670_PLL1_SRC_BCLK2                   (0x2 << 11)
 978 #define RT5670_PLL1_SRC_BCLK3                   (0x3 << 11)
 979 #define RT5670_PLL1_PD_MASK                     (0x1 << 3)
 980 #define RT5670_PLL1_PD_SFT                      3
 981 #define RT5670_PLL1_PD_1                        (0x0 << 3)
 982 #define RT5670_PLL1_PD_2                        (0x1 << 3)
 983 
 984 #define RT5670_PLL_INP_MAX                      40000000
 985 #define RT5670_PLL_INP_MIN                      256000
 986 /* PLL M/N/K Code Control 1 (0x81) */
 987 #define RT5670_PLL_N_MAX                        0x1ff
 988 #define RT5670_PLL_N_MASK                       (RT5670_PLL_N_MAX << 7)
 989 #define RT5670_PLL_N_SFT                        7
 990 #define RT5670_PLL_K_MAX                        0x1f
 991 #define RT5670_PLL_K_MASK                       (RT5670_PLL_K_MAX)
 992 #define RT5670_PLL_K_SFT                        0
 993 
 994 /* PLL M/N/K Code Control 2 (0x82) */
 995 #define RT5670_PLL_M_MAX                        0xf
 996 #define RT5670_PLL_M_MASK                       (RT5670_PLL_M_MAX << 12)
 997 #define RT5670_PLL_M_SFT                        12
 998 #define RT5670_PLL_M_BP                         (0x1 << 11)
 999 #define RT5670_PLL_M_BP_SFT                     11
1000 
1001 /* ASRC Control 1 (0x83) */
1002 #define RT5670_STO_T_MASK                       (0x1 << 15)
1003 #define RT5670_STO_T_SFT                        15
1004 #define RT5670_STO_T_SCLK                       (0x0 << 15)
1005 #define RT5670_STO_T_LRCK1                      (0x1 << 15)
1006 #define RT5670_M1_T_MASK                        (0x1 << 14)
1007 #define RT5670_M1_T_SFT                         14
1008 #define RT5670_M1_T_I2S2                        (0x0 << 14)
1009 #define RT5670_M1_T_I2S2_D3                     (0x1 << 14)
1010 #define RT5670_I2S2_F_MASK                      (0x1 << 12)
1011 #define RT5670_I2S2_F_SFT                       12
1012 #define RT5670_I2S2_F_I2S2_D2                   (0x0 << 12)
1013 #define RT5670_I2S2_F_I2S1_TCLK                 (0x1 << 12)
1014 #define RT5670_DMIC_1_M_MASK                    (0x1 << 9)
1015 #define RT5670_DMIC_1_M_SFT                     9
1016 #define RT5670_DMIC_1_M_NOR                     (0x0 << 9)
1017 #define RT5670_DMIC_1_M_ASYN                    (0x1 << 9)
1018 #define RT5670_DMIC_2_M_MASK                    (0x1 << 8)
1019 #define RT5670_DMIC_2_M_SFT                     8
1020 #define RT5670_DMIC_2_M_NOR                     (0x0 << 8)
1021 #define RT5670_DMIC_2_M_ASYN                    (0x1 << 8)
1022 
1023 /* ASRC clock source selection (0x84, 0x85) */
1024 #define RT5670_CLK_SEL_SYS                      (0x0)
1025 #define RT5670_CLK_SEL_I2S1_ASRC                (0x1)
1026 #define RT5670_CLK_SEL_I2S2_ASRC                (0x2)
1027 #define RT5670_CLK_SEL_I2S3_ASRC                (0x3)
1028 #define RT5670_CLK_SEL_SYS2                     (0x5)
1029 #define RT5670_CLK_SEL_SYS3                     (0x6)
1030 
1031 /* ASRC Control 2 (0x84) */
1032 #define RT5670_DA_STO_CLK_SEL_MASK              (0xf << 12)
1033 #define RT5670_DA_STO_CLK_SEL_SFT               12
1034 #define RT5670_DA_MONOL_CLK_SEL_MASK            (0xf << 8)
1035 #define RT5670_DA_MONOL_CLK_SEL_SFT             8
1036 #define RT5670_DA_MONOR_CLK_SEL_MASK            (0xf << 4)
1037 #define RT5670_DA_MONOR_CLK_SEL_SFT             4
1038 #define RT5670_AD_STO1_CLK_SEL_MASK             (0xf << 0)
1039 #define RT5670_AD_STO1_CLK_SEL_SFT              0
1040 
1041 /* ASRC Control 3 (0x85) */
1042 #define RT5670_UP_CLK_SEL_MASK                  (0xf << 12)
1043 #define RT5670_UP_CLK_SEL_SFT                   12
1044 #define RT5670_DOWN_CLK_SEL_MASK                (0xf << 8)
1045 #define RT5670_DOWN_CLK_SEL_SFT                 8
1046 #define RT5670_AD_MONOL_CLK_SEL_MASK            (0xf << 4)
1047 #define RT5670_AD_MONOL_CLK_SEL_SFT             4
1048 #define RT5670_AD_MONOR_CLK_SEL_MASK            (0xf << 0)
1049 #define RT5670_AD_MONOR_CLK_SEL_SFT             0
1050 
1051 /* ASRC Control 4 (0x89) */
1052 #define RT5670_I2S1_PD_MASK                     (0x7 << 12)
1053 #define RT5670_I2S1_PD_SFT                      12
1054 #define RT5670_I2S2_PD_MASK                     (0x7 << 8)
1055 #define RT5670_I2S2_PD_SFT                      8
1056 
1057 /* HPOUT Over Current Detection (0x8b) */
1058 #define RT5670_HP_OVCD_MASK                     (0x1 << 10)
1059 #define RT5670_HP_OVCD_SFT                      10
1060 #define RT5670_HP_OVCD_DIS                      (0x0 << 10)
1061 #define RT5670_HP_OVCD_EN                       (0x1 << 10)
1062 #define RT5670_HP_OC_TH_MASK                    (0x3 << 8)
1063 #define RT5670_HP_OC_TH_SFT                     8
1064 #define RT5670_HP_OC_TH_90                      (0x0 << 8)
1065 #define RT5670_HP_OC_TH_105                     (0x1 << 8)
1066 #define RT5670_HP_OC_TH_120                     (0x2 << 8)
1067 #define RT5670_HP_OC_TH_135                     (0x3 << 8)
1068 
1069 /* Class D Over Current Control (0x8c) */
1070 #define RT5670_CLSD_OC_MASK                     (0x1 << 9)
1071 #define RT5670_CLSD_OC_SFT                      9
1072 #define RT5670_CLSD_OC_PU                       (0x0 << 9)
1073 #define RT5670_CLSD_OC_PD                       (0x1 << 9)
1074 #define RT5670_AUTO_PD_MASK                     (0x1 << 8)
1075 #define RT5670_AUTO_PD_SFT                      8
1076 #define RT5670_AUTO_PD_DIS                      (0x0 << 8)
1077 #define RT5670_AUTO_PD_EN                       (0x1 << 8)
1078 #define RT5670_CLSD_OC_TH_MASK                  (0x3f)
1079 #define RT5670_CLSD_OC_TH_SFT                   0
1080 
1081 /* Class D Output Control (0x8d) */
1082 #define RT5670_CLSD_RATIO_MASK                  (0xf << 12)
1083 #define RT5670_CLSD_RATIO_SFT                   12
1084 #define RT5670_CLSD_OM_MASK                     (0x1 << 11)
1085 #define RT5670_CLSD_OM_SFT                      11
1086 #define RT5670_CLSD_OM_MONO                     (0x0 << 11)
1087 #define RT5670_CLSD_OM_STO                      (0x1 << 11)
1088 #define RT5670_CLSD_SCH_MASK                    (0x1 << 10)
1089 #define RT5670_CLSD_SCH_SFT                     10
1090 #define RT5670_CLSD_SCH_L                       (0x0 << 10)
1091 #define RT5670_CLSD_SCH_S                       (0x1 << 10)
1092 
1093 /* Depop Mode Control 1 (0x8e) */
1094 #define RT5670_SMT_TRIG_MASK                    (0x1 << 15)
1095 #define RT5670_SMT_TRIG_SFT                     15
1096 #define RT5670_SMT_TRIG_DIS                     (0x0 << 15)
1097 #define RT5670_SMT_TRIG_EN                      (0x1 << 15)
1098 #define RT5670_HP_L_SMT_MASK                    (0x1 << 9)
1099 #define RT5670_HP_L_SMT_SFT                     9
1100 #define RT5670_HP_L_SMT_DIS                     (0x0 << 9)
1101 #define RT5670_HP_L_SMT_EN                      (0x1 << 9)
1102 #define RT5670_HP_R_SMT_MASK                    (0x1 << 8)
1103 #define RT5670_HP_R_SMT_SFT                     8
1104 #define RT5670_HP_R_SMT_DIS                     (0x0 << 8)
1105 #define RT5670_HP_R_SMT_EN                      (0x1 << 8)
1106 #define RT5670_HP_CD_PD_MASK                    (0x1 << 7)
1107 #define RT5670_HP_CD_PD_SFT                     7
1108 #define RT5670_HP_CD_PD_DIS                     (0x0 << 7)
1109 #define RT5670_HP_CD_PD_EN                      (0x1 << 7)
1110 #define RT5670_RSTN_MASK                        (0x1 << 6)
1111 #define RT5670_RSTN_SFT                         6
1112 #define RT5670_RSTN_DIS                         (0x0 << 6)
1113 #define RT5670_RSTN_EN                          (0x1 << 6)
1114 #define RT5670_RSTP_MASK                        (0x1 << 5)
1115 #define RT5670_RSTP_SFT                         5
1116 #define RT5670_RSTP_DIS                         (0x0 << 5)
1117 #define RT5670_RSTP_EN                          (0x1 << 5)
1118 #define RT5670_HP_CO_MASK                       (0x1 << 4)
1119 #define RT5670_HP_CO_SFT                        4
1120 #define RT5670_HP_CO_DIS                        (0x0 << 4)
1121 #define RT5670_HP_CO_EN                         (0x1 << 4)
1122 #define RT5670_HP_CP_MASK                       (0x1 << 3)
1123 #define RT5670_HP_CP_SFT                        3
1124 #define RT5670_HP_CP_PD                         (0x0 << 3)
1125 #define RT5670_HP_CP_PU                         (0x1 << 3)
1126 #define RT5670_HP_SG_MASK                       (0x1 << 2)
1127 #define RT5670_HP_SG_SFT                        2
1128 #define RT5670_HP_SG_DIS                        (0x0 << 2)
1129 #define RT5670_HP_SG_EN                         (0x1 << 2)
1130 #define RT5670_HP_DP_MASK                       (0x1 << 1)
1131 #define RT5670_HP_DP_SFT                        1
1132 #define RT5670_HP_DP_PD                         (0x0 << 1)
1133 #define RT5670_HP_DP_PU                         (0x1 << 1)
1134 #define RT5670_HP_CB_MASK                       (0x1)
1135 #define RT5670_HP_CB_SFT                        0
1136 #define RT5670_HP_CB_PD                         (0x0)
1137 #define RT5670_HP_CB_PU                         (0x1)
1138 
1139 /* Depop Mode Control 2 (0x8f) */
1140 #define RT5670_DEPOP_MASK                       (0x1 << 13)
1141 #define RT5670_DEPOP_SFT                        13
1142 #define RT5670_DEPOP_AUTO                       (0x0 << 13)
1143 #define RT5670_DEPOP_MAN                        (0x1 << 13)
1144 #define RT5670_RAMP_MASK                        (0x1 << 12)
1145 #define RT5670_RAMP_SFT                         12
1146 #define RT5670_RAMP_DIS                         (0x0 << 12)
1147 #define RT5670_RAMP_EN                          (0x1 << 12)
1148 #define RT5670_BPS_MASK                         (0x1 << 11)
1149 #define RT5670_BPS_SFT                          11
1150 #define RT5670_BPS_DIS                          (0x0 << 11)
1151 #define RT5670_BPS_EN                           (0x1 << 11)
1152 #define RT5670_FAST_UPDN_MASK                   (0x1 << 10)
1153 #define RT5670_FAST_UPDN_SFT                    10
1154 #define RT5670_FAST_UPDN_DIS                    (0x0 << 10)
1155 #define RT5670_FAST_UPDN_EN                     (0x1 << 10)
1156 #define RT5670_MRES_MASK                        (0x3 << 8)
1157 #define RT5670_MRES_SFT                         8
1158 #define RT5670_MRES_15MO                        (0x0 << 8)
1159 #define RT5670_MRES_25MO                        (0x1 << 8)
1160 #define RT5670_MRES_35MO                        (0x2 << 8)
1161 #define RT5670_MRES_45MO                        (0x3 << 8)
1162 #define RT5670_VLO_MASK                         (0x1 << 7)
1163 #define RT5670_VLO_SFT                          7
1164 #define RT5670_VLO_3V                           (0x0 << 7)
1165 #define RT5670_VLO_32V                          (0x1 << 7)
1166 #define RT5670_DIG_DP_MASK                      (0x1 << 6)
1167 #define RT5670_DIG_DP_SFT                       6
1168 #define RT5670_DIG_DP_DIS                       (0x0 << 6)
1169 #define RT5670_DIG_DP_EN                        (0x1 << 6)
1170 #define RT5670_DP_TH_MASK                       (0x3 << 4)
1171 #define RT5670_DP_TH_SFT                        4
1172 
1173 /* Depop Mode Control 3 (0x90) */
1174 #define RT5670_CP_SYS_MASK                      (0x7 << 12)
1175 #define RT5670_CP_SYS_SFT                       12
1176 #define RT5670_CP_FQ1_MASK                      (0x7 << 8)
1177 #define RT5670_CP_FQ1_SFT                       8
1178 #define RT5670_CP_FQ2_MASK                      (0x7 << 4)
1179 #define RT5670_CP_FQ2_SFT                       4
1180 #define RT5670_CP_FQ3_MASK                      (0x7)
1181 #define RT5670_CP_FQ3_SFT                       0
1182 #define RT5670_CP_FQ_1_5_KHZ                    0
1183 #define RT5670_CP_FQ_3_KHZ                      1
1184 #define RT5670_CP_FQ_6_KHZ                      2
1185 #define RT5670_CP_FQ_12_KHZ                     3
1186 #define RT5670_CP_FQ_24_KHZ                     4
1187 #define RT5670_CP_FQ_48_KHZ                     5
1188 #define RT5670_CP_FQ_96_KHZ                     6
1189 #define RT5670_CP_FQ_192_KHZ                    7
1190 
1191 /* HPOUT charge pump (0x91) */
1192 #define RT5670_OSW_L_MASK                       (0x1 << 11)
1193 #define RT5670_OSW_L_SFT                        11
1194 #define RT5670_OSW_L_DIS                        (0x0 << 11)
1195 #define RT5670_OSW_L_EN                         (0x1 << 11)
1196 #define RT5670_OSW_R_MASK                       (0x1 << 10)
1197 #define RT5670_OSW_R_SFT                        10
1198 #define RT5670_OSW_R_DIS                        (0x0 << 10)
1199 #define RT5670_OSW_R_EN                         (0x1 << 10)
1200 #define RT5670_PM_HP_MASK                       (0x3 << 8)
1201 #define RT5670_PM_HP_SFT                        8
1202 #define RT5670_PM_HP_LV                         (0x0 << 8)
1203 #define RT5670_PM_HP_MV                         (0x1 << 8)
1204 #define RT5670_PM_HP_HV                         (0x2 << 8)
1205 #define RT5670_IB_HP_MASK                       (0x3 << 6)
1206 #define RT5670_IB_HP_SFT                        6
1207 #define RT5670_IB_HP_125IL                      (0x0 << 6)
1208 #define RT5670_IB_HP_25IL                       (0x1 << 6)
1209 #define RT5670_IB_HP_5IL                        (0x2 << 6)
1210 #define RT5670_IB_HP_1IL                        (0x3 << 6)
1211 
1212 /* PV detection and SPK gain control (0x92) */
1213 #define RT5670_PVDD_DET_MASK                    (0x1 << 15)
1214 #define RT5670_PVDD_DET_SFT                     15
1215 #define RT5670_PVDD_DET_DIS                     (0x0 << 15)
1216 #define RT5670_PVDD_DET_EN                      (0x1 << 15)
1217 #define RT5670_SPK_AG_MASK                      (0x1 << 14)
1218 #define RT5670_SPK_AG_SFT                       14
1219 #define RT5670_SPK_AG_DIS                       (0x0 << 14)
1220 #define RT5670_SPK_AG_EN                        (0x1 << 14)
1221 
1222 /* Micbias Control (0x93) */
1223 #define RT5670_MIC1_BS_MASK                     (0x1 << 15)
1224 #define RT5670_MIC1_BS_SFT                      15
1225 #define RT5670_MIC1_BS_9AV                      (0x0 << 15)
1226 #define RT5670_MIC1_BS_75AV                     (0x1 << 15)
1227 #define RT5670_MIC2_BS_MASK                     (0x1 << 14)
1228 #define RT5670_MIC2_BS_SFT                      14
1229 #define RT5670_MIC2_BS_9AV                      (0x0 << 14)
1230 #define RT5670_MIC2_BS_75AV                     (0x1 << 14)
1231 #define RT5670_MIC1_CLK_MASK                    (0x1 << 13)
1232 #define RT5670_MIC1_CLK_SFT                     13
1233 #define RT5670_MIC1_CLK_DIS                     (0x0 << 13)
1234 #define RT5670_MIC1_CLK_EN                      (0x1 << 13)
1235 #define RT5670_MIC2_CLK_MASK                    (0x1 << 12)
1236 #define RT5670_MIC2_CLK_SFT                     12
1237 #define RT5670_MIC2_CLK_DIS                     (0x0 << 12)
1238 #define RT5670_MIC2_CLK_EN                      (0x1 << 12)
1239 #define RT5670_MIC1_OVCD_MASK                   (0x1 << 11)
1240 #define RT5670_MIC1_OVCD_SFT                    11
1241 #define RT5670_MIC1_OVCD_DIS                    (0x0 << 11)
1242 #define RT5670_MIC1_OVCD_EN                     (0x1 << 11)
1243 #define RT5670_MIC1_OVTH_MASK                   (0x3 << 9)
1244 #define RT5670_MIC1_OVTH_SFT                    9
1245 #define RT5670_MIC1_OVTH_600UA                  (0x0 << 9)
1246 #define RT5670_MIC1_OVTH_1500UA                 (0x1 << 9)
1247 #define RT5670_MIC1_OVTH_2000UA                 (0x2 << 9)
1248 #define RT5670_MIC2_OVCD_MASK                   (0x1 << 8)
1249 #define RT5670_MIC2_OVCD_SFT                    8
1250 #define RT5670_MIC2_OVCD_DIS                    (0x0 << 8)
1251 #define RT5670_MIC2_OVCD_EN                     (0x1 << 8)
1252 #define RT5670_MIC2_OVTH_MASK                   (0x3 << 6)
1253 #define RT5670_MIC2_OVTH_SFT                    6
1254 #define RT5670_MIC2_OVTH_600UA                  (0x0 << 6)
1255 #define RT5670_MIC2_OVTH_1500UA                 (0x1 << 6)
1256 #define RT5670_MIC2_OVTH_2000UA                 (0x2 << 6)
1257 #define RT5670_PWR_MB_MASK                      (0x1 << 5)
1258 #define RT5670_PWR_MB_SFT                       5
1259 #define RT5670_PWR_MB_PD                        (0x0 << 5)
1260 #define RT5670_PWR_MB_PU                        (0x1 << 5)
1261 #define RT5670_PWR_CLK25M_MASK                  (0x1 << 4)
1262 #define RT5670_PWR_CLK25M_SFT                   4
1263 #define RT5670_PWR_CLK25M_PD                    (0x0 << 4)
1264 #define RT5670_PWR_CLK25M_PU                    (0x1 << 4)
1265 
1266 /* Analog JD Control 1 (0x94) */
1267 #define RT5670_JD1_MODE_MASK                    (0x3 << 0)
1268 #define RT5670_JD1_MODE_0                       (0x0 << 0)
1269 #define RT5670_JD1_MODE_1                       (0x1 << 0)
1270 #define RT5670_JD1_MODE_2                       (0x2 << 0)
1271 
1272 /* VAD Control 4 (0x9d) */
1273 #define RT5670_VAD_SEL_MASK                     (0x3 << 8)
1274 #define RT5670_VAD_SEL_SFT                      8
1275 
1276 /* EQ Control 1 (0xb0) */
1277 #define RT5670_EQ_SRC_MASK                      (0x1 << 15)
1278 #define RT5670_EQ_SRC_SFT                       15
1279 #define RT5670_EQ_SRC_DAC                       (0x0 << 15)
1280 #define RT5670_EQ_SRC_ADC                       (0x1 << 15)
1281 #define RT5670_EQ_UPD                           (0x1 << 14)
1282 #define RT5670_EQ_UPD_BIT                       14
1283 #define RT5670_EQ_CD_MASK                       (0x1 << 13)
1284 #define RT5670_EQ_CD_SFT                        13
1285 #define RT5670_EQ_CD_DIS                        (0x0 << 13)
1286 #define RT5670_EQ_CD_EN                         (0x1 << 13)
1287 #define RT5670_EQ_DITH_MASK                     (0x3 << 8)
1288 #define RT5670_EQ_DITH_SFT                      8
1289 #define RT5670_EQ_DITH_NOR                      (0x0 << 8)
1290 #define RT5670_EQ_DITH_LSB                      (0x1 << 8)
1291 #define RT5670_EQ_DITH_LSB_1                    (0x2 << 8)
1292 #define RT5670_EQ_DITH_LSB_2                    (0x3 << 8)
1293 
1294 /* EQ Control 2 (0xb1) */
1295 #define RT5670_EQ_HPF1_M_MASK                   (0x1 << 8)
1296 #define RT5670_EQ_HPF1_M_SFT                    8
1297 #define RT5670_EQ_HPF1_M_HI                     (0x0 << 8)
1298 #define RT5670_EQ_HPF1_M_1ST                    (0x1 << 8)
1299 #define RT5670_EQ_LPF1_M_MASK                   (0x1 << 7)
1300 #define RT5670_EQ_LPF1_M_SFT                    7
1301 #define RT5670_EQ_LPF1_M_LO                     (0x0 << 7)
1302 #define RT5670_EQ_LPF1_M_1ST                    (0x1 << 7)
1303 #define RT5670_EQ_HPF2_MASK                     (0x1 << 6)
1304 #define RT5670_EQ_HPF2_SFT                      6
1305 #define RT5670_EQ_HPF2_DIS                      (0x0 << 6)
1306 #define RT5670_EQ_HPF2_EN                       (0x1 << 6)
1307 #define RT5670_EQ_HPF1_MASK                     (0x1 << 5)
1308 #define RT5670_EQ_HPF1_SFT                      5
1309 #define RT5670_EQ_HPF1_DIS                      (0x0 << 5)
1310 #define RT5670_EQ_HPF1_EN                       (0x1 << 5)
1311 #define RT5670_EQ_BPF4_MASK                     (0x1 << 4)
1312 #define RT5670_EQ_BPF4_SFT                      4
1313 #define RT5670_EQ_BPF4_DIS                      (0x0 << 4)
1314 #define RT5670_EQ_BPF4_EN                       (0x1 << 4)
1315 #define RT5670_EQ_BPF3_MASK                     (0x1 << 3)
1316 #define RT5670_EQ_BPF3_SFT                      3
1317 #define RT5670_EQ_BPF3_DIS                      (0x0 << 3)
1318 #define RT5670_EQ_BPF3_EN                       (0x1 << 3)
1319 #define RT5670_EQ_BPF2_MASK                     (0x1 << 2)
1320 #define RT5670_EQ_BPF2_SFT                      2
1321 #define RT5670_EQ_BPF2_DIS                      (0x0 << 2)
1322 #define RT5670_EQ_BPF2_EN                       (0x1 << 2)
1323 #define RT5670_EQ_BPF1_MASK                     (0x1 << 1)
1324 #define RT5670_EQ_BPF1_SFT                      1
1325 #define RT5670_EQ_BPF1_DIS                      (0x0 << 1)
1326 #define RT5670_EQ_BPF1_EN                       (0x1 << 1)
1327 #define RT5670_EQ_LPF_MASK                      (0x1)
1328 #define RT5670_EQ_LPF_SFT                       0
1329 #define RT5670_EQ_LPF_DIS                       (0x0)
1330 #define RT5670_EQ_LPF_EN                        (0x1)
1331 #define RT5670_EQ_CTRL_MASK                     (0x7f)
1332 
1333 /* Memory Test (0xb2) */
1334 #define RT5670_MT_MASK                          (0x1 << 15)
1335 #define RT5670_MT_SFT                           15
1336 #define RT5670_MT_DIS                           (0x0 << 15)
1337 #define RT5670_MT_EN                            (0x1 << 15)
1338 
1339 /* DRC/AGC Control 1 (0xb4) */
1340 #define RT5670_DRC_AGC_P_MASK                   (0x1 << 15)
1341 #define RT5670_DRC_AGC_P_SFT                    15
1342 #define RT5670_DRC_AGC_P_DAC                    (0x0 << 15)
1343 #define RT5670_DRC_AGC_P_ADC                    (0x1 << 15)
1344 #define RT5670_DRC_AGC_MASK                     (0x1 << 14)
1345 #define RT5670_DRC_AGC_SFT                      14
1346 #define RT5670_DRC_AGC_DIS                      (0x0 << 14)
1347 #define RT5670_DRC_AGC_EN                       (0x1 << 14)
1348 #define RT5670_DRC_AGC_UPD                      (0x1 << 13)
1349 #define RT5670_DRC_AGC_UPD_BIT                  13
1350 #define RT5670_DRC_AGC_AR_MASK                  (0x1f << 8)
1351 #define RT5670_DRC_AGC_AR_SFT                   8
1352 #define RT5670_DRC_AGC_R_MASK                   (0x7 << 5)
1353 #define RT5670_DRC_AGC_R_SFT                    5
1354 #define RT5670_DRC_AGC_R_48K                    (0x1 << 5)
1355 #define RT5670_DRC_AGC_R_96K                    (0x2 << 5)
1356 #define RT5670_DRC_AGC_R_192K                   (0x3 << 5)
1357 #define RT5670_DRC_AGC_R_441K                   (0x5 << 5)
1358 #define RT5670_DRC_AGC_R_882K                   (0x6 << 5)
1359 #define RT5670_DRC_AGC_R_1764K                  (0x7 << 5)
1360 #define RT5670_DRC_AGC_RC_MASK                  (0x1f)
1361 #define RT5670_DRC_AGC_RC_SFT                   0
1362 
1363 /* DRC/AGC Control 2 (0xb5) */
1364 #define RT5670_DRC_AGC_POB_MASK                 (0x3f << 8)
1365 #define RT5670_DRC_AGC_POB_SFT                  8
1366 #define RT5670_DRC_AGC_CP_MASK                  (0x1 << 7)
1367 #define RT5670_DRC_AGC_CP_SFT                   7
1368 #define RT5670_DRC_AGC_CP_DIS                   (0x0 << 7)
1369 #define RT5670_DRC_AGC_CP_EN                    (0x1 << 7)
1370 #define RT5670_DRC_AGC_CPR_MASK                 (0x3 << 5)
1371 #define RT5670_DRC_AGC_CPR_SFT                  5
1372 #define RT5670_DRC_AGC_CPR_1_1                  (0x0 << 5)
1373 #define RT5670_DRC_AGC_CPR_1_2                  (0x1 << 5)
1374 #define RT5670_DRC_AGC_CPR_1_3                  (0x2 << 5)
1375 #define RT5670_DRC_AGC_CPR_1_4                  (0x3 << 5)
1376 #define RT5670_DRC_AGC_PRB_MASK                 (0x1f)
1377 #define RT5670_DRC_AGC_PRB_SFT                  0
1378 
1379 /* DRC/AGC Control 3 (0xb6) */
1380 #define RT5670_DRC_AGC_NGB_MASK                 (0xf << 12)
1381 #define RT5670_DRC_AGC_NGB_SFT                  12
1382 #define RT5670_DRC_AGC_TAR_MASK                 (0x1f << 7)
1383 #define RT5670_DRC_AGC_TAR_SFT                  7
1384 #define RT5670_DRC_AGC_NG_MASK                  (0x1 << 6)
1385 #define RT5670_DRC_AGC_NG_SFT                   6
1386 #define RT5670_DRC_AGC_NG_DIS                   (0x0 << 6)
1387 #define RT5670_DRC_AGC_NG_EN                    (0x1 << 6)
1388 #define RT5670_DRC_AGC_NGH_MASK                 (0x1 << 5)
1389 #define RT5670_DRC_AGC_NGH_SFT                  5
1390 #define RT5670_DRC_AGC_NGH_DIS                  (0x0 << 5)
1391 #define RT5670_DRC_AGC_NGH_EN                   (0x1 << 5)
1392 #define RT5670_DRC_AGC_NGT_MASK                 (0x1f)
1393 #define RT5670_DRC_AGC_NGT_SFT                  0
1394 
1395 /* Jack Detect Control (0xbb) */
1396 #define RT5670_JD_MASK                          (0x7 << 13)
1397 #define RT5670_JD_SFT                           13
1398 #define RT5670_JD_DIS                           (0x0 << 13)
1399 #define RT5670_JD_GPIO1                         (0x1 << 13)
1400 #define RT5670_JD_JD1_IN4P                      (0x2 << 13)
1401 #define RT5670_JD_JD2_IN4N                      (0x3 << 13)
1402 #define RT5670_JD_GPIO2                         (0x4 << 13)
1403 #define RT5670_JD_GPIO3                         (0x5 << 13)
1404 #define RT5670_JD_GPIO4                         (0x6 << 13)
1405 #define RT5670_JD_HP_MASK                       (0x1 << 11)
1406 #define RT5670_JD_HP_SFT                        11
1407 #define RT5670_JD_HP_DIS                        (0x0 << 11)
1408 #define RT5670_JD_HP_EN                         (0x1 << 11)
1409 #define RT5670_JD_HP_TRG_MASK                   (0x1 << 10)
1410 #define RT5670_JD_HP_TRG_SFT                    10
1411 #define RT5670_JD_HP_TRG_LO                     (0x0 << 10)
1412 #define RT5670_JD_HP_TRG_HI                     (0x1 << 10)
1413 #define RT5670_JD_SPL_MASK                      (0x1 << 9)
1414 #define RT5670_JD_SPL_SFT                       9
1415 #define RT5670_JD_SPL_DIS                       (0x0 << 9)
1416 #define RT5670_JD_SPL_EN                        (0x1 << 9)
1417 #define RT5670_JD_SPL_TRG_MASK                  (0x1 << 8)
1418 #define RT5670_JD_SPL_TRG_SFT                   8
1419 #define RT5670_JD_SPL_TRG_LO                    (0x0 << 8)
1420 #define RT5670_JD_SPL_TRG_HI                    (0x1 << 8)
1421 #define RT5670_JD_SPR_MASK                      (0x1 << 7)
1422 #define RT5670_JD_SPR_SFT                       7
1423 #define RT5670_JD_SPR_DIS                       (0x0 << 7)
1424 #define RT5670_JD_SPR_EN                        (0x1 << 7)
1425 #define RT5670_JD_SPR_TRG_MASK                  (0x1 << 6)
1426 #define RT5670_JD_SPR_TRG_SFT                   6
1427 #define RT5670_JD_SPR_TRG_LO                    (0x0 << 6)
1428 #define RT5670_JD_SPR_TRG_HI                    (0x1 << 6)
1429 #define RT5670_JD_MO_MASK                       (0x1 << 5)
1430 #define RT5670_JD_MO_SFT                        5
1431 #define RT5670_JD_MO_DIS                        (0x0 << 5)
1432 #define RT5670_JD_MO_EN                         (0x1 << 5)
1433 #define RT5670_JD_MO_TRG_MASK                   (0x1 << 4)
1434 #define RT5670_JD_MO_TRG_SFT                    4
1435 #define RT5670_JD_MO_TRG_LO                     (0x0 << 4)
1436 #define RT5670_JD_MO_TRG_HI                     (0x1 << 4)
1437 #define RT5670_JD_LO_MASK                       (0x1 << 3)
1438 #define RT5670_JD_LO_SFT                        3
1439 #define RT5670_JD_LO_DIS                        (0x0 << 3)
1440 #define RT5670_JD_LO_EN                         (0x1 << 3)
1441 #define RT5670_JD_LO_TRG_MASK                   (0x1 << 2)
1442 #define RT5670_JD_LO_TRG_SFT                    2
1443 #define RT5670_JD_LO_TRG_LO                     (0x0 << 2)
1444 #define RT5670_JD_LO_TRG_HI                     (0x1 << 2)
1445 #define RT5670_JD1_IN4P_MASK                    (0x1 << 1)
1446 #define RT5670_JD1_IN4P_SFT                     1
1447 #define RT5670_JD1_IN4P_DIS                     (0x0 << 1)
1448 #define RT5670_JD1_IN4P_EN                      (0x1 << 1)
1449 #define RT5670_JD2_IN4N_MASK                    (0x1)
1450 #define RT5670_JD2_IN4N_SFT                     0
1451 #define RT5670_JD2_IN4N_DIS                     (0x0)
1452 #define RT5670_JD2_IN4N_EN                      (0x1)
1453 
1454 /* IRQ Control 1 (0xbd) */
1455 #define RT5670_IRQ_JD_MASK                      (0x1 << 15)
1456 #define RT5670_IRQ_JD_SFT                       15
1457 #define RT5670_IRQ_JD_BP                        (0x0 << 15)
1458 #define RT5670_IRQ_JD_NOR                       (0x1 << 15)
1459 #define RT5670_IRQ_OT_MASK                      (0x1 << 14)
1460 #define RT5670_IRQ_OT_SFT                       14
1461 #define RT5670_IRQ_OT_BP                        (0x0 << 14)
1462 #define RT5670_IRQ_OT_NOR                       (0x1 << 14)
1463 #define RT5670_JD_STKY_MASK                     (0x1 << 13)
1464 #define RT5670_JD_STKY_SFT                      13
1465 #define RT5670_JD_STKY_DIS                      (0x0 << 13)
1466 #define RT5670_JD_STKY_EN                       (0x1 << 13)
1467 #define RT5670_OT_STKY_MASK                     (0x1 << 12)
1468 #define RT5670_OT_STKY_SFT                      12
1469 #define RT5670_OT_STKY_DIS                      (0x0 << 12)
1470 #define RT5670_OT_STKY_EN                       (0x1 << 12)
1471 #define RT5670_JD_P_MASK                        (0x1 << 11)
1472 #define RT5670_JD_P_SFT                         11
1473 #define RT5670_JD_P_NOR                         (0x0 << 11)
1474 #define RT5670_JD_P_INV                         (0x1 << 11)
1475 #define RT5670_OT_P_MASK                        (0x1 << 10)
1476 #define RT5670_OT_P_SFT                         10
1477 #define RT5670_OT_P_NOR                         (0x0 << 10)
1478 #define RT5670_OT_P_INV                         (0x1 << 10)
1479 #define RT5670_JD1_1_EN_MASK                    (0x1 << 9)
1480 #define RT5670_JD1_1_EN_SFT                     9
1481 #define RT5670_JD1_1_DIS                        (0x0 << 9)
1482 #define RT5670_JD1_1_EN                         (0x1 << 9)
1483 
1484 /* IRQ Control 2 (0xbe) */
1485 #define RT5670_IRQ_MB1_OC_MASK                  (0x1 << 15)
1486 #define RT5670_IRQ_MB1_OC_SFT                   15
1487 #define RT5670_IRQ_MB1_OC_BP                    (0x0 << 15)
1488 #define RT5670_IRQ_MB1_OC_NOR                   (0x1 << 15)
1489 #define RT5670_IRQ_MB2_OC_MASK                  (0x1 << 14)
1490 #define RT5670_IRQ_MB2_OC_SFT                   14
1491 #define RT5670_IRQ_MB2_OC_BP                    (0x0 << 14)
1492 #define RT5670_IRQ_MB2_OC_NOR                   (0x1 << 14)
1493 #define RT5670_MB1_OC_STKY_MASK                 (0x1 << 11)
1494 #define RT5670_MB1_OC_STKY_SFT                  11
1495 #define RT5670_MB1_OC_STKY_DIS                  (0x0 << 11)
1496 #define RT5670_MB1_OC_STKY_EN                   (0x1 << 11)
1497 #define RT5670_MB2_OC_STKY_MASK                 (0x1 << 10)
1498 #define RT5670_MB2_OC_STKY_SFT                  10
1499 #define RT5670_MB2_OC_STKY_DIS                  (0x0 << 10)
1500 #define RT5670_MB2_OC_STKY_EN                   (0x1 << 10)
1501 #define RT5670_MB1_OC_P_MASK                    (0x1 << 7)
1502 #define RT5670_MB1_OC_P_SFT                     7
1503 #define RT5670_MB1_OC_P_NOR                     (0x0 << 7)
1504 #define RT5670_MB1_OC_P_INV                     (0x1 << 7)
1505 #define RT5670_MB2_OC_P_MASK                    (0x1 << 6)
1506 #define RT5670_MB2_OC_P_SFT                     6
1507 #define RT5670_MB2_OC_P_NOR                     (0x0 << 6)
1508 #define RT5670_MB2_OC_P_INV                     (0x1 << 6)
1509 #define RT5670_MB1_OC_CLR                       (0x1 << 3)
1510 #define RT5670_MB1_OC_CLR_SFT                   3
1511 #define RT5670_MB2_OC_CLR                       (0x1 << 2)
1512 #define RT5670_MB2_OC_CLR_SFT                   2
1513 
1514 /* GPIO Control 1 (0xc0) */
1515 #define RT5670_GP1_PIN_MASK                     (0x1 << 15)
1516 #define RT5670_GP1_PIN_SFT                      15
1517 #define RT5670_GP1_PIN_GPIO1                    (0x0 << 15)
1518 #define RT5670_GP1_PIN_IRQ                      (0x1 << 15)
1519 #define RT5670_GP2_PIN_MASK                     (0x1 << 14)
1520 #define RT5670_GP2_PIN_SFT                      14
1521 #define RT5670_GP2_PIN_GPIO2                    (0x0 << 14)
1522 #define RT5670_GP2_PIN_DMIC1_SCL                (0x1 << 14)
1523 #define RT5670_GP3_PIN_MASK                     (0x3 << 12)
1524 #define RT5670_GP3_PIN_SFT                      12
1525 #define RT5670_GP3_PIN_GPIO3                    (0x0 << 12)
1526 #define RT5670_GP3_PIN_DMIC1_SDA                (0x1 << 12)
1527 #define RT5670_GP3_PIN_IRQ                      (0x2 << 12)
1528 #define RT5670_GP4_PIN_MASK                     (0x1 << 11)
1529 #define RT5670_GP4_PIN_SFT                      11
1530 #define RT5670_GP4_PIN_GPIO4                    (0x0 << 11)
1531 #define RT5670_GP4_PIN_DMIC2_SDA                (0x1 << 11)
1532 #define RT5670_DP_SIG_MASK                      (0x1 << 10)
1533 #define RT5670_DP_SIG_SFT                       10
1534 #define RT5670_DP_SIG_TEST                      (0x0 << 10)
1535 #define RT5670_DP_SIG_AP                        (0x1 << 10)
1536 #define RT5670_GPIO_M_MASK                      (0x1 << 9)
1537 #define RT5670_GPIO_M_SFT                       9
1538 #define RT5670_GPIO_M_FLT                       (0x0 << 9)
1539 #define RT5670_GPIO_M_PH                        (0x1 << 9)
1540 #define RT5670_I2S2_PIN_MASK                    (0x1 << 8)
1541 #define RT5670_I2S2_PIN_SFT                     8
1542 #define RT5670_I2S2_PIN_I2S                     (0x0 << 8)
1543 #define RT5670_I2S2_PIN_GPIO                    (0x1 << 8)
1544 #define RT5670_GP5_PIN_MASK                     (0x1 << 7)
1545 #define RT5670_GP5_PIN_SFT                      7
1546 #define RT5670_GP5_PIN_GPIO5                    (0x0 << 7)
1547 #define RT5670_GP5_PIN_DMIC3_SDA                (0x1 << 7)
1548 #define RT5670_GP6_PIN_MASK                     (0x1 << 6)
1549 #define RT5670_GP6_PIN_SFT                      6
1550 #define RT5670_GP6_PIN_GPIO6                    (0x0 << 6)
1551 #define RT5670_GP6_PIN_DMIC1_SDA                (0x1 << 6)
1552 #define RT5670_GP7_PIN_MASK                     (0x3 << 4)
1553 #define RT5670_GP7_PIN_SFT                      4
1554 #define RT5670_GP7_PIN_GPIO7                    (0x0 << 4)
1555 #define RT5670_GP7_PIN_DMIC1_SDA                (0x1 << 4)
1556 #define RT5670_GP7_PIN_PDM_SCL2                 (0x2 << 4)
1557 #define RT5670_GP8_PIN_MASK                     (0x1 << 3)
1558 #define RT5670_GP8_PIN_SFT                      3
1559 #define RT5670_GP8_PIN_GPIO8                    (0x0 << 3)
1560 #define RT5670_GP8_PIN_DMIC2_SDA                (0x1 << 3)
1561 #define RT5670_GP9_PIN_MASK                     (0x1 << 2)
1562 #define RT5670_GP9_PIN_SFT                      2
1563 #define RT5670_GP9_PIN_GPIO9                    (0x0 << 2)
1564 #define RT5670_GP9_PIN_DMIC3_SDA                (0x1 << 2)
1565 #define RT5670_GP10_PIN_MASK                    (0x3)
1566 #define RT5670_GP10_PIN_SFT                     0
1567 #define RT5670_GP10_PIN_GPIO9                   (0x0)
1568 #define RT5670_GP10_PIN_DMIC3_SDA               (0x1)
1569 #define RT5670_GP10_PIN_PDM_ADT2                (0x2)
1570 
1571 /* GPIO Control 2 (0xc1) */
1572 #define RT5670_GP4_PF_MASK                      (0x1 << 11)
1573 #define RT5670_GP4_PF_SFT                       11
1574 #define RT5670_GP4_PF_IN                        (0x0 << 11)
1575 #define RT5670_GP4_PF_OUT                       (0x1 << 11)
1576 #define RT5670_GP4_OUT_MASK                     (0x1 << 10)
1577 #define RT5670_GP4_OUT_SFT                      10
1578 #define RT5670_GP4_OUT_LO                       (0x0 << 10)
1579 #define RT5670_GP4_OUT_HI                       (0x1 << 10)
1580 #define RT5670_GP4_P_MASK                       (0x1 << 9)
1581 #define RT5670_GP4_P_SFT                        9
1582 #define RT5670_GP4_P_NOR                        (0x0 << 9)
1583 #define RT5670_GP4_P_INV                        (0x1 << 9)
1584 #define RT5670_GP3_PF_MASK                      (0x1 << 8)
1585 #define RT5670_GP3_PF_SFT                       8
1586 #define RT5670_GP3_PF_IN                        (0x0 << 8)
1587 #define RT5670_GP3_PF_OUT                       (0x1 << 8)
1588 #define RT5670_GP3_OUT_MASK                     (0x1 << 7)
1589 #define RT5670_GP3_OUT_SFT                      7
1590 #define RT5670_GP3_OUT_LO                       (0x0 << 7)
1591 #define RT5670_GP3_OUT_HI                       (0x1 << 7)
1592 #define RT5670_GP3_P_MASK                       (0x1 << 6)
1593 #define RT5670_GP3_P_SFT                        6
1594 #define RT5670_GP3_P_NOR                        (0x0 << 6)
1595 #define RT5670_GP3_P_INV                        (0x1 << 6)
1596 #define RT5670_GP2_PF_MASK                      (0x1 << 5)
1597 #define RT5670_GP2_PF_SFT                       5
1598 #define RT5670_GP2_PF_IN                        (0x0 << 5)
1599 #define RT5670_GP2_PF_OUT                       (0x1 << 5)
1600 #define RT5670_GP2_OUT_MASK                     (0x1 << 4)
1601 #define RT5670_GP2_OUT_SFT                      4
1602 #define RT5670_GP2_OUT_LO                       (0x0 << 4)
1603 #define RT5670_GP2_OUT_HI                       (0x1 << 4)
1604 #define RT5670_GP2_P_MASK                       (0x1 << 3)
1605 #define RT5670_GP2_P_SFT                        3
1606 #define RT5670_GP2_P_NOR                        (0x0 << 3)
1607 #define RT5670_GP2_P_INV                        (0x1 << 3)
1608 #define RT5670_GP1_PF_MASK                      (0x1 << 2)
1609 #define RT5670_GP1_PF_SFT                       2
1610 #define RT5670_GP1_PF_IN                        (0x0 << 2)
1611 #define RT5670_GP1_PF_OUT                       (0x1 << 2)
1612 #define RT5670_GP1_OUT_MASK                     (0x1 << 1)
1613 #define RT5670_GP1_OUT_SFT                      1
1614 #define RT5670_GP1_OUT_LO                       (0x0 << 1)
1615 #define RT5670_GP1_OUT_HI                       (0x1 << 1)
1616 #define RT5670_GP1_P_MASK                       (0x1)
1617 #define RT5670_GP1_P_SFT                        0
1618 #define RT5670_GP1_P_NOR                        (0x0)
1619 #define RT5670_GP1_P_INV                        (0x1)
1620 
1621 /* Scramble Function (0xcd) */
1622 #define RT5670_SCB_KEY_MASK                     (0xff)
1623 #define RT5670_SCB_KEY_SFT                      0
1624 
1625 /* Scramble Control (0xce) */
1626 #define RT5670_SCB_SWAP_MASK                    (0x1 << 15)
1627 #define RT5670_SCB_SWAP_SFT                     15
1628 #define RT5670_SCB_SWAP_DIS                     (0x0 << 15)
1629 #define RT5670_SCB_SWAP_EN                      (0x1 << 15)
1630 #define RT5670_SCB_MASK                         (0x1 << 14)
1631 #define RT5670_SCB_SFT                          14
1632 #define RT5670_SCB_DIS                          (0x0 << 14)
1633 #define RT5670_SCB_EN                           (0x1 << 14)
1634 
1635 /* Baseback Control (0xcf) */
1636 #define RT5670_BB_MASK                          (0x1 << 15)
1637 #define RT5670_BB_SFT                           15
1638 #define RT5670_BB_DIS                           (0x0 << 15)
1639 #define RT5670_BB_EN                            (0x1 << 15)
1640 #define RT5670_BB_CT_MASK                       (0x7 << 12)
1641 #define RT5670_BB_CT_SFT                        12
1642 #define RT5670_BB_CT_A                          (0x0 << 12)
1643 #define RT5670_BB_CT_B                          (0x1 << 12)
1644 #define RT5670_BB_CT_C                          (0x2 << 12)
1645 #define RT5670_BB_CT_D                          (0x3 << 12)
1646 #define RT5670_M_BB_L_MASK                      (0x1 << 9)
1647 #define RT5670_M_BB_L_SFT                       9
1648 #define RT5670_M_BB_R_MASK                      (0x1 << 8)
1649 #define RT5670_M_BB_R_SFT                       8
1650 #define RT5670_M_BB_HPF_L_MASK                  (0x1 << 7)
1651 #define RT5670_M_BB_HPF_L_SFT                   7
1652 #define RT5670_M_BB_HPF_R_MASK                  (0x1 << 6)
1653 #define RT5670_M_BB_HPF_R_SFT                   6
1654 #define RT5670_G_BB_BST_MASK                    (0x3f)
1655 #define RT5670_G_BB_BST_SFT                     0
1656 
1657 /* MP3 Plus Control 1 (0xd0) */
1658 #define RT5670_M_MP3_L_MASK                     (0x1 << 15)
1659 #define RT5670_M_MP3_L_SFT                      15
1660 #define RT5670_M_MP3_R_MASK                     (0x1 << 14)
1661 #define RT5670_M_MP3_R_SFT                      14
1662 #define RT5670_M_MP3_MASK                       (0x1 << 13)
1663 #define RT5670_M_MP3_SFT                        13
1664 #define RT5670_M_MP3_DIS                        (0x0 << 13)
1665 #define RT5670_M_MP3_EN                         (0x1 << 13)
1666 #define RT5670_EG_MP3_MASK                      (0x1f << 8)
1667 #define RT5670_EG_MP3_SFT                       8
1668 #define RT5670_MP3_HLP_MASK                     (0x1 << 7)
1669 #define RT5670_MP3_HLP_SFT                      7
1670 #define RT5670_MP3_HLP_DIS                      (0x0 << 7)
1671 #define RT5670_MP3_HLP_EN                       (0x1 << 7)
1672 #define RT5670_M_MP3_ORG_L_MASK                 (0x1 << 6)
1673 #define RT5670_M_MP3_ORG_L_SFT                  6
1674 #define RT5670_M_MP3_ORG_R_MASK                 (0x1 << 5)
1675 #define RT5670_M_MP3_ORG_R_SFT                  5
1676 
1677 /* MP3 Plus Control 2 (0xd1) */
1678 #define RT5670_MP3_WT_MASK                      (0x1 << 13)
1679 #define RT5670_MP3_WT_SFT                       13
1680 #define RT5670_MP3_WT_1_4                       (0x0 << 13)
1681 #define RT5670_MP3_WT_1_2                       (0x1 << 13)
1682 #define RT5670_OG_MP3_MASK                      (0x1f << 8)
1683 #define RT5670_OG_MP3_SFT                       8
1684 #define RT5670_HG_MP3_MASK                      (0x3f)
1685 #define RT5670_HG_MP3_SFT                       0
1686 
1687 /* 3D HP Control 1 (0xd2) */
1688 #define RT5670_3D_CF_MASK                       (0x1 << 15)
1689 #define RT5670_3D_CF_SFT                        15
1690 #define RT5670_3D_CF_DIS                        (0x0 << 15)
1691 #define RT5670_3D_CF_EN                         (0x1 << 15)
1692 #define RT5670_3D_HP_MASK                       (0x1 << 14)
1693 #define RT5670_3D_HP_SFT                        14
1694 #define RT5670_3D_HP_DIS                        (0x0 << 14)
1695 #define RT5670_3D_HP_EN                         (0x1 << 14)
1696 #define RT5670_3D_BT_MASK                       (0x1 << 13)
1697 #define RT5670_3D_BT_SFT                        13
1698 #define RT5670_3D_BT_DIS                        (0x0 << 13)
1699 #define RT5670_3D_BT_EN                         (0x1 << 13)
1700 #define RT5670_3D_1F_MIX_MASK                   (0x3 << 11)
1701 #define RT5670_3D_1F_MIX_SFT                    11
1702 #define RT5670_3D_HP_M_MASK                     (0x1 << 10)
1703 #define RT5670_3D_HP_M_SFT                      10
1704 #define RT5670_3D_HP_M_SUR                      (0x0 << 10)
1705 #define RT5670_3D_HP_M_FRO                      (0x1 << 10)
1706 #define RT5670_M_3D_HRTF_MASK                   (0x1 << 9)
1707 #define RT5670_M_3D_HRTF_SFT                    9
1708 #define RT5670_M_3D_D2H_MASK                    (0x1 << 8)
1709 #define RT5670_M_3D_D2H_SFT                     8
1710 #define RT5670_M_3D_D2R_MASK                    (0x1 << 7)
1711 #define RT5670_M_3D_D2R_SFT                     7
1712 #define RT5670_M_3D_REVB_MASK                   (0x1 << 6)
1713 #define RT5670_M_3D_REVB_SFT                    6
1714 
1715 /* Adjustable high pass filter control 1 (0xd3) */
1716 #define RT5670_2ND_HPF_MASK                     (0x1 << 15)
1717 #define RT5670_2ND_HPF_SFT                      15
1718 #define RT5670_2ND_HPF_DIS                      (0x0 << 15)
1719 #define RT5670_2ND_HPF_EN                       (0x1 << 15)
1720 #define RT5670_HPF_CF_L_MASK                    (0x7 << 12)
1721 #define RT5670_HPF_CF_L_SFT                     12
1722 #define RT5670_1ST_HPF_MASK                     (0x1 << 11)
1723 #define RT5670_1ST_HPF_SFT                      11
1724 #define RT5670_1ST_HPF_DIS                      (0x0 << 11)
1725 #define RT5670_1ST_HPF_EN                       (0x1 << 11)
1726 #define RT5670_HPF_CF_R_MASK                    (0x7 << 8)
1727 #define RT5670_HPF_CF_R_SFT                     8
1728 #define RT5670_ZD_T_MASK                        (0x3 << 6)
1729 #define RT5670_ZD_T_SFT                         6
1730 #define RT5670_ZD_F_MASK                        (0x3 << 4)
1731 #define RT5670_ZD_F_SFT                         4
1732 #define RT5670_ZD_F_IM                          (0x0 << 4)
1733 #define RT5670_ZD_F_ZC_IM                       (0x1 << 4)
1734 #define RT5670_ZD_F_ZC_IOD                      (0x2 << 4)
1735 #define RT5670_ZD_F_UN                          (0x3 << 4)
1736 
1737 /* HP calibration control and Amp detection (0xd6) */
1738 #define RT5670_SI_DAC_MASK                      (0x1 << 11)
1739 #define RT5670_SI_DAC_SFT                       11
1740 #define RT5670_SI_DAC_AUTO                      (0x0 << 11)
1741 #define RT5670_SI_DAC_TEST                      (0x1 << 11)
1742 #define RT5670_DC_CAL_M_MASK                    (0x1 << 10)
1743 #define RT5670_DC_CAL_M_SFT                     10
1744 #define RT5670_DC_CAL_M_CAL                     (0x0 << 10)
1745 #define RT5670_DC_CAL_M_NOR                     (0x1 << 10)
1746 #define RT5670_DC_CAL_MASK                      (0x1 << 9)
1747 #define RT5670_DC_CAL_SFT                       9
1748 #define RT5670_DC_CAL_DIS                       (0x0 << 9)
1749 #define RT5670_DC_CAL_EN                        (0x1 << 9)
1750 #define RT5670_HPD_RCV_MASK                     (0x7 << 6)
1751 #define RT5670_HPD_RCV_SFT                      6
1752 #define RT5670_HPD_PS_MASK                      (0x1 << 5)
1753 #define RT5670_HPD_PS_SFT                       5
1754 #define RT5670_HPD_PS_DIS                       (0x0 << 5)
1755 #define RT5670_HPD_PS_EN                        (0x1 << 5)
1756 #define RT5670_CAL_M_MASK                       (0x1 << 4)
1757 #define RT5670_CAL_M_SFT                        4
1758 #define RT5670_CAL_M_DEP                        (0x0 << 4)
1759 #define RT5670_CAL_M_CAL                        (0x1 << 4)
1760 #define RT5670_CAL_MASK                         (0x1 << 3)
1761 #define RT5670_CAL_SFT                          3
1762 #define RT5670_CAL_DIS                          (0x0 << 3)
1763 #define RT5670_CAL_EN                           (0x1 << 3)
1764 #define RT5670_CAL_TEST_MASK                    (0x1 << 2)
1765 #define RT5670_CAL_TEST_SFT                     2
1766 #define RT5670_CAL_TEST_DIS                     (0x0 << 2)
1767 #define RT5670_CAL_TEST_EN                      (0x1 << 2)
1768 #define RT5670_CAL_P_MASK                       (0x3)
1769 #define RT5670_CAL_P_SFT                        0
1770 #define RT5670_CAL_P_NONE                       (0x0)
1771 #define RT5670_CAL_P_CAL                        (0x1)
1772 #define RT5670_CAL_P_DAC_CAL                    (0x2)
1773 
1774 /* Soft volume and zero cross control 1 (0xd9) */
1775 #define RT5670_SV_MASK                          (0x1 << 15)
1776 #define RT5670_SV_SFT                           15
1777 #define RT5670_SV_DIS                           (0x0 << 15)
1778 #define RT5670_SV_EN                            (0x1 << 15)
1779 #define RT5670_SPO_SV_MASK                      (0x1 << 14)
1780 #define RT5670_SPO_SV_SFT                       14
1781 #define RT5670_SPO_SV_DIS                       (0x0 << 14)
1782 #define RT5670_SPO_SV_EN                        (0x1 << 14)
1783 #define RT5670_OUT_SV_MASK                      (0x1 << 13)
1784 #define RT5670_OUT_SV_SFT                       13
1785 #define RT5670_OUT_SV_DIS                       (0x0 << 13)
1786 #define RT5670_OUT_SV_EN                        (0x1 << 13)
1787 #define RT5670_HP_SV_MASK                       (0x1 << 12)
1788 #define RT5670_HP_SV_SFT                        12
1789 #define RT5670_HP_SV_DIS                        (0x0 << 12)
1790 #define RT5670_HP_SV_EN                         (0x1 << 12)
1791 #define RT5670_ZCD_DIG_MASK                     (0x1 << 11)
1792 #define RT5670_ZCD_DIG_SFT                      11
1793 #define RT5670_ZCD_DIG_DIS                      (0x0 << 11)
1794 #define RT5670_ZCD_DIG_EN                       (0x1 << 11)
1795 #define RT5670_ZCD_MASK                         (0x1 << 10)
1796 #define RT5670_ZCD_SFT                          10
1797 #define RT5670_ZCD_PD                           (0x0 << 10)
1798 #define RT5670_ZCD_PU                           (0x1 << 10)
1799 #define RT5670_M_ZCD_MASK                       (0x3f << 4)
1800 #define RT5670_M_ZCD_SFT                        4
1801 #define RT5670_M_ZCD_RM_L                       (0x1 << 9)
1802 #define RT5670_M_ZCD_RM_R                       (0x1 << 8)
1803 #define RT5670_M_ZCD_SM_L                       (0x1 << 7)
1804 #define RT5670_M_ZCD_SM_R                       (0x1 << 6)
1805 #define RT5670_M_ZCD_OM_L                       (0x1 << 5)
1806 #define RT5670_M_ZCD_OM_R                       (0x1 << 4)
1807 #define RT5670_SV_DLY_MASK                      (0xf)
1808 #define RT5670_SV_DLY_SFT                       0
1809 
1810 /* Soft volume and zero cross control 2 (0xda) */
1811 #define RT5670_ZCD_HP_MASK                      (0x1 << 15)
1812 #define RT5670_ZCD_HP_SFT                       15
1813 #define RT5670_ZCD_HP_DIS                       (0x0 << 15)
1814 #define RT5670_ZCD_HP_EN                        (0x1 << 15)
1815 
1816 /* General Control 3 (0xfc) */
1817 #define RT5670_TDM_DATA_MODE_SEL                (0x1 << 11)
1818 #define RT5670_TDM_DATA_MODE_NOR                (0x0 << 11)
1819 #define RT5670_TDM_DATA_MODE_50FS               (0x1 << 11)
1820 
1821 /* Codec Private Register definition */
1822 /* 3D Speaker Control (0x63) */
1823 #define RT5670_3D_SPK_MASK                      (0x1 << 15)
1824 #define RT5670_3D_SPK_SFT                       15
1825 #define RT5670_3D_SPK_DIS                       (0x0 << 15)
1826 #define RT5670_3D_SPK_EN                        (0x1 << 15)
1827 #define RT5670_3D_SPK_M_MASK                    (0x3 << 13)
1828 #define RT5670_3D_SPK_M_SFT                     13
1829 #define RT5670_3D_SPK_CG_MASK                   (0x1f << 8)
1830 #define RT5670_3D_SPK_CG_SFT                    8
1831 #define RT5670_3D_SPK_SG_MASK                   (0x1f)
1832 #define RT5670_3D_SPK_SG_SFT                    0
1833 
1834 /* Wind Noise Detection Control 1 (0x6c) */
1835 #define RT5670_WND_MASK                         (0x1 << 15)
1836 #define RT5670_WND_SFT                          15
1837 #define RT5670_WND_DIS                          (0x0 << 15)
1838 #define RT5670_WND_EN                           (0x1 << 15)
1839 
1840 /* Wind Noise Detection Control 2 (0x6d) */
1841 #define RT5670_WND_FC_NW_MASK                   (0x3f << 10)
1842 #define RT5670_WND_FC_NW_SFT                    10
1843 #define RT5670_WND_FC_WK_MASK                   (0x3f << 4)
1844 #define RT5670_WND_FC_WK_SFT                    4
1845 
1846 /* Wind Noise Detection Control 3 (0x6e) */
1847 #define RT5670_HPF_FC_MASK                      (0x3f << 6)
1848 #define RT5670_HPF_FC_SFT                       6
1849 #define RT5670_WND_FC_ST_MASK                   (0x3f)
1850 #define RT5670_WND_FC_ST_SFT                    0
1851 
1852 /* Wind Noise Detection Control 4 (0x6f) */
1853 #define RT5670_WND_TH_LO_MASK                   (0x3ff)
1854 #define RT5670_WND_TH_LO_SFT                    0
1855 
1856 /* Wind Noise Detection Control 5 (0x70) */
1857 #define RT5670_WND_TH_HI_MASK                   (0x3ff)
1858 #define RT5670_WND_TH_HI_SFT                    0
1859 
1860 /* Wind Noise Detection Control 8 (0x73) */
1861 #define RT5670_WND_WIND_MASK                    (0x1 << 13) /* Read-Only */
1862 #define RT5670_WND_WIND_SFT                     13
1863 #define RT5670_WND_STRONG_MASK                  (0x1 << 12) /* Read-Only */
1864 #define RT5670_WND_STRONG_SFT                   12
1865 enum {
1866         RT5670_NO_WIND,
1867         RT5670_BREEZE,
1868         RT5670_STORM,
1869 };
1870 
1871 /* Dipole Speaker Interface (0x75) */
1872 #define RT5670_DP_ATT_MASK                      (0x3 << 14)
1873 #define RT5670_DP_ATT_SFT                       14
1874 #define RT5670_DP_SPK_MASK                      (0x1 << 10)
1875 #define RT5670_DP_SPK_SFT                       10
1876 #define RT5670_DP_SPK_DIS                       (0x0 << 10)
1877 #define RT5670_DP_SPK_EN                        (0x1 << 10)
1878 
1879 /* EQ Pre Volume Control (0xb3) */
1880 #define RT5670_EQ_PRE_VOL_MASK                  (0xffff)
1881 #define RT5670_EQ_PRE_VOL_SFT                   0
1882 
1883 /* EQ Post Volume Control (0xb4) */
1884 #define RT5670_EQ_PST_VOL_MASK                  (0xffff)
1885 #define RT5670_EQ_PST_VOL_SFT                   0
1886 
1887 /* Jack Detect Control 3 (0xf8) */
1888 #define RT5670_CMP_MIC_IN_DET_MASK              (0x7 << 12)
1889 #define RT5670_JD_CBJ_EN                        (0x1 << 7)
1890 #define RT5670_JD_CBJ_POL                       (0x1 << 6)
1891 #define RT5670_JD_TRI_CBJ_SEL_MASK              (0x7 << 3)
1892 #define RT5670_JD_TRI_CBJ_SEL_SFT               (3)
1893 #define RT5670_JD_CBJ_GPIO_JD1                  (0x0 << 3)
1894 #define RT5670_JD_CBJ_JD1_1                     (0x1 << 3)
1895 #define RT5670_JD_CBJ_JD1_2                     (0x2 << 3)
1896 #define RT5670_JD_CBJ_JD2                       (0x3 << 3)
1897 #define RT5670_JD_CBJ_JD3                       (0x4 << 3)
1898 #define RT5670_JD_CBJ_GPIO_JD2                  (0x5 << 3)
1899 #define RT5670_JD_CBJ_MX0B_12                   (0x6 << 3)
1900 #define RT5670_JD_TRI_HPO_SEL_MASK              (0x7 << 3)
1901 #define RT5670_JD_TRI_HPO_SEL_SFT               (0)
1902 #define RT5670_JD_HPO_GPIO_JD1                  (0x0)
1903 #define RT5670_JD_HPO_JD1_1                     (0x1)
1904 #define RT5670_JD_HPO_JD1_2                     (0x2)
1905 #define RT5670_JD_HPO_JD2                       (0x3)
1906 #define RT5670_JD_HPO_JD3                       (0x4)
1907 #define RT5670_JD_HPO_GPIO_JD2                  (0x5)
1908 #define RT5670_JD_HPO_MX0B_12                   (0x6)
1909 
1910 /* Digital Misc Control (0xfa) */
1911 #define RT5670_RST_DSP                          (0x1 << 13)
1912 #define RT5670_IF1_ADC1_IN1_SEL                 (0x1 << 12)
1913 #define RT5670_IF1_ADC1_IN1_SFT                 12
1914 #define RT5670_IF1_ADC1_IN2_SEL                 (0x1 << 11)
1915 #define RT5670_IF1_ADC1_IN2_SFT                 11
1916 #define RT5670_IF1_ADC2_IN1_SEL                 (0x1 << 10)
1917 #define RT5670_IF1_ADC2_IN1_SFT                 10
1918 #define RT5670_MCLK_DET                         (0x1 << 3)
1919 
1920 /* General Control2 (0xfb) */
1921 #define RT5670_RXDC_SRC_MASK                    (0x1 << 7)
1922 #define RT5670_RXDC_SRC_STO                     (0x0 << 7)
1923 #define RT5670_RXDC_SRC_MONO                    (0x1 << 7)
1924 #define RT5670_RXDC_SRC_SFT                     (7)
1925 #define RT5670_RXDP2_SEL_MASK                   (0x1 << 3)
1926 #define RT5670_RXDP2_SEL_IF2                    (0x0 << 3)
1927 #define RT5670_RXDP2_SEL_ADC                    (0x1 << 3)
1928 #define RT5670_RXDP2_SEL_SFT                    (3)
1929 
1930 /* System Clock Source */
1931 enum {
1932         RT5670_SCLK_S_MCLK,
1933         RT5670_SCLK_S_PLL1,
1934         RT5670_SCLK_S_RCCLK,
1935 };
1936 
1937 /* PLL1 Source */
1938 enum {
1939         RT5670_PLL1_S_MCLK,
1940         RT5670_PLL1_S_BCLK1,
1941         RT5670_PLL1_S_BCLK2,
1942         RT5670_PLL1_S_BCLK3,
1943         RT5670_PLL1_S_BCLK4,
1944 };
1945 
1946 enum {
1947         RT5670_AIF1,
1948         RT5670_AIF2,
1949         RT5670_AIF3,
1950         RT5670_AIF4,
1951         RT5670_AIFS,
1952 };
1953 
1954 enum {
1955         RT5670_DMIC1_DISABLED,
1956         RT5670_DMIC_DATA_GPIO6,
1957         RT5670_DMIC_DATA_IN2P,
1958         RT5670_DMIC_DATA_GPIO7,
1959 };
1960 
1961 enum {
1962         RT5670_DMIC2_DISABLED,
1963         RT5670_DMIC_DATA_GPIO8,
1964         RT5670_DMIC_DATA_IN3N,
1965 };
1966 
1967 enum {
1968         RT5670_DMIC3_DISABLED,
1969         RT5670_DMIC_DATA_GPIO9,
1970         RT5670_DMIC_DATA_GPIO10,
1971         RT5670_DMIC_DATA_GPIO5,
1972 };
1973 
1974 /* filter mask */
1975 enum {
1976         RT5670_DA_STEREO_FILTER = 0x1,
1977         RT5670_DA_MONO_L_FILTER = (0x1 << 1),
1978         RT5670_DA_MONO_R_FILTER = (0x1 << 2),
1979         RT5670_AD_STEREO_FILTER = (0x1 << 3),
1980         RT5670_AD_MONO_L_FILTER = (0x1 << 4),
1981         RT5670_AD_MONO_R_FILTER = (0x1 << 5),
1982         RT5670_UP_RATE_FILTER   = (0x1 << 6),
1983         RT5670_DOWN_RATE_FILTER = (0x1 << 7),
1984 };
1985 
1986 int rt5670_sel_asrc_clk_src(struct snd_soc_component *component,
1987                             unsigned int filter_mask, unsigned int clk_src);
1988 
1989 struct rt5670_priv {
1990         struct snd_soc_component *component;
1991         struct rt5670_platform_data pdata;
1992         struct regmap *regmap;
1993         struct snd_soc_jack *jack;
1994         struct snd_soc_jack_gpio hp_gpio;
1995 
1996         int sysclk;
1997         int sysclk_src;
1998         int lrck[RT5670_AIFS];
1999         int bclk[RT5670_AIFS];
2000         int master[RT5670_AIFS];
2001 
2002         int pll_src;
2003         int pll_in;
2004         int pll_out;
2005 
2006         int dsp_sw; /* expected parameter setting */
2007         int dsp_rate;
2008         int jack_type;
2009         int jack_type_saved;
2010 };
2011 
2012 void rt5670_jack_suspend(struct snd_soc_component *component);
2013 void rt5670_jack_resume(struct snd_soc_component *component);
2014 int rt5670_set_jack_detect(struct snd_soc_component *component,
2015         struct snd_soc_jack *jack);
2016 #endif /* __RT5670_H__ */