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9 #ifndef __RT5645_H__
10 #define __RT5645_H__
11
12 #include <sound/rt5645.h>
13
14
15 #define RT5645_RESET 0x00
16 #define RT5645_VENDOR_ID 0xfd
17 #define RT5645_VENDOR_ID1 0xfe
18 #define RT5645_VENDOR_ID2 0xff
19
20 #define RT5645_SPK_VOL 0x01
21 #define RT5645_HP_VOL 0x02
22 #define RT5645_LOUT1 0x03
23 #define RT5645_LOUT_CTRL 0x05
24
25 #define RT5645_IN1_CTRL1 0x0a
26 #define RT5645_IN1_CTRL2 0x0b
27 #define RT5645_IN1_CTRL3 0x0c
28 #define RT5645_IN2_CTRL 0x0d
29 #define RT5645_INL1_INR1_VOL 0x0f
30 #define RT5645_SPK_FUNC_LIM 0x14
31 #define RT5645_ADJ_HPF_CTRL 0x16
32
33 #define RT5645_DAC1_DIG_VOL 0x19
34 #define RT5645_DAC2_DIG_VOL 0x1a
35 #define RT5645_DAC_CTRL 0x1b
36 #define RT5645_STO1_ADC_DIG_VOL 0x1c
37 #define RT5645_MONO_ADC_DIG_VOL 0x1d
38 #define RT5645_ADC_BST_VOL1 0x1e
39 #define RT5645_ADC_BST_VOL2 0x20
40
41 #define RT5645_STO1_ADC_MIXER 0x27
42 #define RT5645_MONO_ADC_MIXER 0x28
43 #define RT5645_AD_DA_MIXER 0x29
44 #define RT5645_STO_DAC_MIXER 0x2a
45 #define RT5645_MONO_DAC_MIXER 0x2b
46 #define RT5645_DIG_MIXER 0x2c
47 #define RT5650_A_DAC_SOUR 0x2d
48 #define RT5645_DIG_INF1_DATA 0x2f
49
50 #define RT5645_PDM_OUT_CTRL 0x31
51
52 #define RT5645_REC_L1_MIXER 0x3b
53 #define RT5645_REC_L2_MIXER 0x3c
54 #define RT5645_REC_R1_MIXER 0x3d
55 #define RT5645_REC_R2_MIXER 0x3e
56
57 #define RT5645_HPMIXL_CTRL 0x3f
58 #define RT5645_HPOMIXL_CTRL 0x40
59 #define RT5645_HPMIXR_CTRL 0x41
60 #define RT5645_HPOMIXR_CTRL 0x42
61 #define RT5645_HPO_MIXER 0x45
62 #define RT5645_SPK_L_MIXER 0x46
63 #define RT5645_SPK_R_MIXER 0x47
64 #define RT5645_SPO_MIXER 0x48
65 #define RT5645_SPO_CLSD_RATIO 0x4a
66 #define RT5645_OUT_L_GAIN1 0x4d
67 #define RT5645_OUT_L_GAIN2 0x4e
68 #define RT5645_OUT_L1_MIXER 0x4f
69 #define RT5645_OUT_R_GAIN1 0x50
70 #define RT5645_OUT_R_GAIN2 0x51
71 #define RT5645_OUT_R1_MIXER 0x52
72 #define RT5645_LOUT_MIXER 0x53
73
74 #define RT5645_HAPTIC_CTRL1 0x56
75 #define RT5645_HAPTIC_CTRL2 0x57
76 #define RT5645_HAPTIC_CTRL3 0x58
77 #define RT5645_HAPTIC_CTRL4 0x59
78 #define RT5645_HAPTIC_CTRL5 0x5a
79 #define RT5645_HAPTIC_CTRL6 0x5b
80 #define RT5645_HAPTIC_CTRL7 0x5c
81 #define RT5645_HAPTIC_CTRL8 0x5d
82 #define RT5645_HAPTIC_CTRL9 0x5e
83 #define RT5645_HAPTIC_CTRL10 0x5f
84
85 #define RT5645_PWR_DIG1 0x61
86 #define RT5645_PWR_DIG2 0x62
87 #define RT5645_PWR_ANLG1 0x63
88 #define RT5645_PWR_ANLG2 0x64
89 #define RT5645_PWR_MIXER 0x65
90 #define RT5645_PWR_VOL 0x66
91
92 #define RT5645_PRIV_INDEX 0x6a
93 #define RT5645_PRIV_DATA 0x6c
94
95 #define RT5645_I2S1_SDP 0x70
96 #define RT5645_I2S2_SDP 0x71
97 #define RT5645_ADDA_CLK1 0x73
98 #define RT5645_ADDA_CLK2 0x74
99 #define RT5645_DMIC_CTRL1 0x75
100 #define RT5645_DMIC_CTRL2 0x76
101
102 #define RT5645_TDM_CTRL_1 0x77
103 #define RT5645_TDM_CTRL_2 0x78
104 #define RT5645_TDM_CTRL_3 0x79
105 #define RT5650_TDM_CTRL_4 0x7a
106
107
108 #define RT5645_GLB_CLK 0x80
109 #define RT5645_PLL_CTRL1 0x81
110 #define RT5645_PLL_CTRL2 0x82
111 #define RT5645_ASRC_1 0x83
112 #define RT5645_ASRC_2 0x84
113 #define RT5645_ASRC_3 0x85
114 #define RT5645_ASRC_4 0x8a
115 #define RT5645_DEPOP_M1 0x8e
116 #define RT5645_DEPOP_M2 0x8f
117 #define RT5645_DEPOP_M3 0x90
118 #define RT5645_CHARGE_PUMP 0x91
119 #define RT5645_MICBIAS 0x93
120 #define RT5645_A_JD_CTRL1 0x94
121 #define RT5645_VAD_CTRL4 0x9d
122 #define RT5645_CLSD_OUT_CTRL 0xa0
123
124 #define RT5645_ADC_EQ_CTRL1 0xae
125 #define RT5645_ADC_EQ_CTRL2 0xaf
126 #define RT5645_EQ_CTRL1 0xb0
127 #define RT5645_EQ_CTRL2 0xb1
128 #define RT5645_ALC_CTRL_1 0xb3
129 #define RT5645_ALC_CTRL_2 0xb4
130 #define RT5645_ALC_CTRL_3 0xb5
131 #define RT5645_ALC_CTRL_4 0xb6
132 #define RT5645_ALC_CTRL_5 0xb7
133 #define RT5645_JD_CTRL 0xbb
134 #define RT5645_IRQ_CTRL1 0xbc
135 #define RT5645_IRQ_CTRL2 0xbd
136 #define RT5645_IRQ_CTRL3 0xbe
137 #define RT5645_INT_IRQ_ST 0xbf
138 #define RT5645_GPIO_CTRL1 0xc0
139 #define RT5645_GPIO_CTRL2 0xc1
140 #define RT5645_GPIO_CTRL3 0xc2
141 #define RT5645_BASS_BACK 0xcf
142 #define RT5645_MP3_PLUS1 0xd0
143 #define RT5645_MP3_PLUS2 0xd1
144 #define RT5645_ADJ_HPF1 0xd3
145 #define RT5645_ADJ_HPF2 0xd4
146 #define RT5645_HP_CALIB_AMP_DET 0xd6
147 #define RT5645_SV_ZCD1 0xd9
148 #define RT5645_SV_ZCD2 0xda
149 #define RT5645_IL_CMD 0xdb
150 #define RT5645_IL_CMD2 0xdc
151 #define RT5645_IL_CMD3 0xdd
152 #define RT5650_4BTN_IL_CMD1 0xdf
153 #define RT5650_4BTN_IL_CMD2 0xe0
154 #define RT5645_DRC1_HL_CTRL1 0xe7
155 #define RT5645_DRC2_HL_CTRL1 0xe9
156 #define RT5645_MUTI_DRC_CTRL1 0xea
157 #define RT5645_ADC_MONO_HP_CTRL1 0xec
158 #define RT5645_ADC_MONO_HP_CTRL2 0xed
159 #define RT5645_DRC2_CTRL1 0xf0
160 #define RT5645_DRC2_CTRL2 0xf1
161 #define RT5645_DRC2_CTRL3 0xf2
162 #define RT5645_DRC2_CTRL4 0xf3
163 #define RT5645_DRC2_CTRL5 0xf4
164 #define RT5645_JD_CTRL3 0xf8
165 #define RT5645_JD_CTRL4 0xf9
166
167 #define RT5645_GEN_CTRL1 0xfa
168 #define RT5645_GEN_CTRL2 0xfb
169 #define RT5645_GEN_CTRL3 0xfc
170
171
172
173 #define RT5645_DIG_VOL 0x00
174 #define RT5645_PR_ALC_CTRL_1 0x01
175 #define RT5645_PR_ALC_CTRL_2 0x02
176 #define RT5645_PR_ALC_CTRL_3 0x03
177 #define RT5645_PR_ALC_CTRL_4 0x04
178 #define RT5645_PR_ALC_CTRL_5 0x05
179 #define RT5645_PR_ALC_CTRL_6 0x06
180 #define RT5645_BIAS_CUR1 0x12
181 #define RT5645_BIAS_CUR3 0x14
182 #define RT5645_CLSD_INT_REG1 0x1c
183 #define RT5645_MAMP_INT_REG2 0x37
184 #define RT5645_CHOP_DAC_ADC 0x3d
185 #define RT5645_MIXER_INT_REG 0x3f
186 #define RT5645_3D_SPK 0x63
187 #define RT5645_WND_1 0x6c
188 #define RT5645_WND_2 0x6d
189 #define RT5645_WND_3 0x6e
190 #define RT5645_WND_4 0x6f
191 #define RT5645_WND_5 0x70
192 #define RT5645_WND_8 0x73
193 #define RT5645_DIP_SPK_INF 0x75
194 #define RT5645_HP_DCC_INT1 0x77
195 #define RT5645_EQ_BW_LOP 0xa0
196 #define RT5645_EQ_GN_LOP 0xa1
197 #define RT5645_EQ_FC_BP1 0xa2
198 #define RT5645_EQ_BW_BP1 0xa3
199 #define RT5645_EQ_GN_BP1 0xa4
200 #define RT5645_EQ_FC_BP2 0xa5
201 #define RT5645_EQ_BW_BP2 0xa6
202 #define RT5645_EQ_GN_BP2 0xa7
203 #define RT5645_EQ_FC_BP3 0xa8
204 #define RT5645_EQ_BW_BP3 0xa9
205 #define RT5645_EQ_GN_BP3 0xaa
206 #define RT5645_EQ_FC_BP4 0xab
207 #define RT5645_EQ_BW_BP4 0xac
208 #define RT5645_EQ_GN_BP4 0xad
209 #define RT5645_EQ_FC_HIP1 0xae
210 #define RT5645_EQ_GN_HIP1 0xaf
211 #define RT5645_EQ_FC_HIP2 0xb0
212 #define RT5645_EQ_BW_HIP2 0xb1
213 #define RT5645_EQ_GN_HIP2 0xb2
214 #define RT5645_EQ_PRE_VOL 0xb3
215 #define RT5645_EQ_PST_VOL 0xb4
216
217
218
219 #define RT5645_L_MUTE (0x1 << 15)
220 #define RT5645_L_MUTE_SFT 15
221 #define RT5645_VOL_L_MUTE (0x1 << 14)
222 #define RT5645_VOL_L_SFT 14
223 #define RT5645_R_MUTE (0x1 << 7)
224 #define RT5645_R_MUTE_SFT 7
225 #define RT5645_VOL_R_MUTE (0x1 << 6)
226 #define RT5645_VOL_R_SFT 6
227 #define RT5645_L_VOL_MASK (0x3f << 8)
228 #define RT5645_L_VOL_SFT 8
229 #define RT5645_R_VOL_MASK (0x3f)
230 #define RT5645_R_VOL_SFT 0
231
232
233 #define RT5645_CBJ_BST1_MASK (0xf << 12)
234 #define RT5645_CBJ_BST1_SFT (12)
235 #define RT5645_CBJ_JD_HP_EN (0x1 << 9)
236 #define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
237 #define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7)
238 #define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
239 #define RT5645_CBJ_MIC_SEL_L (0x1 << 5)
240 #define RT5645_CBJ_MIC_SW (0x1 << 4)
241 #define RT5645_CBJ_BST1_EN (0x1 << 2)
242
243
244 #define RT5645_CBJ_MN_JD (0x1 << 12)
245 #define RT5645_CAPLESS_EN (0x1 << 11)
246 #define RT5645_CBJ_DET_MODE (0x1 << 7)
247
248
249 #define RT5645_CBJ_TIE_G_L (0x1 << 15)
250 #define RT5645_CBJ_TIE_G_R (0x1 << 14)
251
252
253 #define RT5645_BST_MASK1 (0xf<<12)
254 #define RT5645_BST_SFT1 12
255 #define RT5645_BST_MASK2 (0xf<<8)
256 #define RT5645_BST_SFT2 8
257 #define RT5645_IN_DF2 (0x1 << 6)
258 #define RT5645_IN_SFT2 6
259
260
261 #define RT5645_INL_SEL_MASK (0x1 << 15)
262 #define RT5645_INL_SEL_SFT 15
263 #define RT5645_INL_SEL_IN4P (0x0 << 15)
264 #define RT5645_INL_SEL_MONOP (0x1 << 15)
265 #define RT5645_INL_VOL_MASK (0x1f << 8)
266 #define RT5645_INL_VOL_SFT 8
267 #define RT5645_INR_SEL_MASK (0x1 << 7)
268 #define RT5645_INR_SEL_SFT 7
269 #define RT5645_INR_SEL_IN4N (0x0 << 7)
270 #define RT5645_INR_SEL_MONON (0x1 << 7)
271 #define RT5645_INR_VOL_MASK (0x1f)
272 #define RT5645_INR_VOL_SFT 0
273
274
275 #define RT5645_DAC_L1_VOL_MASK (0xff << 8)
276 #define RT5645_DAC_L1_VOL_SFT 8
277 #define RT5645_DAC_R1_VOL_MASK (0xff)
278 #define RT5645_DAC_R1_VOL_SFT 0
279
280
281 #define RT5645_DAC_L2_VOL_MASK (0xff << 8)
282 #define RT5645_DAC_L2_VOL_SFT 8
283 #define RT5645_DAC_R2_VOL_MASK (0xff)
284 #define RT5645_DAC_R2_VOL_SFT 0
285
286
287 #define RT5645_M_DAC_L2_VOL (0x1 << 13)
288 #define RT5645_M_DAC_L2_VOL_SFT 13
289 #define RT5645_M_DAC_R2_VOL (0x1 << 12)
290 #define RT5645_M_DAC_R2_VOL_SFT 12
291 #define RT5645_DAC2_L_SEL_MASK (0x7 << 4)
292 #define RT5645_DAC2_L_SEL_SFT 4
293 #define RT5645_DAC2_R_SEL_MASK (0x7 << 0)
294 #define RT5645_DAC2_R_SEL_SFT 0
295
296
297 #define RT5645_ADC_L_VOL_MASK (0x7f << 8)
298 #define RT5645_ADC_L_VOL_SFT 8
299 #define RT5645_ADC_R_VOL_MASK (0x7f)
300 #define RT5645_ADC_R_VOL_SFT 0
301
302
303 #define RT5645_MONO_ADC_L_VOL_MASK (0x7f << 8)
304 #define RT5645_MONO_ADC_L_VOL_SFT 8
305 #define RT5645_MONO_ADC_R_VOL_MASK (0x7f)
306 #define RT5645_MONO_ADC_R_VOL_SFT 0
307
308
309 #define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14)
310 #define RT5645_STO1_ADC_L_BST_SFT 14
311 #define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12)
312 #define RT5645_STO1_ADC_R_BST_SFT 12
313 #define RT5645_STO1_ADC_COMP_MASK (0x3 << 10)
314 #define RT5645_STO1_ADC_COMP_SFT 10
315
316
317 #define RT5645_MONO_ADC_L_BST_MASK (0x3 << 14)
318 #define RT5645_MONO_ADC_L_BST_SFT 14
319 #define RT5645_MONO_ADC_R_BST_MASK (0x3 << 12)
320 #define RT5645_MONO_ADC_R_BST_SFT 12
321 #define RT5645_MONO_ADC_COMP_MASK (0x3 << 10)
322 #define RT5645_MONO_ADC_COMP_SFT 10
323
324
325 #define RT5645_STO2_ADC_SRC_MASK (0x1 << 15)
326 #define RT5645_STO2_ADC_SRC_SFT 15
327
328
329 #define RT5645_M_ADC_L1 (0x1 << 14)
330 #define RT5645_M_ADC_L1_SFT 14
331 #define RT5645_M_ADC_L2 (0x1 << 13)
332 #define RT5645_M_ADC_L2_SFT 13
333 #define RT5645_ADC_1_SRC_MASK (0x1 << 12)
334 #define RT5645_ADC_1_SRC_SFT 12
335 #define RT5645_ADC_1_SRC_ADC (0x1 << 12)
336 #define RT5645_ADC_1_SRC_DACMIX (0x0 << 12)
337 #define RT5645_ADC_2_SRC_MASK (0x1 << 11)
338 #define RT5645_ADC_2_SRC_SFT 11
339 #define RT5645_DMIC_SRC_MASK (0x1 << 8)
340 #define RT5645_DMIC_SRC_SFT 8
341 #define RT5645_M_ADC_R1 (0x1 << 6)
342 #define RT5645_M_ADC_R1_SFT 6
343 #define RT5645_M_ADC_R2 (0x1 << 5)
344 #define RT5645_M_ADC_R2_SFT 5
345 #define RT5645_DMIC3_SRC_MASK (0x1 << 1)
346 #define RT5645_DMIC3_SRC_SFT 0
347
348
349 #define RT5645_M_MONO_ADC_L1 (0x1 << 14)
350 #define RT5645_M_MONO_ADC_L1_SFT 14
351 #define RT5645_M_MONO_ADC_L2 (0x1 << 13)
352 #define RT5645_M_MONO_ADC_L2_SFT 13
353 #define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12)
354 #define RT5645_MONO_ADC_L1_SRC_SFT 12
355 #define RT5645_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
356 #define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
357 #define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11)
358 #define RT5645_MONO_ADC_L2_SRC_SFT 11
359 #define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8)
360 #define RT5645_MONO_DMIC_L_SRC_SFT 8
361 #define RT5645_M_MONO_ADC_R1 (0x1 << 6)
362 #define RT5645_M_MONO_ADC_R1_SFT 6
363 #define RT5645_M_MONO_ADC_R2 (0x1 << 5)
364 #define RT5645_M_MONO_ADC_R2_SFT 5
365 #define RT5645_MONO_ADC_R1_SRC_MASK (0x1 << 4)
366 #define RT5645_MONO_ADC_R1_SRC_SFT 4
367 #define RT5645_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
368 #define RT5645_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
369 #define RT5645_MONO_ADC_R2_SRC_MASK (0x1 << 3)
370 #define RT5645_MONO_ADC_R2_SRC_SFT 3
371 #define RT5645_MONO_DMIC_R_SRC_MASK (0x3)
372 #define RT5645_MONO_DMIC_R_SRC_SFT 0
373
374
375 #define RT5645_M_ADCMIX_L (0x1 << 15)
376 #define RT5645_M_ADCMIX_L_SFT 15
377 #define RT5645_M_DAC1_L (0x1 << 14)
378 #define RT5645_M_DAC1_L_SFT 14
379 #define RT5645_DAC1_R_SEL_MASK (0x3 << 10)
380 #define RT5645_DAC1_R_SEL_SFT 10
381 #define RT5645_DAC1_R_SEL_IF1 (0x0 << 10)
382 #define RT5645_DAC1_R_SEL_IF2 (0x1 << 10)
383 #define RT5645_DAC1_R_SEL_IF3 (0x2 << 10)
384 #define RT5645_DAC1_R_SEL_IF4 (0x3 << 10)
385 #define RT5645_DAC1_L_SEL_MASK (0x3 << 8)
386 #define RT5645_DAC1_L_SEL_SFT 8
387 #define RT5645_DAC1_L_SEL_IF1 (0x0 << 8)
388 #define RT5645_DAC1_L_SEL_IF2 (0x1 << 8)
389 #define RT5645_DAC1_L_SEL_IF3 (0x2 << 8)
390 #define RT5645_DAC1_L_SEL_IF4 (0x3 << 8)
391 #define RT5645_M_ADCMIX_R (0x1 << 7)
392 #define RT5645_M_ADCMIX_R_SFT 7
393 #define RT5645_M_DAC1_R (0x1 << 6)
394 #define RT5645_M_DAC1_R_SFT 6
395
396
397 #define RT5645_M_DAC_L1 (0x1 << 14)
398 #define RT5645_M_DAC_L1_SFT 14
399 #define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
400 #define RT5645_DAC_L1_STO_L_VOL_SFT 13
401 #define RT5645_M_DAC_L2 (0x1 << 12)
402 #define RT5645_M_DAC_L2_SFT 12
403 #define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
404 #define RT5645_DAC_L2_STO_L_VOL_SFT 11
405 #define RT5645_M_ANC_DAC_L (0x1 << 10)
406 #define RT5645_M_ANC_DAC_L_SFT 10
407 #define RT5645_M_DAC_R1_STO_L (0x1 << 9)
408 #define RT5645_M_DAC_R1_STO_L_SFT 9
409 #define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
410 #define RT5645_DAC_R1_STO_L_VOL_SFT 8
411 #define RT5645_M_DAC_R1 (0x1 << 6)
412 #define RT5645_M_DAC_R1_SFT 6
413 #define RT5645_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
414 #define RT5645_DAC_R1_STO_R_VOL_SFT 5
415 #define RT5645_M_DAC_R2 (0x1 << 4)
416 #define RT5645_M_DAC_R2_SFT 4
417 #define RT5645_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
418 #define RT5645_DAC_R2_STO_R_VOL_SFT 3
419 #define RT5645_M_ANC_DAC_R (0x1 << 2)
420 #define RT5645_M_ANC_DAC_R_SFT 2
421 #define RT5645_M_DAC_L1_STO_R (0x1 << 1)
422 #define RT5645_M_DAC_L1_STO_R_SFT 1
423 #define RT5645_DAC_L1_STO_R_VOL_MASK (0x1)
424 #define RT5645_DAC_L1_STO_R_VOL_SFT 0
425
426
427 #define RT5645_M_DAC_L1_MONO_L (0x1 << 14)
428 #define RT5645_M_DAC_L1_MONO_L_SFT 14
429 #define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
430 #define RT5645_DAC_L1_MONO_L_VOL_SFT 13
431 #define RT5645_M_DAC_L2_MONO_L (0x1 << 12)
432 #define RT5645_M_DAC_L2_MONO_L_SFT 12
433 #define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
434 #define RT5645_DAC_L2_MONO_L_VOL_SFT 11
435 #define RT5645_M_DAC_R2_MONO_L (0x1 << 10)
436 #define RT5645_M_DAC_R2_MONO_L_SFT 10
437 #define RT5645_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
438 #define RT5645_DAC_R2_MONO_L_VOL_SFT 9
439 #define RT5645_M_DAC_R1_MONO_R (0x1 << 6)
440 #define RT5645_M_DAC_R1_MONO_R_SFT 6
441 #define RT5645_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
442 #define RT5645_DAC_R1_MONO_R_VOL_SFT 5
443 #define RT5645_M_DAC_R2_MONO_R (0x1 << 4)
444 #define RT5645_M_DAC_R2_MONO_R_SFT 4
445 #define RT5645_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
446 #define RT5645_DAC_R2_MONO_R_VOL_SFT 3
447 #define RT5645_M_DAC_L2_MONO_R (0x1 << 2)
448 #define RT5645_M_DAC_L2_MONO_R_SFT 2
449 #define RT5645_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
450 #define RT5645_DAC_L2_MONO_R_VOL_SFT 1
451
452
453 #define RT5645_M_STO_L_DAC_L (0x1 << 15)
454 #define RT5645_M_STO_L_DAC_L_SFT 15
455 #define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14)
456 #define RT5645_STO_L_DAC_L_VOL_SFT 14
457 #define RT5645_M_DAC_L2_DAC_L (0x1 << 13)
458 #define RT5645_M_DAC_L2_DAC_L_SFT 13
459 #define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
460 #define RT5645_DAC_L2_DAC_L_VOL_SFT 12
461 #define RT5645_M_STO_R_DAC_R (0x1 << 11)
462 #define RT5645_M_STO_R_DAC_R_SFT 11
463 #define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10)
464 #define RT5645_STO_R_DAC_R_VOL_SFT 10
465 #define RT5645_M_DAC_R2_DAC_R (0x1 << 9)
466 #define RT5645_M_DAC_R2_DAC_R_SFT 9
467 #define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
468 #define RT5645_DAC_R2_DAC_R_VOL_SFT 8
469 #define RT5645_M_DAC_R2_DAC_L (0x1 << 7)
470 #define RT5645_M_DAC_R2_DAC_L_SFT 7
471 #define RT5645_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
472 #define RT5645_DAC_R2_DAC_L_VOL_SFT 6
473 #define RT5645_M_DAC_L2_DAC_R (0x1 << 5)
474 #define RT5645_M_DAC_L2_DAC_R_SFT 5
475 #define RT5645_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
476 #define RT5645_DAC_L2_DAC_R_VOL_SFT 4
477
478
479 #define RT5650_A_DAC1_L_IN_SFT 3
480 #define RT5650_A_DAC1_R_IN_SFT 2
481 #define RT5650_A_DAC2_L_IN_SFT 1
482 #define RT5650_A_DAC2_R_IN_SFT 0
483
484
485 #define RT5645_IF1_ADC2_IN_SEL (0x1 << 15)
486 #define RT5645_IF1_ADC2_IN_SFT 15
487 #define RT5645_IF2_ADC_IN_MASK (0x7 << 12)
488 #define RT5645_IF2_ADC_IN_SFT 12
489 #define RT5645_IF2_DAC_SEL_MASK (0x3 << 10)
490 #define RT5645_IF2_DAC_SEL_SFT 10
491 #define RT5645_IF2_ADC_SEL_MASK (0x3 << 8)
492 #define RT5645_IF2_ADC_SEL_SFT 8
493 #define RT5645_IF3_DAC_SEL_MASK (0x3 << 6)
494 #define RT5645_IF3_DAC_SEL_SFT 6
495 #define RT5645_IF3_ADC_SEL_MASK (0x3 << 4)
496 #define RT5645_IF3_ADC_SEL_SFT 4
497 #define RT5645_IF3_ADC_IN_MASK (0x7)
498 #define RT5645_IF3_ADC_IN_SFT 0
499
500
501 #define RT5645_PDM1_L_MASK (0x1 << 15)
502 #define RT5645_PDM1_L_SFT 15
503 #define RT5645_M_PDM1_L (0x1 << 14)
504 #define RT5645_M_PDM1_L_SFT 14
505 #define RT5645_PDM1_R_MASK (0x1 << 13)
506 #define RT5645_PDM1_R_SFT 13
507 #define RT5645_M_PDM1_R (0x1 << 12)
508 #define RT5645_M_PDM1_R_SFT 12
509 #define RT5645_PDM2_L_MASK (0x1 << 11)
510 #define RT5645_PDM2_L_SFT 11
511 #define RT5645_M_PDM2_L (0x1 << 10)
512 #define RT5645_M_PDM2_L_SFT 10
513 #define RT5645_PDM2_R_MASK (0x1 << 9)
514 #define RT5645_PDM2_R_SFT 9
515 #define RT5645_M_PDM2_R (0x1 << 8)
516 #define RT5645_M_PDM2_R_SFT 8
517 #define RT5645_PDM2_BUSY (0x1 << 7)
518 #define RT5645_PDM1_BUSY (0x1 << 6)
519 #define RT5645_PDM_PATTERN (0x1 << 5)
520 #define RT5645_PDM_GAIN (0x1 << 4)
521 #define RT5645_PDM_DIV_MASK (0x3)
522
523
524 #define RT5645_G_HP_L_RM_L_MASK (0x7 << 13)
525 #define RT5645_G_HP_L_RM_L_SFT 13
526 #define RT5645_G_IN_L_RM_L_MASK (0x7 << 10)
527 #define RT5645_G_IN_L_RM_L_SFT 10
528 #define RT5645_G_BST4_RM_L_MASK (0x7 << 7)
529 #define RT5645_G_BST4_RM_L_SFT 7
530 #define RT5645_G_BST3_RM_L_MASK (0x7 << 4)
531 #define RT5645_G_BST3_RM_L_SFT 4
532 #define RT5645_G_BST2_RM_L_MASK (0x7 << 1)
533 #define RT5645_G_BST2_RM_L_SFT 1
534
535
536 #define RT5645_G_BST1_RM_L_MASK (0x7 << 13)
537 #define RT5645_G_BST1_RM_L_SFT 13
538 #define RT5645_G_OM_L_RM_L_MASK (0x7 << 10)
539 #define RT5645_G_OM_L_RM_L_SFT 10
540 #define RT5645_M_MM_L_RM_L (0x1 << 6)
541 #define RT5645_M_MM_L_RM_L_SFT 6
542 #define RT5645_M_IN_L_RM_L (0x1 << 5)
543 #define RT5645_M_IN_L_RM_L_SFT 5
544 #define RT5645_M_HP_L_RM_L (0x1 << 4)
545 #define RT5645_M_HP_L_RM_L_SFT 4
546 #define RT5645_M_BST3_RM_L (0x1 << 3)
547 #define RT5645_M_BST3_RM_L_SFT 3
548 #define RT5645_M_BST2_RM_L (0x1 << 2)
549 #define RT5645_M_BST2_RM_L_SFT 2
550 #define RT5645_M_BST1_RM_L (0x1 << 1)
551 #define RT5645_M_BST1_RM_L_SFT 1
552 #define RT5645_M_OM_L_RM_L (0x1)
553 #define RT5645_M_OM_L_RM_L_SFT 0
554
555
556 #define RT5645_G_HP_R_RM_R_MASK (0x7 << 13)
557 #define RT5645_G_HP_R_RM_R_SFT 13
558 #define RT5645_G_IN_R_RM_R_MASK (0x7 << 10)
559 #define RT5645_G_IN_R_RM_R_SFT 10
560 #define RT5645_G_BST4_RM_R_MASK (0x7 << 7)
561 #define RT5645_G_BST4_RM_R_SFT 7
562 #define RT5645_G_BST3_RM_R_MASK (0x7 << 4)
563 #define RT5645_G_BST3_RM_R_SFT 4
564 #define RT5645_G_BST2_RM_R_MASK (0x7 << 1)
565 #define RT5645_G_BST2_RM_R_SFT 1
566
567
568 #define RT5645_G_BST1_RM_R_MASK (0x7 << 13)
569 #define RT5645_G_BST1_RM_R_SFT 13
570 #define RT5645_G_OM_R_RM_R_MASK (0x7 << 10)
571 #define RT5645_G_OM_R_RM_R_SFT 10
572 #define RT5645_M_MM_R_RM_R (0x1 << 6)
573 #define RT5645_M_MM_R_RM_R_SFT 6
574 #define RT5645_M_IN_R_RM_R (0x1 << 5)
575 #define RT5645_M_IN_R_RM_R_SFT 5
576 #define RT5645_M_HP_R_RM_R (0x1 << 4)
577 #define RT5645_M_HP_R_RM_R_SFT 4
578 #define RT5645_M_BST3_RM_R (0x1 << 3)
579 #define RT5645_M_BST3_RM_R_SFT 3
580 #define RT5645_M_BST2_RM_R (0x1 << 2)
581 #define RT5645_M_BST2_RM_R_SFT 2
582 #define RT5645_M_BST1_RM_R (0x1 << 1)
583 #define RT5645_M_BST1_RM_R_SFT 1
584 #define RT5645_M_OM_R_RM_R (0x1)
585 #define RT5645_M_OM_R_RM_R_SFT 0
586
587
588 #define RT5645_M_BST1_HV (0x1 << 4)
589 #define RT5645_M_BST1_HV_SFT 4
590 #define RT5645_M_BST2_HV (0x1 << 4)
591 #define RT5645_M_BST2_HV_SFT 4
592 #define RT5645_M_BST3_HV (0x1 << 3)
593 #define RT5645_M_BST3_HV_SFT 3
594 #define RT5645_M_IN_HV (0x1 << 2)
595 #define RT5645_M_IN_HV_SFT 2
596 #define RT5645_M_DAC2_HV (0x1 << 1)
597 #define RT5645_M_DAC2_HV_SFT 1
598 #define RT5645_M_DAC1_HV (0x1 << 0)
599 #define RT5645_M_DAC1_HV_SFT 0
600
601
602 #define RT5645_M_DAC1_HM (0x1 << 14)
603 #define RT5645_M_DAC1_HM_SFT 14
604 #define RT5645_M_HPVOL_HM (0x1 << 13)
605 #define RT5645_M_HPVOL_HM_SFT 13
606 #define RT5645_IRQ_PSV_MODE (0x1 << 12)
607
608
609 #define RT5645_G_RM_L_SM_L_MASK (0x3 << 14)
610 #define RT5645_G_RM_L_SM_L_SFT 14
611 #define RT5645_G_IN_L_SM_L_MASK (0x3 << 12)
612 #define RT5645_G_IN_L_SM_L_SFT 12
613 #define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10)
614 #define RT5645_G_DAC_L1_SM_L_SFT 10
615 #define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8)
616 #define RT5645_G_DAC_L2_SM_L_SFT 8
617 #define RT5645_G_OM_L_SM_L_MASK (0x3 << 6)
618 #define RT5645_G_OM_L_SM_L_SFT 6
619 #define RT5645_M_BST1_L_SM_L (0x1 << 5)
620 #define RT5645_M_BST1_L_SM_L_SFT 5
621 #define RT5645_M_BST3_L_SM_L (0x1 << 4)
622 #define RT5645_M_BST3_L_SM_L_SFT 4
623 #define RT5645_M_IN_L_SM_L (0x1 << 3)
624 #define RT5645_M_IN_L_SM_L_SFT 3
625 #define RT5645_M_DAC_L2_SM_L (0x1 << 2)
626 #define RT5645_M_DAC_L2_SM_L_SFT 2
627 #define RT5645_M_DAC_L1_SM_L (0x1 << 1)
628 #define RT5645_M_DAC_L1_SM_L_SFT 1
629
630
631 #define RT5645_G_RM_R_SM_R_MASK (0x3 << 14)
632 #define RT5645_G_RM_R_SM_R_SFT 14
633 #define RT5645_G_IN_R_SM_R_MASK (0x3 << 12)
634 #define RT5645_G_IN_R_SM_R_SFT 12
635 #define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10)
636 #define RT5645_G_DAC_R1_SM_R_SFT 10
637 #define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8)
638 #define RT5645_G_DAC_R2_SM_R_SFT 8
639 #define RT5645_G_OM_R_SM_R_MASK (0x3 << 6)
640 #define RT5645_G_OM_R_SM_R_SFT 6
641 #define RT5645_M_BST2_R_SM_R (0x1 << 5)
642 #define RT5645_M_BST2_R_SM_R_SFT 5
643 #define RT5645_M_BST3_R_SM_R (0x1 << 4)
644 #define RT5645_M_BST3_R_SM_R_SFT 4
645 #define RT5645_M_IN_R_SM_R (0x1 << 3)
646 #define RT5645_M_IN_R_SM_R_SFT 3
647 #define RT5645_M_DAC_R2_SM_R (0x1 << 2)
648 #define RT5645_M_DAC_R2_SM_R_SFT 2
649 #define RT5645_M_DAC_R1_SM_R (0x1 << 1)
650 #define RT5645_M_DAC_R1_SM_R_SFT 1
651
652
653 #define RT5645_M_DAC_L1_SPM_L (0x1 << 15)
654 #define RT5645_M_DAC_L1_SPM_L_SFT 15
655 #define RT5645_M_DAC_R1_SPM_L (0x1 << 14)
656 #define RT5645_M_DAC_R1_SPM_L_SFT 14
657 #define RT5645_M_SV_L_SPM_L (0x1 << 13)
658 #define RT5645_M_SV_L_SPM_L_SFT 13
659 #define RT5645_M_SV_R_SPM_L (0x1 << 12)
660 #define RT5645_M_SV_R_SPM_L_SFT 12
661 #define RT5645_M_BST3_SPM_L (0x1 << 11)
662 #define RT5645_M_BST3_SPM_L_SFT 11
663 #define RT5645_M_DAC_R1_SPM_R (0x1 << 2)
664 #define RT5645_M_DAC_R1_SPM_R_SFT 2
665 #define RT5645_M_BST3_SPM_R (0x1 << 1)
666 #define RT5645_M_BST3_SPM_R_SFT 1
667 #define RT5645_M_SV_R_SPM_R (0x1 << 0)
668 #define RT5645_M_SV_R_SPM_R_SFT 0
669
670
671 #define RT5645_SPK_G_CLSD_MASK (0x7 << 0)
672 #define RT5645_SPK_G_CLSD_SFT 0
673
674
675 #define RT5645_G_MONOMIX_MASK (0x1 << 10)
676 #define RT5645_G_MONOMIX_SFT 10
677 #define RT5645_M_OV_L_MM (0x1 << 9)
678 #define RT5645_M_OV_L_MM_SFT 9
679 #define RT5645_M_DAC_L2_MA (0x1 << 8)
680 #define RT5645_M_DAC_L2_MA_SFT 8
681 #define RT5645_M_BST2_MM (0x1 << 4)
682 #define RT5645_M_BST2_MM_SFT 4
683 #define RT5645_M_DAC_R1_MM (0x1 << 3)
684 #define RT5645_M_DAC_R1_MM_SFT 3
685 #define RT5645_M_DAC_R2_MM (0x1 << 2)
686 #define RT5645_M_DAC_R2_MM_SFT 2
687 #define RT5645_M_DAC_L2_MM (0x1 << 1)
688 #define RT5645_M_DAC_L2_MM_SFT 1
689 #define RT5645_M_BST3_MM (0x1 << 0)
690 #define RT5645_M_BST3_MM_SFT 0
691
692
693 #define RT5645_G_BST3_OM_L_MASK (0x7 << 13)
694 #define RT5645_G_BST3_OM_L_SFT 13
695 #define RT5645_G_BST2_OM_L_MASK (0x7 << 10)
696 #define RT5645_G_BST2_OM_L_SFT 10
697 #define RT5645_G_BST1_OM_L_MASK (0x7 << 7)
698 #define RT5645_G_BST1_OM_L_SFT 7
699 #define RT5645_G_IN_L_OM_L_MASK (0x7 << 4)
700 #define RT5645_G_IN_L_OM_L_SFT 4
701 #define RT5645_G_RM_L_OM_L_MASK (0x7 << 1)
702 #define RT5645_G_RM_L_OM_L_SFT 1
703
704
705 #define RT5645_G_DAC_R2_OM_L_MASK (0x7 << 13)
706 #define RT5645_G_DAC_R2_OM_L_SFT 13
707 #define RT5645_G_DAC_L2_OM_L_MASK (0x7 << 10)
708 #define RT5645_G_DAC_L2_OM_L_SFT 10
709 #define RT5645_G_DAC_L1_OM_L_MASK (0x7 << 7)
710 #define RT5645_G_DAC_L1_OM_L_SFT 7
711
712
713 #define RT5645_M_BST3_OM_L (0x1 << 4)
714 #define RT5645_M_BST3_OM_L_SFT 4
715 #define RT5645_M_BST1_OM_L (0x1 << 3)
716 #define RT5645_M_BST1_OM_L_SFT 3
717 #define RT5645_M_IN_L_OM_L (0x1 << 2)
718 #define RT5645_M_IN_L_OM_L_SFT 2
719 #define RT5645_M_DAC_L2_OM_L (0x1 << 1)
720 #define RT5645_M_DAC_L2_OM_L_SFT 1
721 #define RT5645_M_DAC_L1_OM_L (0x1)
722 #define RT5645_M_DAC_L1_OM_L_SFT 0
723
724
725 #define RT5645_G_BST4_OM_R_MASK (0x7 << 13)
726 #define RT5645_G_BST4_OM_R_SFT 13
727 #define RT5645_G_BST2_OM_R_MASK (0x7 << 10)
728 #define RT5645_G_BST2_OM_R_SFT 10
729 #define RT5645_G_BST1_OM_R_MASK (0x7 << 7)
730 #define RT5645_G_BST1_OM_R_SFT 7
731 #define RT5645_G_IN_R_OM_R_MASK (0x7 << 4)
732 #define RT5645_G_IN_R_OM_R_SFT 4
733 #define RT5645_G_RM_R_OM_R_MASK (0x7 << 1)
734 #define RT5645_G_RM_R_OM_R_SFT 1
735
736
737 #define RT5645_G_DAC_L2_OM_R_MASK (0x7 << 13)
738 #define RT5645_G_DAC_L2_OM_R_SFT 13
739 #define RT5645_G_DAC_R2_OM_R_MASK (0x7 << 10)
740 #define RT5645_G_DAC_R2_OM_R_SFT 10
741 #define RT5645_G_DAC_R1_OM_R_MASK (0x7 << 7)
742 #define RT5645_G_DAC_R1_OM_R_SFT 7
743
744
745 #define RT5645_M_BST3_OM_R (0x1 << 4)
746 #define RT5645_M_BST3_OM_R_SFT 4
747 #define RT5645_M_BST2_OM_R (0x1 << 3)
748 #define RT5645_M_BST2_OM_R_SFT 3
749 #define RT5645_M_IN_R_OM_R (0x1 << 2)
750 #define RT5645_M_IN_R_OM_R_SFT 2
751 #define RT5645_M_DAC_R2_OM_R (0x1 << 1)
752 #define RT5645_M_DAC_R2_OM_R_SFT 1
753 #define RT5645_M_DAC_R1_OM_R (0x1)
754 #define RT5645_M_DAC_R1_OM_R_SFT 0
755
756
757 #define RT5645_M_DAC_L1_LM (0x1 << 15)
758 #define RT5645_M_DAC_L1_LM_SFT 15
759 #define RT5645_M_DAC_R1_LM (0x1 << 14)
760 #define RT5645_M_DAC_R1_LM_SFT 14
761 #define RT5645_M_OV_L_LM (0x1 << 13)
762 #define RT5645_M_OV_L_LM_SFT 13
763 #define RT5645_M_OV_R_LM (0x1 << 12)
764 #define RT5645_M_OV_R_LM_SFT 12
765 #define RT5645_G_LOUTMIX_MASK (0x1 << 11)
766 #define RT5645_G_LOUTMIX_SFT 11
767
768
769 #define RT5645_PWR_I2S1 (0x1 << 15)
770 #define RT5645_PWR_I2S1_BIT 15
771 #define RT5645_PWR_I2S2 (0x1 << 14)
772 #define RT5645_PWR_I2S2_BIT 14
773 #define RT5645_PWR_I2S3 (0x1 << 13)
774 #define RT5645_PWR_I2S3_BIT 13
775 #define RT5645_PWR_DAC_L1 (0x1 << 12)
776 #define RT5645_PWR_DAC_L1_BIT 12
777 #define RT5645_PWR_DAC_R1 (0x1 << 11)
778 #define RT5645_PWR_DAC_R1_BIT 11
779 #define RT5645_PWR_CLS_D_R (0x1 << 9)
780 #define RT5645_PWR_CLS_D_R_BIT 9
781 #define RT5645_PWR_CLS_D_L (0x1 << 8)
782 #define RT5645_PWR_CLS_D_L_BIT 8
783 #define RT5645_PWR_DAC_L2 (0x1 << 7)
784 #define RT5645_PWR_DAC_L2_BIT 7
785 #define RT5645_PWR_DAC_R2 (0x1 << 6)
786 #define RT5645_PWR_DAC_R2_BIT 6
787 #define RT5645_PWR_ADC_L (0x1 << 2)
788 #define RT5645_PWR_ADC_L_BIT 2
789 #define RT5645_PWR_ADC_R (0x1 << 1)
790 #define RT5645_PWR_ADC_R_BIT 1
791 #define RT5645_PWR_CLS_D (0x1)
792 #define RT5645_PWR_CLS_D_BIT 0
793
794
795 #define RT5645_PWR_ADC_S1F (0x1 << 15)
796 #define RT5645_PWR_ADC_S1F_BIT 15
797 #define RT5645_PWR_ADC_MF_L (0x1 << 14)
798 #define RT5645_PWR_ADC_MF_L_BIT 14
799 #define RT5645_PWR_ADC_MF_R (0x1 << 13)
800 #define RT5645_PWR_ADC_MF_R_BIT 13
801 #define RT5645_PWR_I2S_DSP (0x1 << 12)
802 #define RT5645_PWR_I2S_DSP_BIT 12
803 #define RT5645_PWR_DAC_S1F (0x1 << 11)
804 #define RT5645_PWR_DAC_S1F_BIT 11
805 #define RT5645_PWR_DAC_MF_L (0x1 << 10)
806 #define RT5645_PWR_DAC_MF_L_BIT 10
807 #define RT5645_PWR_DAC_MF_R (0x1 << 9)
808 #define RT5645_PWR_DAC_MF_R_BIT 9
809 #define RT5645_PWR_PDM1 (0x1 << 7)
810 #define RT5645_PWR_PDM1_BIT 7
811 #define RT5645_PWR_PDM2 (0x1 << 6)
812 #define RT5645_PWR_PDM2_BIT 6
813 #define RT5645_PWR_IPTV (0x1 << 1)
814 #define RT5645_PWR_IPTV_BIT 1
815 #define RT5645_PWR_PAD (0x1)
816 #define RT5645_PWR_PAD_BIT 0
817
818
819 #define RT5645_PWR_VREF1 (0x1 << 15)
820 #define RT5645_PWR_VREF1_BIT 15
821 #define RT5645_PWR_FV1 (0x1 << 14)
822 #define RT5645_PWR_FV1_BIT 14
823 #define RT5645_PWR_MB (0x1 << 13)
824 #define RT5645_PWR_MB_BIT 13
825 #define RT5645_PWR_LM (0x1 << 12)
826 #define RT5645_PWR_LM_BIT 12
827 #define RT5645_PWR_BG (0x1 << 11)
828 #define RT5645_PWR_BG_BIT 11
829 #define RT5645_PWR_MA (0x1 << 10)
830 #define RT5645_PWR_MA_BIT 10
831 #define RT5645_PWR_HP_L (0x1 << 7)
832 #define RT5645_PWR_HP_L_BIT 7
833 #define RT5645_PWR_HP_R (0x1 << 6)
834 #define RT5645_PWR_HP_R_BIT 6
835 #define RT5645_PWR_HA (0x1 << 5)
836 #define RT5645_PWR_HA_BIT 5
837 #define RT5645_PWR_VREF2 (0x1 << 4)
838 #define RT5645_PWR_VREF2_BIT 4
839 #define RT5645_PWR_FV2 (0x1 << 3)
840 #define RT5645_PWR_FV2_BIT 3
841 #define RT5645_LDO_SEL_MASK (0x3)
842 #define RT5645_LDO_SEL_SFT 0
843
844
845 #define RT5645_PWR_BST1 (0x1 << 15)
846 #define RT5645_PWR_BST1_BIT 15
847 #define RT5645_PWR_BST2 (0x1 << 14)
848 #define RT5645_PWR_BST2_BIT 14
849 #define RT5645_PWR_BST3 (0x1 << 13)
850 #define RT5645_PWR_BST3_BIT 13
851 #define RT5645_PWR_BST4 (0x1 << 12)
852 #define RT5645_PWR_BST4_BIT 12
853 #define RT5645_PWR_MB1 (0x1 << 11)
854 #define RT5645_PWR_MB1_BIT 11
855 #define RT5645_PWR_MB2 (0x1 << 10)
856 #define RT5645_PWR_MB2_BIT 10
857 #define RT5645_PWR_PLL (0x1 << 9)
858 #define RT5645_PWR_PLL_BIT 9
859 #define RT5645_PWR_BST2_P (0x1 << 5)
860 #define RT5645_PWR_BST2_P_BIT 5
861 #define RT5645_PWR_BST3_P (0x1 << 4)
862 #define RT5645_PWR_BST3_P_BIT 4
863 #define RT5645_PWR_BST4_P (0x1 << 3)
864 #define RT5645_PWR_BST4_P_BIT 3
865 #define RT5645_PWR_JD1 (0x1 << 2)
866 #define RT5645_PWR_JD1_BIT 2
867 #define RT5645_PWR_JD (0x1 << 1)
868 #define RT5645_PWR_JD_BIT 1
869
870
871 #define RT5645_PWR_OM_L (0x1 << 15)
872 #define RT5645_PWR_OM_L_BIT 15
873 #define RT5645_PWR_OM_R (0x1 << 14)
874 #define RT5645_PWR_OM_R_BIT 14
875 #define RT5645_PWR_SM_L (0x1 << 13)
876 #define RT5645_PWR_SM_L_BIT 13
877 #define RT5645_PWR_SM_R (0x1 << 12)
878 #define RT5645_PWR_SM_R_BIT 12
879 #define RT5645_PWR_RM_L (0x1 << 11)
880 #define RT5645_PWR_RM_L_BIT 11
881 #define RT5645_PWR_RM_R (0x1 << 10)
882 #define RT5645_PWR_RM_R_BIT 10
883 #define RT5645_PWR_MM (0x1 << 8)
884 #define RT5645_PWR_MM_BIT 8
885 #define RT5645_PWR_HM_L (0x1 << 7)
886 #define RT5645_PWR_HM_L_BIT 7
887 #define RT5645_PWR_HM_R (0x1 << 6)
888 #define RT5645_PWR_HM_R_BIT 6
889 #define RT5645_PWR_LDO2 (0x1 << 1)
890 #define RT5645_PWR_LDO2_BIT 1
891
892
893 #define RT5645_PWR_SV_L (0x1 << 15)
894 #define RT5645_PWR_SV_L_BIT 15
895 #define RT5645_PWR_SV_R (0x1 << 14)
896 #define RT5645_PWR_SV_R_BIT 14
897 #define RT5645_PWR_HV_L (0x1 << 11)
898 #define RT5645_PWR_HV_L_BIT 11
899 #define RT5645_PWR_HV_R (0x1 << 10)
900 #define RT5645_PWR_HV_R_BIT 10
901 #define RT5645_PWR_IN_L (0x1 << 9)
902 #define RT5645_PWR_IN_L_BIT 9
903 #define RT5645_PWR_IN_R (0x1 << 8)
904 #define RT5645_PWR_IN_R_BIT 8
905 #define RT5645_PWR_MIC_DET (0x1 << 5)
906 #define RT5645_PWR_MIC_DET_BIT 5
907
908
909 #define RT5645_I2S_MS_MASK (0x1 << 15)
910 #define RT5645_I2S_MS_SFT 15
911 #define RT5645_I2S_MS_M (0x0 << 15)
912 #define RT5645_I2S_MS_S (0x1 << 15)
913 #define RT5645_I2S_O_CP_MASK (0x3 << 10)
914 #define RT5645_I2S_O_CP_SFT 10
915 #define RT5645_I2S_O_CP_OFF (0x0 << 10)
916 #define RT5645_I2S_O_CP_U_LAW (0x1 << 10)
917 #define RT5645_I2S_O_CP_A_LAW (0x2 << 10)
918 #define RT5645_I2S_I_CP_MASK (0x3 << 8)
919 #define RT5645_I2S_I_CP_SFT 8
920 #define RT5645_I2S_I_CP_OFF (0x0 << 8)
921 #define RT5645_I2S_I_CP_U_LAW (0x1 << 8)
922 #define RT5645_I2S_I_CP_A_LAW (0x2 << 8)
923 #define RT5645_I2S_BP_MASK (0x1 << 7)
924 #define RT5645_I2S_BP_SFT 7
925 #define RT5645_I2S_BP_NOR (0x0 << 7)
926 #define RT5645_I2S_BP_INV (0x1 << 7)
927 #define RT5645_I2S_DL_MASK (0x3 << 2)
928 #define RT5645_I2S_DL_SFT 2
929 #define RT5645_I2S_DL_16 (0x0 << 2)
930 #define RT5645_I2S_DL_20 (0x1 << 2)
931 #define RT5645_I2S_DL_24 (0x2 << 2)
932 #define RT5645_I2S_DL_8 (0x3 << 2)
933 #define RT5645_I2S_DF_MASK (0x3)
934 #define RT5645_I2S_DF_SFT 0
935 #define RT5645_I2S_DF_I2S (0x0)
936 #define RT5645_I2S_DF_LEFT (0x1)
937 #define RT5645_I2S_DF_PCM_A (0x2)
938 #define RT5645_I2S_DF_PCM_B (0x3)
939
940
941 #define RT5645_I2S2_SDI_MASK (0x1 << 6)
942 #define RT5645_I2S2_SDI_SFT 6
943 #define RT5645_I2S2_SDI_I2S1 (0x0 << 6)
944 #define RT5645_I2S2_SDI_I2S2 (0x1 << 6)
945
946
947 #define RT5645_I2S_PD1_MASK (0x7 << 12)
948 #define RT5645_I2S_PD1_SFT 12
949 #define RT5645_I2S_PD1_1 (0x0 << 12)
950 #define RT5645_I2S_PD1_2 (0x1 << 12)
951 #define RT5645_I2S_PD1_3 (0x2 << 12)
952 #define RT5645_I2S_PD1_4 (0x3 << 12)
953 #define RT5645_I2S_PD1_6 (0x4 << 12)
954 #define RT5645_I2S_PD1_8 (0x5 << 12)
955 #define RT5645_I2S_PD1_12 (0x6 << 12)
956 #define RT5645_I2S_PD1_16 (0x7 << 12)
957 #define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11)
958 #define RT5645_I2S_BCLK_MS2_SFT 11
959 #define RT5645_I2S_BCLK_MS2_32 (0x0 << 11)
960 #define RT5645_I2S_BCLK_MS2_64 (0x1 << 11)
961 #define RT5645_I2S_PD2_MASK (0x7 << 8)
962 #define RT5645_I2S_PD2_SFT 8
963 #define RT5645_I2S_PD2_1 (0x0 << 8)
964 #define RT5645_I2S_PD2_2 (0x1 << 8)
965 #define RT5645_I2S_PD2_3 (0x2 << 8)
966 #define RT5645_I2S_PD2_4 (0x3 << 8)
967 #define RT5645_I2S_PD2_6 (0x4 << 8)
968 #define RT5645_I2S_PD2_8 (0x5 << 8)
969 #define RT5645_I2S_PD2_12 (0x6 << 8)
970 #define RT5645_I2S_PD2_16 (0x7 << 8)
971 #define RT5645_I2S_BCLK_MS3_MASK (0x1 << 7)
972 #define RT5645_I2S_BCLK_MS3_SFT 7
973 #define RT5645_I2S_BCLK_MS3_32 (0x0 << 7)
974 #define RT5645_I2S_BCLK_MS3_64 (0x1 << 7)
975 #define RT5645_I2S_PD3_MASK (0x7 << 4)
976 #define RT5645_I2S_PD3_SFT 4
977 #define RT5645_I2S_PD3_1 (0x0 << 4)
978 #define RT5645_I2S_PD3_2 (0x1 << 4)
979 #define RT5645_I2S_PD3_3 (0x2 << 4)
980 #define RT5645_I2S_PD3_4 (0x3 << 4)
981 #define RT5645_I2S_PD3_6 (0x4 << 4)
982 #define RT5645_I2S_PD3_8 (0x5 << 4)
983 #define RT5645_I2S_PD3_12 (0x6 << 4)
984 #define RT5645_I2S_PD3_16 (0x7 << 4)
985 #define RT5645_DAC_OSR_MASK (0x3 << 2)
986 #define RT5645_DAC_OSR_SFT 2
987 #define RT5645_DAC_OSR_128 (0x0 << 2)
988 #define RT5645_DAC_OSR_64 (0x1 << 2)
989 #define RT5645_DAC_OSR_32 (0x2 << 2)
990 #define RT5645_DAC_OSR_16 (0x3 << 2)
991 #define RT5645_ADC_OSR_MASK (0x3)
992 #define RT5645_ADC_OSR_SFT 0
993 #define RT5645_ADC_OSR_128 (0x0)
994 #define RT5645_ADC_OSR_64 (0x1)
995 #define RT5645_ADC_OSR_32 (0x2)
996 #define RT5645_ADC_OSR_16 (0x3)
997
998
999 #define RT5645_DAC_L_OSR_MASK (0x3 << 14)
1000 #define RT5645_DAC_L_OSR_SFT 14
1001 #define RT5645_DAC_L_OSR_128 (0x0 << 14)
1002 #define RT5645_DAC_L_OSR_64 (0x1 << 14)
1003 #define RT5645_DAC_L_OSR_32 (0x2 << 14)
1004 #define RT5645_DAC_L_OSR_16 (0x3 << 14)
1005 #define RT5645_ADC_R_OSR_MASK (0x3 << 12)
1006 #define RT5645_ADC_R_OSR_SFT 12
1007 #define RT5645_ADC_R_OSR_128 (0x0 << 12)
1008 #define RT5645_ADC_R_OSR_64 (0x1 << 12)
1009 #define RT5645_ADC_R_OSR_32 (0x2 << 12)
1010 #define RT5645_ADC_R_OSR_16 (0x3 << 12)
1011 #define RT5645_DAHPF_EN (0x1 << 11)
1012 #define RT5645_DAHPF_EN_SFT 11
1013 #define RT5645_ADHPF_EN (0x1 << 10)
1014 #define RT5645_ADHPF_EN_SFT 10
1015
1016
1017 #define RT5645_DMIC_1_EN_MASK (0x1 << 15)
1018 #define RT5645_DMIC_1_EN_SFT 15
1019 #define RT5645_DMIC_1_DIS (0x0 << 15)
1020 #define RT5645_DMIC_1_EN (0x1 << 15)
1021 #define RT5645_DMIC_2_EN_MASK (0x1 << 14)
1022 #define RT5645_DMIC_2_EN_SFT 14
1023 #define RT5645_DMIC_2_DIS (0x0 << 14)
1024 #define RT5645_DMIC_2_EN (0x1 << 14)
1025 #define RT5645_DMIC_1L_LH_MASK (0x1 << 13)
1026 #define RT5645_DMIC_1L_LH_SFT 13
1027 #define RT5645_DMIC_1L_LH_FALLING (0x0 << 13)
1028 #define RT5645_DMIC_1L_LH_RISING (0x1 << 13)
1029 #define RT5645_DMIC_1R_LH_MASK (0x1 << 12)
1030 #define RT5645_DMIC_1R_LH_SFT 12
1031 #define RT5645_DMIC_1R_LH_FALLING (0x0 << 12)
1032 #define RT5645_DMIC_1R_LH_RISING (0x1 << 12)
1033 #define RT5645_DMIC_2_DP_MASK (0x3 << 10)
1034 #define RT5645_DMIC_2_DP_SFT 10
1035 #define RT5645_DMIC_2_DP_GPIO6 (0x0 << 10)
1036 #define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10)
1037 #define RT5645_DMIC_2_DP_GPIO12 (0x2 << 10)
1038 #define RT5645_DMIC_2_DP_IN2P (0x3 << 10)
1039 #define RT5645_DMIC_2L_LH_MASK (0x1 << 9)
1040 #define RT5645_DMIC_2L_LH_SFT 9
1041 #define RT5645_DMIC_2L_LH_FALLING (0x0 << 9)
1042 #define RT5645_DMIC_2L_LH_RISING (0x1 << 9)
1043 #define RT5645_DMIC_2R_LH_MASK (0x1 << 8)
1044 #define RT5645_DMIC_2R_LH_SFT 8
1045 #define RT5645_DMIC_2R_LH_FALLING (0x0 << 8)
1046 #define RT5645_DMIC_2R_LH_RISING (0x1 << 8)
1047 #define RT5645_DMIC_CLK_MASK (0x7 << 5)
1048 #define RT5645_DMIC_CLK_SFT 5
1049 #define RT5645_DMIC_3_EN_MASK (0x1 << 4)
1050 #define RT5645_DMIC_3_EN_SFT 4
1051 #define RT5645_DMIC_3_DIS (0x0 << 4)
1052 #define RT5645_DMIC_3_EN (0x1 << 4)
1053 #define RT5645_DMIC_1_DP_MASK (0x3 << 0)
1054 #define RT5645_DMIC_1_DP_SFT 0
1055 #define RT5645_DMIC_1_DP_GPIO5 (0x0 << 0)
1056 #define RT5645_DMIC_1_DP_IN2N (0x1 << 0)
1057 #define RT5645_DMIC_1_DP_GPIO11 (0x2 << 0)
1058
1059
1060 #define RT5645_IF1_ADC_IN_MASK (0x3 << 8)
1061 #define RT5645_IF1_ADC_IN_SFT 8
1062
1063
1064 #define RT5645_SCLK_SRC_MASK (0x3 << 14)
1065 #define RT5645_SCLK_SRC_SFT 14
1066 #define RT5645_SCLK_SRC_MCLK (0x0 << 14)
1067 #define RT5645_SCLK_SRC_PLL1 (0x1 << 14)
1068 #define RT5645_SCLK_SRC_RCCLK (0x2 << 14)
1069 #define RT5645_PLL1_SRC_MASK (0x7 << 11)
1070 #define RT5645_PLL1_SRC_SFT 11
1071 #define RT5645_PLL1_SRC_MCLK (0x0 << 11)
1072 #define RT5645_PLL1_SRC_BCLK1 (0x1 << 11)
1073 #define RT5645_PLL1_SRC_BCLK2 (0x2 << 11)
1074 #define RT5645_PLL1_SRC_BCLK3 (0x3 << 11)
1075 #define RT5645_PLL1_SRC_RCCLK (0x4 << 11)
1076 #define RT5645_PLL1_PD_MASK (0x1 << 3)
1077 #define RT5645_PLL1_PD_SFT 3
1078 #define RT5645_PLL1_PD_1 (0x0 << 3)
1079 #define RT5645_PLL1_PD_2 (0x1 << 3)
1080
1081 #define RT5645_PLL_INP_MAX 40000000
1082 #define RT5645_PLL_INP_MIN 256000
1083
1084 #define RT5645_PLL_N_MAX 0x1ff
1085 #define RT5645_PLL_N_MASK (RT5645_PLL_N_MAX << 7)
1086 #define RT5645_PLL_N_SFT 7
1087 #define RT5645_PLL_K_MAX 0x1f
1088 #define RT5645_PLL_K_MASK (RT5645_PLL_K_MAX)
1089 #define RT5645_PLL_K_SFT 0
1090
1091
1092 #define RT5645_PLL_M_MAX 0xf
1093 #define RT5645_PLL_M_MASK (RT5645_PLL_M_MAX << 12)
1094 #define RT5645_PLL_M_SFT 12
1095 #define RT5645_PLL_M_BP (0x1 << 11)
1096 #define RT5645_PLL_M_BP_SFT 11
1097
1098
1099 #define RT5645_STO_T_MASK (0x1 << 15)
1100 #define RT5645_STO_T_SFT 15
1101 #define RT5645_STO_T_SCLK (0x0 << 15)
1102 #define RT5645_STO_T_LRCK1 (0x1 << 15)
1103 #define RT5645_M1_T_MASK (0x1 << 14)
1104 #define RT5645_M1_T_SFT 14
1105 #define RT5645_M1_T_I2S2 (0x0 << 14)
1106 #define RT5645_M1_T_I2S2_D3 (0x1 << 14)
1107 #define RT5645_I2S2_F_MASK (0x1 << 12)
1108 #define RT5645_I2S2_F_SFT 12
1109 #define RT5645_I2S2_F_I2S2_D2 (0x0 << 12)
1110 #define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12)
1111 #define RT5645_DMIC_1_M_MASK (0x1 << 9)
1112 #define RT5645_DMIC_1_M_SFT 9
1113 #define RT5645_DMIC_1_M_NOR (0x0 << 9)
1114 #define RT5645_DMIC_1_M_ASYN (0x1 << 9)
1115 #define RT5645_DMIC_2_M_MASK (0x1 << 8)
1116 #define RT5645_DMIC_2_M_SFT 8
1117 #define RT5645_DMIC_2_M_NOR (0x0 << 8)
1118 #define RT5645_DMIC_2_M_ASYN (0x1 << 8)
1119
1120
1121 #define RT5645_CLK_SEL_SYS (0x0)
1122 #define RT5645_CLK_SEL_I2S1_ASRC (0x1)
1123 #define RT5645_CLK_SEL_I2S2_ASRC (0x2)
1124 #define RT5645_CLK_SEL_SYS2 (0x5)
1125
1126
1127 #define RT5645_DA_STO_CLK_SEL_MASK (0xf << 12)
1128 #define RT5645_DA_STO_CLK_SEL_SFT 12
1129 #define RT5645_DA_MONOL_CLK_SEL_MASK (0xf << 8)
1130 #define RT5645_DA_MONOL_CLK_SEL_SFT 8
1131 #define RT5645_DA_MONOR_CLK_SEL_MASK (0xf << 4)
1132 #define RT5645_DA_MONOR_CLK_SEL_SFT 4
1133 #define RT5645_AD_STO1_CLK_SEL_MASK (0xf << 0)
1134 #define RT5645_AD_STO1_CLK_SEL_SFT 0
1135
1136
1137 #define RT5645_AD_MONOL_CLK_SEL_MASK (0xf << 4)
1138 #define RT5645_AD_MONOL_CLK_SEL_SFT 4
1139 #define RT5645_AD_MONOR_CLK_SEL_MASK (0xf << 0)
1140 #define RT5645_AD_MONOR_CLK_SEL_SFT 0
1141
1142
1143 #define RT5645_I2S1_PD_MASK (0x7 << 12)
1144 #define RT5645_I2S1_PD_SFT 12
1145 #define RT5645_I2S2_PD_MASK (0x7 << 8)
1146 #define RT5645_I2S2_PD_SFT 8
1147
1148
1149 #define RT5645_HP_OVCD_MASK (0x1 << 10)
1150 #define RT5645_HP_OVCD_SFT 10
1151 #define RT5645_HP_OVCD_DIS (0x0 << 10)
1152 #define RT5645_HP_OVCD_EN (0x1 << 10)
1153 #define RT5645_HP_OC_TH_MASK (0x3 << 8)
1154 #define RT5645_HP_OC_TH_SFT 8
1155 #define RT5645_HP_OC_TH_90 (0x0 << 8)
1156 #define RT5645_HP_OC_TH_105 (0x1 << 8)
1157 #define RT5645_HP_OC_TH_120 (0x2 << 8)
1158 #define RT5645_HP_OC_TH_135 (0x3 << 8)
1159
1160
1161 #define RT5645_CLSD_OC_MASK (0x1 << 9)
1162 #define RT5645_CLSD_OC_SFT 9
1163 #define RT5645_CLSD_OC_PU (0x0 << 9)
1164 #define RT5645_CLSD_OC_PD (0x1 << 9)
1165 #define RT5645_AUTO_PD_MASK (0x1 << 8)
1166 #define RT5645_AUTO_PD_SFT 8
1167 #define RT5645_AUTO_PD_DIS (0x0 << 8)
1168 #define RT5645_AUTO_PD_EN (0x1 << 8)
1169 #define RT5645_CLSD_OC_TH_MASK (0x3f)
1170 #define RT5645_CLSD_OC_TH_SFT 0
1171
1172
1173 #define RT5645_CLSD_RATIO_MASK (0xf << 12)
1174 #define RT5645_CLSD_RATIO_SFT 12
1175 #define RT5645_CLSD_OM_MASK (0x1 << 11)
1176 #define RT5645_CLSD_OM_SFT 11
1177 #define RT5645_CLSD_OM_MONO (0x0 << 11)
1178 #define RT5645_CLSD_OM_STO (0x1 << 11)
1179 #define RT5645_CLSD_SCH_MASK (0x1 << 10)
1180 #define RT5645_CLSD_SCH_SFT 10
1181 #define RT5645_CLSD_SCH_L (0x0 << 10)
1182 #define RT5645_CLSD_SCH_S (0x1 << 10)
1183
1184
1185 #define RT5645_SMT_TRIG_MASK (0x1 << 15)
1186 #define RT5645_SMT_TRIG_SFT 15
1187 #define RT5645_SMT_TRIG_DIS (0x0 << 15)
1188 #define RT5645_SMT_TRIG_EN (0x1 << 15)
1189 #define RT5645_HP_L_SMT_MASK (0x1 << 9)
1190 #define RT5645_HP_L_SMT_SFT 9
1191 #define RT5645_HP_L_SMT_DIS (0x0 << 9)
1192 #define RT5645_HP_L_SMT_EN (0x1 << 9)
1193 #define RT5645_HP_R_SMT_MASK (0x1 << 8)
1194 #define RT5645_HP_R_SMT_SFT 8
1195 #define RT5645_HP_R_SMT_DIS (0x0 << 8)
1196 #define RT5645_HP_R_SMT_EN (0x1 << 8)
1197 #define RT5645_HP_CD_PD_MASK (0x1 << 7)
1198 #define RT5645_HP_CD_PD_SFT 7
1199 #define RT5645_HP_CD_PD_DIS (0x0 << 7)
1200 #define RT5645_HP_CD_PD_EN (0x1 << 7)
1201 #define RT5645_RSTN_MASK (0x1 << 6)
1202 #define RT5645_RSTN_SFT 6
1203 #define RT5645_RSTN_DIS (0x0 << 6)
1204 #define RT5645_RSTN_EN (0x1 << 6)
1205 #define RT5645_RSTP_MASK (0x1 << 5)
1206 #define RT5645_RSTP_SFT 5
1207 #define RT5645_RSTP_DIS (0x0 << 5)
1208 #define RT5645_RSTP_EN (0x1 << 5)
1209 #define RT5645_HP_CO_MASK (0x1 << 4)
1210 #define RT5645_HP_CO_SFT 4
1211 #define RT5645_HP_CO_DIS (0x0 << 4)
1212 #define RT5645_HP_CO_EN (0x1 << 4)
1213 #define RT5645_HP_CP_MASK (0x1 << 3)
1214 #define RT5645_HP_CP_SFT 3
1215 #define RT5645_HP_CP_PD (0x0 << 3)
1216 #define RT5645_HP_CP_PU (0x1 << 3)
1217 #define RT5645_HP_SG_MASK (0x1 << 2)
1218 #define RT5645_HP_SG_SFT 2
1219 #define RT5645_HP_SG_DIS (0x0 << 2)
1220 #define RT5645_HP_SG_EN (0x1 << 2)
1221 #define RT5645_HP_DP_MASK (0x1 << 1)
1222 #define RT5645_HP_DP_SFT 1
1223 #define RT5645_HP_DP_PD (0x0 << 1)
1224 #define RT5645_HP_DP_PU (0x1 << 1)
1225 #define RT5645_HP_CB_MASK (0x1)
1226 #define RT5645_HP_CB_SFT 0
1227 #define RT5645_HP_CB_PD (0x0)
1228 #define RT5645_HP_CB_PU (0x1)
1229
1230
1231 #define RT5645_DEPOP_MASK (0x1 << 13)
1232 #define RT5645_DEPOP_SFT 13
1233 #define RT5645_DEPOP_AUTO (0x0 << 13)
1234 #define RT5645_DEPOP_MAN (0x1 << 13)
1235 #define RT5645_RAMP_MASK (0x1 << 12)
1236 #define RT5645_RAMP_SFT 12
1237 #define RT5645_RAMP_DIS (0x0 << 12)
1238 #define RT5645_RAMP_EN (0x1 << 12)
1239 #define RT5645_BPS_MASK (0x1 << 11)
1240 #define RT5645_BPS_SFT 11
1241 #define RT5645_BPS_DIS (0x0 << 11)
1242 #define RT5645_BPS_EN (0x1 << 11)
1243 #define RT5645_FAST_UPDN_MASK (0x1 << 10)
1244 #define RT5645_FAST_UPDN_SFT 10
1245 #define RT5645_FAST_UPDN_DIS (0x0 << 10)
1246 #define RT5645_FAST_UPDN_EN (0x1 << 10)
1247 #define RT5645_MRES_MASK (0x3 << 8)
1248 #define RT5645_MRES_SFT 8
1249 #define RT5645_MRES_15MO (0x0 << 8)
1250 #define RT5645_MRES_25MO (0x1 << 8)
1251 #define RT5645_MRES_35MO (0x2 << 8)
1252 #define RT5645_MRES_45MO (0x3 << 8)
1253 #define RT5645_VLO_MASK (0x1 << 7)
1254 #define RT5645_VLO_SFT 7
1255 #define RT5645_VLO_3V (0x0 << 7)
1256 #define RT5645_VLO_32V (0x1 << 7)
1257 #define RT5645_DIG_DP_MASK (0x1 << 6)
1258 #define RT5645_DIG_DP_SFT 6
1259 #define RT5645_DIG_DP_DIS (0x0 << 6)
1260 #define RT5645_DIG_DP_EN (0x1 << 6)
1261 #define RT5645_DP_TH_MASK (0x3 << 4)
1262 #define RT5645_DP_TH_SFT 4
1263
1264
1265 #define RT5645_CP_SYS_MASK (0x7 << 12)
1266 #define RT5645_CP_SYS_SFT 12
1267 #define RT5645_CP_FQ1_MASK (0x7 << 8)
1268 #define RT5645_CP_FQ1_SFT 8
1269 #define RT5645_CP_FQ2_MASK (0x7 << 4)
1270 #define RT5645_CP_FQ2_SFT 4
1271 #define RT5645_CP_FQ3_MASK (0x7)
1272 #define RT5645_CP_FQ3_SFT 0
1273 #define RT5645_CP_FQ_1_5_KHZ 0
1274 #define RT5645_CP_FQ_3_KHZ 1
1275 #define RT5645_CP_FQ_6_KHZ 2
1276 #define RT5645_CP_FQ_12_KHZ 3
1277 #define RT5645_CP_FQ_24_KHZ 4
1278 #define RT5645_CP_FQ_48_KHZ 5
1279 #define RT5645_CP_FQ_96_KHZ 6
1280 #define RT5645_CP_FQ_192_KHZ 7
1281
1282
1283 #define RT5645_PVDD_DET_MASK (0x1 << 15)
1284 #define RT5645_PVDD_DET_SFT 15
1285 #define RT5645_PVDD_DET_DIS (0x0 << 15)
1286 #define RT5645_PVDD_DET_EN (0x1 << 15)
1287 #define RT5645_SPK_AG_MASK (0x1 << 14)
1288 #define RT5645_SPK_AG_SFT 14
1289 #define RT5645_SPK_AG_DIS (0x0 << 14)
1290 #define RT5645_SPK_AG_EN (0x1 << 14)
1291
1292
1293 #define RT5645_MIC1_BS_MASK (0x1 << 15)
1294 #define RT5645_MIC1_BS_SFT 15
1295 #define RT5645_MIC1_BS_9AV (0x0 << 15)
1296 #define RT5645_MIC1_BS_75AV (0x1 << 15)
1297 #define RT5645_MIC2_BS_MASK (0x1 << 14)
1298 #define RT5645_MIC2_BS_SFT 14
1299 #define RT5645_MIC2_BS_9AV (0x0 << 14)
1300 #define RT5645_MIC2_BS_75AV (0x1 << 14)
1301 #define RT5645_MIC1_CLK_MASK (0x1 << 13)
1302 #define RT5645_MIC1_CLK_SFT 13
1303 #define RT5645_MIC1_CLK_DIS (0x0 << 13)
1304 #define RT5645_MIC1_CLK_EN (0x1 << 13)
1305 #define RT5645_MIC2_CLK_MASK (0x1 << 12)
1306 #define RT5645_MIC2_CLK_SFT 12
1307 #define RT5645_MIC2_CLK_DIS (0x0 << 12)
1308 #define RT5645_MIC2_CLK_EN (0x1 << 12)
1309 #define RT5645_MIC1_OVCD_MASK (0x1 << 11)
1310 #define RT5645_MIC1_OVCD_SFT 11
1311 #define RT5645_MIC1_OVCD_DIS (0x0 << 11)
1312 #define RT5645_MIC1_OVCD_EN (0x1 << 11)
1313 #define RT5645_MIC1_OVTH_MASK (0x3 << 9)
1314 #define RT5645_MIC1_OVTH_SFT 9
1315 #define RT5645_MIC1_OVTH_600UA (0x0 << 9)
1316 #define RT5645_MIC1_OVTH_1500UA (0x1 << 9)
1317 #define RT5645_MIC1_OVTH_2000UA (0x2 << 9)
1318 #define RT5645_MIC2_OVCD_MASK (0x1 << 8)
1319 #define RT5645_MIC2_OVCD_SFT 8
1320 #define RT5645_MIC2_OVCD_DIS (0x0 << 8)
1321 #define RT5645_MIC2_OVCD_EN (0x1 << 8)
1322 #define RT5645_MIC2_OVTH_MASK (0x3 << 6)
1323 #define RT5645_MIC2_OVTH_SFT 6
1324 #define RT5645_MIC2_OVTH_600UA (0x0 << 6)
1325 #define RT5645_MIC2_OVTH_1500UA (0x1 << 6)
1326 #define RT5645_MIC2_OVTH_2000UA (0x2 << 6)
1327 #define RT5645_PWR_MB_MASK (0x1 << 5)
1328 #define RT5645_PWR_MB_SFT 5
1329 #define RT5645_PWR_MB_PD (0x0 << 5)
1330 #define RT5645_PWR_MB_PU (0x1 << 5)
1331 #define RT5645_PWR_CLK25M_MASK (0x1 << 4)
1332 #define RT5645_PWR_CLK25M_SFT 4
1333 #define RT5645_PWR_CLK25M_PD (0x0 << 4)
1334 #define RT5645_PWR_CLK25M_PU (0x1 << 4)
1335 #define RT5645_IRQ_CLK_MCLK (0x0 << 3)
1336 #define RT5645_IRQ_CLK_INT (0x1 << 3)
1337 #define RT5645_JD1_MODE_MASK (0x3 << 0)
1338 #define RT5645_JD1_MODE_0 (0x0 << 0)
1339 #define RT5645_JD1_MODE_1 (0x1 << 0)
1340 #define RT5645_JD1_MODE_2 (0x2 << 0)
1341
1342
1343 #define RT5645_VAD_SEL_MASK (0x3 << 8)
1344 #define RT5645_VAD_SEL_SFT 8
1345
1346
1347 #define RT5645_EQ_SRC_MASK (0x1 << 15)
1348 #define RT5645_EQ_SRC_SFT 15
1349 #define RT5645_EQ_SRC_DAC (0x0 << 15)
1350 #define RT5645_EQ_SRC_ADC (0x1 << 15)
1351 #define RT5645_EQ_UPD (0x1 << 14)
1352 #define RT5645_EQ_UPD_BIT 14
1353 #define RT5645_EQ_CD_MASK (0x1 << 13)
1354 #define RT5645_EQ_CD_SFT 13
1355 #define RT5645_EQ_CD_DIS (0x0 << 13)
1356 #define RT5645_EQ_CD_EN (0x1 << 13)
1357 #define RT5645_EQ_DITH_MASK (0x3 << 8)
1358 #define RT5645_EQ_DITH_SFT 8
1359 #define RT5645_EQ_DITH_NOR (0x0 << 8)
1360 #define RT5645_EQ_DITH_LSB (0x1 << 8)
1361 #define RT5645_EQ_DITH_LSB_1 (0x2 << 8)
1362 #define RT5645_EQ_DITH_LSB_2 (0x3 << 8)
1363
1364
1365 #define RT5645_EQ_HPF1_M_MASK (0x1 << 8)
1366 #define RT5645_EQ_HPF1_M_SFT 8
1367 #define RT5645_EQ_HPF1_M_HI (0x0 << 8)
1368 #define RT5645_EQ_HPF1_M_1ST (0x1 << 8)
1369 #define RT5645_EQ_LPF1_M_MASK (0x1 << 7)
1370 #define RT5645_EQ_LPF1_M_SFT 7
1371 #define RT5645_EQ_LPF1_M_LO (0x0 << 7)
1372 #define RT5645_EQ_LPF1_M_1ST (0x1 << 7)
1373 #define RT5645_EQ_HPF2_MASK (0x1 << 6)
1374 #define RT5645_EQ_HPF2_SFT 6
1375 #define RT5645_EQ_HPF2_DIS (0x0 << 6)
1376 #define RT5645_EQ_HPF2_EN (0x1 << 6)
1377 #define RT5645_EQ_HPF1_MASK (0x1 << 5)
1378 #define RT5645_EQ_HPF1_SFT 5
1379 #define RT5645_EQ_HPF1_DIS (0x0 << 5)
1380 #define RT5645_EQ_HPF1_EN (0x1 << 5)
1381 #define RT5645_EQ_BPF4_MASK (0x1 << 4)
1382 #define RT5645_EQ_BPF4_SFT 4
1383 #define RT5645_EQ_BPF4_DIS (0x0 << 4)
1384 #define RT5645_EQ_BPF4_EN (0x1 << 4)
1385 #define RT5645_EQ_BPF3_MASK (0x1 << 3)
1386 #define RT5645_EQ_BPF3_SFT 3
1387 #define RT5645_EQ_BPF3_DIS (0x0 << 3)
1388 #define RT5645_EQ_BPF3_EN (0x1 << 3)
1389 #define RT5645_EQ_BPF2_MASK (0x1 << 2)
1390 #define RT5645_EQ_BPF2_SFT 2
1391 #define RT5645_EQ_BPF2_DIS (0x0 << 2)
1392 #define RT5645_EQ_BPF2_EN (0x1 << 2)
1393 #define RT5645_EQ_BPF1_MASK (0x1 << 1)
1394 #define RT5645_EQ_BPF1_SFT 1
1395 #define RT5645_EQ_BPF1_DIS (0x0 << 1)
1396 #define RT5645_EQ_BPF1_EN (0x1 << 1)
1397 #define RT5645_EQ_LPF_MASK (0x1)
1398 #define RT5645_EQ_LPF_SFT 0
1399 #define RT5645_EQ_LPF_DIS (0x0)
1400 #define RT5645_EQ_LPF_EN (0x1)
1401 #define RT5645_EQ_CTRL_MASK (0x7f)
1402
1403
1404 #define RT5645_MT_MASK (0x1 << 15)
1405 #define RT5645_MT_SFT 15
1406 #define RT5645_MT_DIS (0x0 << 15)
1407 #define RT5645_MT_EN (0x1 << 15)
1408
1409
1410 #define RT5645_DRC_AGC_P_MASK (0x1 << 15)
1411 #define RT5645_DRC_AGC_P_SFT 15
1412 #define RT5645_DRC_AGC_P_DAC (0x0 << 15)
1413 #define RT5645_DRC_AGC_P_ADC (0x1 << 15)
1414 #define RT5645_DRC_AGC_MASK (0x1 << 14)
1415 #define RT5645_DRC_AGC_SFT 14
1416 #define RT5645_DRC_AGC_DIS (0x0 << 14)
1417 #define RT5645_DRC_AGC_EN (0x1 << 14)
1418 #define RT5645_DRC_AGC_UPD (0x1 << 13)
1419 #define RT5645_DRC_AGC_UPD_BIT 13
1420 #define RT5645_DRC_AGC_AR_MASK (0x1f << 8)
1421 #define RT5645_DRC_AGC_AR_SFT 8
1422 #define RT5645_DRC_AGC_R_MASK (0x7 << 5)
1423 #define RT5645_DRC_AGC_R_SFT 5
1424 #define RT5645_DRC_AGC_R_48K (0x1 << 5)
1425 #define RT5645_DRC_AGC_R_96K (0x2 << 5)
1426 #define RT5645_DRC_AGC_R_192K (0x3 << 5)
1427 #define RT5645_DRC_AGC_R_441K (0x5 << 5)
1428 #define RT5645_DRC_AGC_R_882K (0x6 << 5)
1429 #define RT5645_DRC_AGC_R_1764K (0x7 << 5)
1430 #define RT5645_DRC_AGC_RC_MASK (0x1f)
1431 #define RT5645_DRC_AGC_RC_SFT 0
1432
1433
1434 #define RT5645_DRC_AGC_POB_MASK (0x3f << 8)
1435 #define RT5645_DRC_AGC_POB_SFT 8
1436 #define RT5645_DRC_AGC_CP_MASK (0x1 << 7)
1437 #define RT5645_DRC_AGC_CP_SFT 7
1438 #define RT5645_DRC_AGC_CP_DIS (0x0 << 7)
1439 #define RT5645_DRC_AGC_CP_EN (0x1 << 7)
1440 #define RT5645_DRC_AGC_CPR_MASK (0x3 << 5)
1441 #define RT5645_DRC_AGC_CPR_SFT 5
1442 #define RT5645_DRC_AGC_CPR_1_1 (0x0 << 5)
1443 #define RT5645_DRC_AGC_CPR_1_2 (0x1 << 5)
1444 #define RT5645_DRC_AGC_CPR_1_3 (0x2 << 5)
1445 #define RT5645_DRC_AGC_CPR_1_4 (0x3 << 5)
1446 #define RT5645_DRC_AGC_PRB_MASK (0x1f)
1447 #define RT5645_DRC_AGC_PRB_SFT 0
1448
1449
1450 #define RT5645_DRC_AGC_NGB_MASK (0xf << 12)
1451 #define RT5645_DRC_AGC_NGB_SFT 12
1452 #define RT5645_DRC_AGC_TAR_MASK (0x1f << 7)
1453 #define RT5645_DRC_AGC_TAR_SFT 7
1454 #define RT5645_DRC_AGC_NG_MASK (0x1 << 6)
1455 #define RT5645_DRC_AGC_NG_SFT 6
1456 #define RT5645_DRC_AGC_NG_DIS (0x0 << 6)
1457 #define RT5645_DRC_AGC_NG_EN (0x1 << 6)
1458 #define RT5645_DRC_AGC_NGH_MASK (0x1 << 5)
1459 #define RT5645_DRC_AGC_NGH_SFT 5
1460 #define RT5645_DRC_AGC_NGH_DIS (0x0 << 5)
1461 #define RT5645_DRC_AGC_NGH_EN (0x1 << 5)
1462 #define RT5645_DRC_AGC_NGT_MASK (0x1f)
1463 #define RT5645_DRC_AGC_NGT_SFT 0
1464
1465
1466 #define RT5645_ANC_M_MASK (0x1 << 15)
1467 #define RT5645_ANC_M_SFT 15
1468 #define RT5645_ANC_M_NOR (0x0 << 15)
1469 #define RT5645_ANC_M_REV (0x1 << 15)
1470 #define RT5645_ANC_MASK (0x1 << 14)
1471 #define RT5645_ANC_SFT 14
1472 #define RT5645_ANC_DIS (0x0 << 14)
1473 #define RT5645_ANC_EN (0x1 << 14)
1474 #define RT5645_ANC_MD_MASK (0x3 << 12)
1475 #define RT5645_ANC_MD_SFT 12
1476 #define RT5645_ANC_MD_DIS (0x0 << 12)
1477 #define RT5645_ANC_MD_67MS (0x1 << 12)
1478 #define RT5645_ANC_MD_267MS (0x2 << 12)
1479 #define RT5645_ANC_MD_1067MS (0x3 << 12)
1480 #define RT5645_ANC_SN_MASK (0x1 << 11)
1481 #define RT5645_ANC_SN_SFT 11
1482 #define RT5645_ANC_SN_DIS (0x0 << 11)
1483 #define RT5645_ANC_SN_EN (0x1 << 11)
1484 #define RT5645_ANC_CLK_MASK (0x1 << 10)
1485 #define RT5645_ANC_CLK_SFT 10
1486 #define RT5645_ANC_CLK_ANC (0x0 << 10)
1487 #define RT5645_ANC_CLK_REG (0x1 << 10)
1488 #define RT5645_ANC_ZCD_MASK (0x3 << 8)
1489 #define RT5645_ANC_ZCD_SFT 8
1490 #define RT5645_ANC_ZCD_DIS (0x0 << 8)
1491 #define RT5645_ANC_ZCD_T1 (0x1 << 8)
1492 #define RT5645_ANC_ZCD_T2 (0x2 << 8)
1493 #define RT5645_ANC_ZCD_WT (0x3 << 8)
1494 #define RT5645_ANC_CS_MASK (0x1 << 7)
1495 #define RT5645_ANC_CS_SFT 7
1496 #define RT5645_ANC_CS_DIS (0x0 << 7)
1497 #define RT5645_ANC_CS_EN (0x1 << 7)
1498 #define RT5645_ANC_SW_MASK (0x1 << 6)
1499 #define RT5645_ANC_SW_SFT 6
1500 #define RT5645_ANC_SW_NOR (0x0 << 6)
1501 #define RT5645_ANC_SW_AUTO (0x1 << 6)
1502 #define RT5645_ANC_CO_L_MASK (0x3f)
1503 #define RT5645_ANC_CO_L_SFT 0
1504
1505
1506 #define RT5645_ANC_FG_R_MASK (0xf << 12)
1507 #define RT5645_ANC_FG_R_SFT 12
1508 #define RT5645_ANC_FG_L_MASK (0xf << 8)
1509 #define RT5645_ANC_FG_L_SFT 8
1510 #define RT5645_ANC_CG_R_MASK (0xf << 4)
1511 #define RT5645_ANC_CG_R_SFT 4
1512 #define RT5645_ANC_CG_L_MASK (0xf)
1513 #define RT5645_ANC_CG_L_SFT 0
1514
1515
1516 #define RT5645_ANC_CD_MASK (0x1 << 6)
1517 #define RT5645_ANC_CD_SFT 6
1518 #define RT5645_ANC_CD_BOTH (0x0 << 6)
1519 #define RT5645_ANC_CD_IND (0x1 << 6)
1520 #define RT5645_ANC_CO_R_MASK (0x3f)
1521 #define RT5645_ANC_CO_R_SFT 0
1522
1523
1524 #define RT5645_JD_MASK (0x7 << 13)
1525 #define RT5645_JD_SFT 13
1526 #define RT5645_JD_DIS (0x0 << 13)
1527 #define RT5645_JD_GPIO1 (0x1 << 13)
1528 #define RT5645_JD_JD1_IN4P (0x2 << 13)
1529 #define RT5645_JD_JD2_IN4N (0x3 << 13)
1530 #define RT5645_JD_GPIO2 (0x4 << 13)
1531 #define RT5645_JD_GPIO3 (0x5 << 13)
1532 #define RT5645_JD_GPIO4 (0x6 << 13)
1533 #define RT5645_JD_HP_MASK (0x1 << 11)
1534 #define RT5645_JD_HP_SFT 11
1535 #define RT5645_JD_HP_DIS (0x0 << 11)
1536 #define RT5645_JD_HP_EN (0x1 << 11)
1537 #define RT5645_JD_HP_TRG_MASK (0x1 << 10)
1538 #define RT5645_JD_HP_TRG_SFT 10
1539 #define RT5645_JD_HP_TRG_LO (0x0 << 10)
1540 #define RT5645_JD_HP_TRG_HI (0x1 << 10)
1541 #define RT5645_JD_SPL_MASK (0x1 << 9)
1542 #define RT5645_JD_SPL_SFT 9
1543 #define RT5645_JD_SPL_DIS (0x0 << 9)
1544 #define RT5645_JD_SPL_EN (0x1 << 9)
1545 #define RT5645_JD_SPL_TRG_MASK (0x1 << 8)
1546 #define RT5645_JD_SPL_TRG_SFT 8
1547 #define RT5645_JD_SPL_TRG_LO (0x0 << 8)
1548 #define RT5645_JD_SPL_TRG_HI (0x1 << 8)
1549 #define RT5645_JD_SPR_MASK (0x1 << 7)
1550 #define RT5645_JD_SPR_SFT 7
1551 #define RT5645_JD_SPR_DIS (0x0 << 7)
1552 #define RT5645_JD_SPR_EN (0x1 << 7)
1553 #define RT5645_JD_SPR_TRG_MASK (0x1 << 6)
1554 #define RT5645_JD_SPR_TRG_SFT 6
1555 #define RT5645_JD_SPR_TRG_LO (0x0 << 6)
1556 #define RT5645_JD_SPR_TRG_HI (0x1 << 6)
1557 #define RT5645_JD_MO_MASK (0x1 << 5)
1558 #define RT5645_JD_MO_SFT 5
1559 #define RT5645_JD_MO_DIS (0x0 << 5)
1560 #define RT5645_JD_MO_EN (0x1 << 5)
1561 #define RT5645_JD_MO_TRG_MASK (0x1 << 4)
1562 #define RT5645_JD_MO_TRG_SFT 4
1563 #define RT5645_JD_MO_TRG_LO (0x0 << 4)
1564 #define RT5645_JD_MO_TRG_HI (0x1 << 4)
1565 #define RT5645_JD_LO_MASK (0x1 << 3)
1566 #define RT5645_JD_LO_SFT 3
1567 #define RT5645_JD_LO_DIS (0x0 << 3)
1568 #define RT5645_JD_LO_EN (0x1 << 3)
1569 #define RT5645_JD_LO_TRG_MASK (0x1 << 2)
1570 #define RT5645_JD_LO_TRG_SFT 2
1571 #define RT5645_JD_LO_TRG_LO (0x0 << 2)
1572 #define RT5645_JD_LO_TRG_HI (0x1 << 2)
1573 #define RT5645_JD1_IN4P_MASK (0x1 << 1)
1574 #define RT5645_JD1_IN4P_SFT 1
1575 #define RT5645_JD1_IN4P_DIS (0x0 << 1)
1576 #define RT5645_JD1_IN4P_EN (0x1 << 1)
1577 #define RT5645_JD2_IN4N_MASK (0x1)
1578 #define RT5645_JD2_IN4N_SFT 0
1579 #define RT5645_JD2_IN4N_DIS (0x0)
1580 #define RT5645_JD2_IN4N_EN (0x1)
1581
1582
1583 #define RT5645_ANC_DET_MASK (0x3 << 4)
1584 #define RT5645_ANC_DET_SFT 4
1585 #define RT5645_ANC_DET_DIS (0x0 << 4)
1586 #define RT5645_ANC_DET_MB1 (0x1 << 4)
1587 #define RT5645_ANC_DET_MB2 (0x2 << 4)
1588 #define RT5645_ANC_DET_JD (0x3 << 4)
1589 #define RT5645_AD_TRG_MASK (0x1 << 3)
1590 #define RT5645_AD_TRG_SFT 3
1591 #define RT5645_AD_TRG_LO (0x0 << 3)
1592 #define RT5645_AD_TRG_HI (0x1 << 3)
1593 #define RT5645_ANCM_DET_MASK (0x3 << 4)
1594 #define RT5645_ANCM_DET_SFT 4
1595 #define RT5645_ANCM_DET_DIS (0x0 << 4)
1596 #define RT5645_ANCM_DET_MB1 (0x1 << 4)
1597 #define RT5645_ANCM_DET_MB2 (0x2 << 4)
1598 #define RT5645_ANCM_DET_JD (0x3 << 4)
1599 #define RT5645_AMD_TRG_MASK (0x1 << 3)
1600 #define RT5645_AMD_TRG_SFT 3
1601 #define RT5645_AMD_TRG_LO (0x0 << 3)
1602 #define RT5645_AMD_TRG_HI (0x1 << 3)
1603
1604
1605 #define RT5645_IRQ_JD_MASK (0x1 << 15)
1606 #define RT5645_IRQ_JD_SFT 15
1607 #define RT5645_IRQ_JD_BP (0x0 << 15)
1608 #define RT5645_IRQ_JD_NOR (0x1 << 15)
1609 #define RT5645_IRQ_OT_MASK (0x1 << 14)
1610 #define RT5645_IRQ_OT_SFT 14
1611 #define RT5645_IRQ_OT_BP (0x0 << 14)
1612 #define RT5645_IRQ_OT_NOR (0x1 << 14)
1613 #define RT5645_JD_STKY_MASK (0x1 << 13)
1614 #define RT5645_JD_STKY_SFT 13
1615 #define RT5645_JD_STKY_DIS (0x0 << 13)
1616 #define RT5645_JD_STKY_EN (0x1 << 13)
1617 #define RT5645_OT_STKY_MASK (0x1 << 12)
1618 #define RT5645_OT_STKY_SFT 12
1619 #define RT5645_OT_STKY_DIS (0x0 << 12)
1620 #define RT5645_OT_STKY_EN (0x1 << 12)
1621 #define RT5645_JD_P_MASK (0x1 << 11)
1622 #define RT5645_JD_P_SFT 11
1623 #define RT5645_JD_P_NOR (0x0 << 11)
1624 #define RT5645_JD_P_INV (0x1 << 11)
1625 #define RT5645_OT_P_MASK (0x1 << 10)
1626 #define RT5645_OT_P_SFT 10
1627 #define RT5645_OT_P_NOR (0x0 << 10)
1628 #define RT5645_OT_P_INV (0x1 << 10)
1629 #define RT5645_IRQ_JD_1_1_EN (0x1 << 9)
1630 #define RT5645_JD_1_1_MASK (0x1 << 7)
1631 #define RT5645_JD_1_1_SFT 7
1632 #define RT5645_JD_1_1_NOR (0x0 << 7)
1633 #define RT5645_JD_1_1_INV (0x1 << 7)
1634
1635
1636 #define RT5645_IRQ_MB1_OC_MASK (0x1 << 15)
1637 #define RT5645_IRQ_MB1_OC_SFT 15
1638 #define RT5645_IRQ_MB1_OC_BP (0x0 << 15)
1639 #define RT5645_IRQ_MB1_OC_NOR (0x1 << 15)
1640 #define RT5645_IRQ_MB2_OC_MASK (0x1 << 14)
1641 #define RT5645_IRQ_MB2_OC_SFT 14
1642 #define RT5645_IRQ_MB2_OC_BP (0x0 << 14)
1643 #define RT5645_IRQ_MB2_OC_NOR (0x1 << 14)
1644 #define RT5645_MB1_OC_STKY_MASK (0x1 << 13)
1645 #define RT5645_MB1_OC_STKY_SFT 13
1646 #define RT5645_MB1_OC_STKY_DIS (0x0 << 13)
1647 #define RT5645_MB1_OC_STKY_EN (0x1 << 13)
1648 #define RT5645_MB2_OC_STKY_MASK (0x1 << 12)
1649 #define RT5645_MB2_OC_STKY_SFT 12
1650 #define RT5645_MB2_OC_STKY_DIS (0x0 << 12)
1651 #define RT5645_MB2_OC_STKY_EN (0x1 << 12)
1652 #define RT5645_MB1_OC_P_MASK (0x1 << 7)
1653 #define RT5645_MB1_OC_P_SFT 7
1654 #define RT5645_MB1_OC_P_NOR (0x0 << 7)
1655 #define RT5645_MB1_OC_P_INV (0x1 << 7)
1656 #define RT5645_MB2_OC_P_MASK (0x1 << 6)
1657 #define RT5645_MB2_OC_P_SFT 6
1658 #define RT5645_MB2_OC_P_NOR (0x0 << 6)
1659 #define RT5645_MB2_OC_P_INV (0x1 << 6)
1660 #define RT5645_MB1_OC_CLR (0x1 << 3)
1661 #define RT5645_MB1_OC_CLR_SFT 3
1662 #define RT5645_MB2_OC_CLR (0x1 << 2)
1663 #define RT5645_MB2_OC_CLR_SFT 2
1664
1665
1666 #define RT5645_GP1_PIN_MASK (0x1 << 15)
1667 #define RT5645_GP1_PIN_SFT 15
1668 #define RT5645_GP1_PIN_GPIO1 (0x0 << 15)
1669 #define RT5645_GP1_PIN_IRQ (0x1 << 15)
1670 #define RT5645_GP2_PIN_MASK (0x1 << 14)
1671 #define RT5645_GP2_PIN_SFT 14
1672 #define RT5645_GP2_PIN_GPIO2 (0x0 << 14)
1673 #define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14)
1674 #define RT5645_GP3_PIN_MASK (0x3 << 12)
1675 #define RT5645_GP3_PIN_SFT 12
1676 #define RT5645_GP3_PIN_GPIO3 (0x0 << 12)
1677 #define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12)
1678 #define RT5645_GP3_PIN_IRQ (0x2 << 12)
1679 #define RT5645_GP4_PIN_MASK (0x1 << 11)
1680 #define RT5645_GP4_PIN_SFT 11
1681 #define RT5645_GP4_PIN_GPIO4 (0x0 << 11)
1682 #define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11)
1683 #define RT5645_DP_SIG_MASK (0x1 << 10)
1684 #define RT5645_DP_SIG_SFT 10
1685 #define RT5645_DP_SIG_TEST (0x0 << 10)
1686 #define RT5645_DP_SIG_AP (0x1 << 10)
1687 #define RT5645_GPIO_M_MASK (0x1 << 9)
1688 #define RT5645_GPIO_M_SFT 9
1689 #define RT5645_GPIO_M_FLT (0x0 << 9)
1690 #define RT5645_GPIO_M_PH (0x1 << 9)
1691 #define RT5645_I2S2_SEL (0x1 << 8)
1692 #define RT5645_I2S2_SEL_SFT 8
1693 #define RT5645_GP5_PIN_MASK (0x1 << 7)
1694 #define RT5645_GP5_PIN_SFT 7
1695 #define RT5645_GP5_PIN_GPIO5 (0x0 << 7)
1696 #define RT5645_GP5_PIN_DMIC1_SDA (0x1 << 7)
1697 #define RT5645_GP6_PIN_MASK (0x1 << 6)
1698 #define RT5645_GP6_PIN_SFT 6
1699 #define RT5645_GP6_PIN_GPIO6 (0x0 << 6)
1700 #define RT5645_GP6_PIN_DMIC2_SDA (0x1 << 6)
1701 #define RT5645_I2S2_DAC_PIN_MASK (0x1 << 4)
1702 #define RT5645_I2S2_DAC_PIN_SFT 4
1703 #define RT5645_I2S2_DAC_PIN_I2S (0x0 << 4)
1704 #define RT5645_I2S2_DAC_PIN_GPIO (0x1 << 4)
1705 #define RT5645_GP8_PIN_MASK (0x1 << 3)
1706 #define RT5645_GP8_PIN_SFT 3
1707 #define RT5645_GP8_PIN_GPIO8 (0x0 << 3)
1708 #define RT5645_GP8_PIN_DMIC2_SDA (0x1 << 3)
1709 #define RT5645_GP12_PIN_MASK (0x1 << 2)
1710 #define RT5645_GP12_PIN_SFT 2
1711 #define RT5645_GP12_PIN_GPIO12 (0x0 << 2)
1712 #define RT5645_GP12_PIN_DMIC2_SDA (0x1 << 2)
1713 #define RT5645_GP11_PIN_MASK (0x1 << 1)
1714 #define RT5645_GP11_PIN_SFT 1
1715 #define RT5645_GP11_PIN_GPIO11 (0x0 << 1)
1716 #define RT5645_GP11_PIN_DMIC1_SDA (0x1 << 1)
1717 #define RT5645_GP10_PIN_MASK (0x1)
1718 #define RT5645_GP10_PIN_SFT 0
1719 #define RT5645_GP10_PIN_GPIO10 (0x0)
1720 #define RT5645_GP10_PIN_DMIC2_SDA (0x1)
1721
1722
1723 #define RT5645_GP4_PF_MASK (0x1 << 11)
1724 #define RT5645_GP4_PF_SFT 11
1725 #define RT5645_GP4_PF_IN (0x0 << 11)
1726 #define RT5645_GP4_PF_OUT (0x1 << 11)
1727 #define RT5645_GP4_OUT_MASK (0x1 << 10)
1728 #define RT5645_GP4_OUT_SFT 10
1729 #define RT5645_GP4_OUT_LO (0x0 << 10)
1730 #define RT5645_GP4_OUT_HI (0x1 << 10)
1731 #define RT5645_GP4_P_MASK (0x1 << 9)
1732 #define RT5645_GP4_P_SFT 9
1733 #define RT5645_GP4_P_NOR (0x0 << 9)
1734 #define RT5645_GP4_P_INV (0x1 << 9)
1735 #define RT5645_GP3_PF_MASK (0x1 << 8)
1736 #define RT5645_GP3_PF_SFT 8
1737 #define RT5645_GP3_PF_IN (0x0 << 8)
1738 #define RT5645_GP3_PF_OUT (0x1 << 8)
1739 #define RT5645_GP3_OUT_MASK (0x1 << 7)
1740 #define RT5645_GP3_OUT_SFT 7
1741 #define RT5645_GP3_OUT_LO (0x0 << 7)
1742 #define RT5645_GP3_OUT_HI (0x1 << 7)
1743 #define RT5645_GP3_P_MASK (0x1 << 6)
1744 #define RT5645_GP3_P_SFT 6
1745 #define RT5645_GP3_P_NOR (0x0 << 6)
1746 #define RT5645_GP3_P_INV (0x1 << 6)
1747 #define RT5645_GP2_PF_MASK (0x1 << 5)
1748 #define RT5645_GP2_PF_SFT 5
1749 #define RT5645_GP2_PF_IN (0x0 << 5)
1750 #define RT5645_GP2_PF_OUT (0x1 << 5)
1751 #define RT5645_GP2_OUT_MASK (0x1 << 4)
1752 #define RT5645_GP2_OUT_SFT 4
1753 #define RT5645_GP2_OUT_LO (0x0 << 4)
1754 #define RT5645_GP2_OUT_HI (0x1 << 4)
1755 #define RT5645_GP2_P_MASK (0x1 << 3)
1756 #define RT5645_GP2_P_SFT 3
1757 #define RT5645_GP2_P_NOR (0x0 << 3)
1758 #define RT5645_GP2_P_INV (0x1 << 3)
1759 #define RT5645_GP1_PF_MASK (0x1 << 2)
1760 #define RT5645_GP1_PF_SFT 2
1761 #define RT5645_GP1_PF_IN (0x0 << 2)
1762 #define RT5645_GP1_PF_OUT (0x1 << 2)
1763 #define RT5645_GP1_OUT_MASK (0x1 << 1)
1764 #define RT5645_GP1_OUT_SFT 1
1765 #define RT5645_GP1_OUT_LO (0x0 << 1)
1766 #define RT5645_GP1_OUT_HI (0x1 << 1)
1767 #define RT5645_GP1_P_MASK (0x1)
1768 #define RT5645_GP1_P_SFT 0
1769 #define RT5645_GP1_P_NOR (0x0)
1770 #define RT5645_GP1_P_INV (0x1)
1771
1772
1773 #define RT5645_REG_SEQ_MASK (0xf << 12)
1774 #define RT5645_REG_SEQ_SFT 12
1775 #define RT5645_SEQ1_ST_MASK (0x1 << 11)
1776 #define RT5645_SEQ1_ST_SFT 11
1777 #define RT5645_SEQ1_ST_RUN (0x0 << 11)
1778 #define RT5645_SEQ1_ST_FIN (0x1 << 11)
1779 #define RT5645_SEQ2_ST_MASK (0x1 << 10)
1780 #define RT5645_SEQ2_ST_SFT 10
1781 #define RT5645_SEQ2_ST_RUN (0x0 << 10)
1782 #define RT5645_SEQ2_ST_FIN (0x1 << 10)
1783 #define RT5645_REG_LV_MASK (0x1 << 9)
1784 #define RT5645_REG_LV_SFT 9
1785 #define RT5645_REG_LV_MX (0x0 << 9)
1786 #define RT5645_REG_LV_PR (0x1 << 9)
1787 #define RT5645_SEQ_2_PT_MASK (0x1 << 8)
1788 #define RT5645_SEQ_2_PT_BIT 8
1789 #define RT5645_REG_IDX_MASK (0xff)
1790 #define RT5645_REG_IDX_SFT 0
1791
1792
1793 #define RT5645_REG_DAT_MASK (0xffff)
1794 #define RT5645_REG_DAT_SFT 0
1795
1796
1797 #define RT5645_SEQ_DLY_MASK (0xff << 8)
1798 #define RT5645_SEQ_DLY_SFT 8
1799 #define RT5645_PROG_MASK (0x1 << 7)
1800 #define RT5645_PROG_SFT 7
1801 #define RT5645_PROG_DIS (0x0 << 7)
1802 #define RT5645_PROG_EN (0x1 << 7)
1803 #define RT5645_SEQ1_PT_RUN (0x1 << 6)
1804 #define RT5645_SEQ1_PT_RUN_BIT 6
1805 #define RT5645_SEQ2_PT_RUN (0x1 << 5)
1806 #define RT5645_SEQ2_PT_RUN_BIT 5
1807
1808
1809 #define RT5645_SEQ1_START_MASK (0xf << 8)
1810 #define RT5645_SEQ1_START_SFT 8
1811 #define RT5645_SEQ1_END_MASK (0xf)
1812 #define RT5645_SEQ1_END_SFT 0
1813
1814
1815 #define RT5645_SEQ2_START_MASK (0xf << 8)
1816 #define RT5645_SEQ2_START_SFT 8
1817 #define RT5645_SEQ2_END_MASK (0xf)
1818 #define RT5645_SEQ2_END_SFT 0
1819
1820
1821 #define RT5645_SCB_KEY_MASK (0xff)
1822 #define RT5645_SCB_KEY_SFT 0
1823
1824
1825 #define RT5645_SCB_SWAP_MASK (0x1 << 15)
1826 #define RT5645_SCB_SWAP_SFT 15
1827 #define RT5645_SCB_SWAP_DIS (0x0 << 15)
1828 #define RT5645_SCB_SWAP_EN (0x1 << 15)
1829 #define RT5645_SCB_MASK (0x1 << 14)
1830 #define RT5645_SCB_SFT 14
1831 #define RT5645_SCB_DIS (0x0 << 14)
1832 #define RT5645_SCB_EN (0x1 << 14)
1833
1834
1835 #define RT5645_BB_MASK (0x1 << 15)
1836 #define RT5645_BB_SFT 15
1837 #define RT5645_BB_DIS (0x0 << 15)
1838 #define RT5645_BB_EN (0x1 << 15)
1839 #define RT5645_BB_CT_MASK (0x7 << 12)
1840 #define RT5645_BB_CT_SFT 12
1841 #define RT5645_BB_CT_A (0x0 << 12)
1842 #define RT5645_BB_CT_B (0x1 << 12)
1843 #define RT5645_BB_CT_C (0x2 << 12)
1844 #define RT5645_BB_CT_D (0x3 << 12)
1845 #define RT5645_M_BB_L_MASK (0x1 << 9)
1846 #define RT5645_M_BB_L_SFT 9
1847 #define RT5645_M_BB_R_MASK (0x1 << 8)
1848 #define RT5645_M_BB_R_SFT 8
1849 #define RT5645_M_BB_HPF_L_MASK (0x1 << 7)
1850 #define RT5645_M_BB_HPF_L_SFT 7
1851 #define RT5645_M_BB_HPF_R_MASK (0x1 << 6)
1852 #define RT5645_M_BB_HPF_R_SFT 6
1853 #define RT5645_G_BB_BST_MASK (0x3f)
1854 #define RT5645_G_BB_BST_SFT 0
1855 #define RT5645_G_BB_BST_25DB 0x14
1856
1857
1858 #define RT5645_M_MP3_L_MASK (0x1 << 15)
1859 #define RT5645_M_MP3_L_SFT 15
1860 #define RT5645_M_MP3_R_MASK (0x1 << 14)
1861 #define RT5645_M_MP3_R_SFT 14
1862 #define RT5645_M_MP3_MASK (0x1 << 13)
1863 #define RT5645_M_MP3_SFT 13
1864 #define RT5645_M_MP3_DIS (0x0 << 13)
1865 #define RT5645_M_MP3_EN (0x1 << 13)
1866 #define RT5645_EG_MP3_MASK (0x1f << 8)
1867 #define RT5645_EG_MP3_SFT 8
1868 #define RT5645_MP3_HLP_MASK (0x1 << 7)
1869 #define RT5645_MP3_HLP_SFT 7
1870 #define RT5645_MP3_HLP_DIS (0x0 << 7)
1871 #define RT5645_MP3_HLP_EN (0x1 << 7)
1872 #define RT5645_M_MP3_ORG_L_MASK (0x1 << 6)
1873 #define RT5645_M_MP3_ORG_L_SFT 6
1874 #define RT5645_M_MP3_ORG_R_MASK (0x1 << 5)
1875 #define RT5645_M_MP3_ORG_R_SFT 5
1876
1877
1878 #define RT5645_MP3_WT_MASK (0x1 << 13)
1879 #define RT5645_MP3_WT_SFT 13
1880 #define RT5645_MP3_WT_1_4 (0x0 << 13)
1881 #define RT5645_MP3_WT_1_2 (0x1 << 13)
1882 #define RT5645_OG_MP3_MASK (0x1f << 8)
1883 #define RT5645_OG_MP3_SFT 8
1884 #define RT5645_HG_MP3_MASK (0x3f)
1885 #define RT5645_HG_MP3_SFT 0
1886
1887
1888 #define RT5645_3D_CF_MASK (0x1 << 15)
1889 #define RT5645_3D_CF_SFT 15
1890 #define RT5645_3D_CF_DIS (0x0 << 15)
1891 #define RT5645_3D_CF_EN (0x1 << 15)
1892 #define RT5645_3D_HP_MASK (0x1 << 14)
1893 #define RT5645_3D_HP_SFT 14
1894 #define RT5645_3D_HP_DIS (0x0 << 14)
1895 #define RT5645_3D_HP_EN (0x1 << 14)
1896 #define RT5645_3D_BT_MASK (0x1 << 13)
1897 #define RT5645_3D_BT_SFT 13
1898 #define RT5645_3D_BT_DIS (0x0 << 13)
1899 #define RT5645_3D_BT_EN (0x1 << 13)
1900 #define RT5645_3D_1F_MIX_MASK (0x3 << 11)
1901 #define RT5645_3D_1F_MIX_SFT 11
1902 #define RT5645_3D_HP_M_MASK (0x1 << 10)
1903 #define RT5645_3D_HP_M_SFT 10
1904 #define RT5645_3D_HP_M_SUR (0x0 << 10)
1905 #define RT5645_3D_HP_M_FRO (0x1 << 10)
1906 #define RT5645_M_3D_HRTF_MASK (0x1 << 9)
1907 #define RT5645_M_3D_HRTF_SFT 9
1908 #define RT5645_M_3D_D2H_MASK (0x1 << 8)
1909 #define RT5645_M_3D_D2H_SFT 8
1910 #define RT5645_M_3D_D2R_MASK (0x1 << 7)
1911 #define RT5645_M_3D_D2R_SFT 7
1912 #define RT5645_M_3D_REVB_MASK (0x1 << 6)
1913 #define RT5645_M_3D_REVB_SFT 6
1914
1915
1916 #define RT5645_2ND_HPF_MASK (0x1 << 15)
1917 #define RT5645_2ND_HPF_SFT 15
1918 #define RT5645_2ND_HPF_DIS (0x0 << 15)
1919 #define RT5645_2ND_HPF_EN (0x1 << 15)
1920 #define RT5645_HPF_CF_L_MASK (0x7 << 12)
1921 #define RT5645_HPF_CF_L_SFT 12
1922 #define RT5645_1ST_HPF_MASK (0x1 << 11)
1923 #define RT5645_1ST_HPF_SFT 11
1924 #define RT5645_1ST_HPF_DIS (0x0 << 11)
1925 #define RT5645_1ST_HPF_EN (0x1 << 11)
1926 #define RT5645_HPF_CF_R_MASK (0x7 << 8)
1927 #define RT5645_HPF_CF_R_SFT 8
1928 #define RT5645_ZD_T_MASK (0x3 << 6)
1929 #define RT5645_ZD_T_SFT 6
1930 #define RT5645_ZD_F_MASK (0x3 << 4)
1931 #define RT5645_ZD_F_SFT 4
1932 #define RT5645_ZD_F_IM (0x0 << 4)
1933 #define RT5645_ZD_F_ZC_IM (0x1 << 4)
1934 #define RT5645_ZD_F_ZC_IOD (0x2 << 4)
1935 #define RT5645_ZD_F_UN (0x3 << 4)
1936
1937
1938 #define RT5645_SI_DAC_MASK (0x1 << 11)
1939 #define RT5645_SI_DAC_SFT 11
1940 #define RT5645_SI_DAC_AUTO (0x0 << 11)
1941 #define RT5645_SI_DAC_TEST (0x1 << 11)
1942 #define RT5645_DC_CAL_M_MASK (0x1 << 10)
1943 #define RT5645_DC_CAL_M_SFT 10
1944 #define RT5645_DC_CAL_M_CAL (0x0 << 10)
1945 #define RT5645_DC_CAL_M_NOR (0x1 << 10)
1946 #define RT5645_DC_CAL_MASK (0x1 << 9)
1947 #define RT5645_DC_CAL_SFT 9
1948 #define RT5645_DC_CAL_DIS (0x0 << 9)
1949 #define RT5645_DC_CAL_EN (0x1 << 9)
1950 #define RT5645_HPD_RCV_MASK (0x7 << 6)
1951 #define RT5645_HPD_RCV_SFT 6
1952 #define RT5645_HPD_PS_MASK (0x1 << 5)
1953 #define RT5645_HPD_PS_SFT 5
1954 #define RT5645_HPD_PS_DIS (0x0 << 5)
1955 #define RT5645_HPD_PS_EN (0x1 << 5)
1956 #define RT5645_CAL_M_MASK (0x1 << 4)
1957 #define RT5645_CAL_M_SFT 4
1958 #define RT5645_CAL_M_DEP (0x0 << 4)
1959 #define RT5645_CAL_M_CAL (0x1 << 4)
1960 #define RT5645_CAL_MASK (0x1 << 3)
1961 #define RT5645_CAL_SFT 3
1962 #define RT5645_CAL_DIS (0x0 << 3)
1963 #define RT5645_CAL_EN (0x1 << 3)
1964 #define RT5645_CAL_TEST_MASK (0x1 << 2)
1965 #define RT5645_CAL_TEST_SFT 2
1966 #define RT5645_CAL_TEST_DIS (0x0 << 2)
1967 #define RT5645_CAL_TEST_EN (0x1 << 2)
1968 #define RT5645_CAL_P_MASK (0x3)
1969 #define RT5645_CAL_P_SFT 0
1970 #define RT5645_CAL_P_NONE (0x0)
1971 #define RT5645_CAL_P_CAL (0x1)
1972 #define RT5645_CAL_P_DAC_CAL (0x2)
1973
1974
1975 #define RT5645_SV_MASK (0x1 << 15)
1976 #define RT5645_SV_SFT 15
1977 #define RT5645_SV_DIS (0x0 << 15)
1978 #define RT5645_SV_EN (0x1 << 15)
1979 #define RT5645_SPO_SV_MASK (0x1 << 14)
1980 #define RT5645_SPO_SV_SFT 14
1981 #define RT5645_SPO_SV_DIS (0x0 << 14)
1982 #define RT5645_SPO_SV_EN (0x1 << 14)
1983 #define RT5645_OUT_SV_MASK (0x1 << 13)
1984 #define RT5645_OUT_SV_SFT 13
1985 #define RT5645_OUT_SV_DIS (0x0 << 13)
1986 #define RT5645_OUT_SV_EN (0x1 << 13)
1987 #define RT5645_HP_SV_MASK (0x1 << 12)
1988 #define RT5645_HP_SV_SFT 12
1989 #define RT5645_HP_SV_DIS (0x0 << 12)
1990 #define RT5645_HP_SV_EN (0x1 << 12)
1991 #define RT5645_ZCD_DIG_MASK (0x1 << 11)
1992 #define RT5645_ZCD_DIG_SFT 11
1993 #define RT5645_ZCD_DIG_DIS (0x0 << 11)
1994 #define RT5645_ZCD_DIG_EN (0x1 << 11)
1995 #define RT5645_ZCD_MASK (0x1 << 10)
1996 #define RT5645_ZCD_SFT 10
1997 #define RT5645_ZCD_PD (0x0 << 10)
1998 #define RT5645_ZCD_PU (0x1 << 10)
1999 #define RT5645_M_ZCD_MASK (0x3f << 4)
2000 #define RT5645_M_ZCD_SFT 4
2001 #define RT5645_M_ZCD_RM_L (0x1 << 9)
2002 #define RT5645_M_ZCD_RM_R (0x1 << 8)
2003 #define RT5645_M_ZCD_SM_L (0x1 << 7)
2004 #define RT5645_M_ZCD_SM_R (0x1 << 6)
2005 #define RT5645_M_ZCD_OM_L (0x1 << 5)
2006 #define RT5645_M_ZCD_OM_R (0x1 << 4)
2007 #define RT5645_SV_DLY_MASK (0xf)
2008 #define RT5645_SV_DLY_SFT 0
2009
2010
2011 #define RT5645_ZCD_HP_MASK (0x1 << 15)
2012 #define RT5645_ZCD_HP_SFT 15
2013 #define RT5645_ZCD_HP_DIS (0x0 << 15)
2014 #define RT5645_ZCD_HP_EN (0x1 << 15)
2015
2016
2017
2018
2019 #define RT5645_DA1_ZDET_SFT 6
2020
2021
2022 #define RT5645_3D_SPK_MASK (0x1 << 15)
2023 #define RT5645_3D_SPK_SFT 15
2024 #define RT5645_3D_SPK_DIS (0x0 << 15)
2025 #define RT5645_3D_SPK_EN (0x1 << 15)
2026 #define RT5645_3D_SPK_M_MASK (0x3 << 13)
2027 #define RT5645_3D_SPK_M_SFT 13
2028 #define RT5645_3D_SPK_CG_MASK (0x1f << 8)
2029 #define RT5645_3D_SPK_CG_SFT 8
2030 #define RT5645_3D_SPK_SG_MASK (0x1f)
2031 #define RT5645_3D_SPK_SG_SFT 0
2032
2033
2034 #define RT5645_WND_MASK (0x1 << 15)
2035 #define RT5645_WND_SFT 15
2036 #define RT5645_WND_DIS (0x0 << 15)
2037 #define RT5645_WND_EN (0x1 << 15)
2038
2039
2040 #define RT5645_WND_FC_NW_MASK (0x3f << 10)
2041 #define RT5645_WND_FC_NW_SFT 10
2042 #define RT5645_WND_FC_WK_MASK (0x3f << 4)
2043 #define RT5645_WND_FC_WK_SFT 4
2044
2045
2046 #define RT5645_HPF_FC_MASK (0x3f << 6)
2047 #define RT5645_HPF_FC_SFT 6
2048 #define RT5645_WND_FC_ST_MASK (0x3f)
2049 #define RT5645_WND_FC_ST_SFT 0
2050
2051
2052 #define RT5645_WND_TH_LO_MASK (0x3ff)
2053 #define RT5645_WND_TH_LO_SFT 0
2054
2055
2056 #define RT5645_WND_TH_HI_MASK (0x3ff)
2057 #define RT5645_WND_TH_HI_SFT 0
2058
2059
2060 #define RT5645_WND_WIND_MASK (0x1 << 13)
2061 #define RT5645_WND_WIND_SFT 13
2062 #define RT5645_WND_STRONG_MASK (0x1 << 12)
2063 #define RT5645_WND_STRONG_SFT 12
2064 enum {
2065 RT5645_NO_WIND,
2066 RT5645_BREEZE,
2067 RT5645_STORM,
2068 };
2069
2070
2071 #define RT5645_DP_ATT_MASK (0x3 << 14)
2072 #define RT5645_DP_ATT_SFT 14
2073 #define RT5645_DP_SPK_MASK (0x1 << 10)
2074 #define RT5645_DP_SPK_SFT 10
2075 #define RT5645_DP_SPK_DIS (0x0 << 10)
2076 #define RT5645_DP_SPK_EN (0x1 << 10)
2077
2078
2079 #define RT5645_EQ_PRE_VOL_MASK (0xffff)
2080 #define RT5645_EQ_PRE_VOL_SFT 0
2081
2082
2083 #define RT5645_EQ_PST_VOL_MASK (0xffff)
2084 #define RT5645_EQ_PST_VOL_SFT 0
2085
2086
2087 #define RT5645_CMP_MIC_IN_DET_MASK (0x7 << 12)
2088 #define RT5645_JD_CBJ_EN (0x1 << 7)
2089 #define RT5645_JD_CBJ_POL (0x1 << 6)
2090 #define RT5645_JD_TRI_CBJ_SEL_MASK (0x7 << 3)
2091 #define RT5645_JD_TRI_CBJ_SEL_SFT (3)
2092 #define RT5645_JD_TRI_HPO_SEL_MASK (0x7)
2093 #define RT5645_JD_TRI_HPO_SEL_SFT (0)
2094 #define RT5645_JD_F_GPIO_JD1 (0x0)
2095 #define RT5645_JD_F_JD1_1 (0x1)
2096 #define RT5645_JD_F_JD1_2 (0x2)
2097 #define RT5645_JD_F_JD2 (0x3)
2098 #define RT5645_JD_F_JD3 (0x4)
2099 #define RT5645_JD_F_GPIO_JD2 (0x5)
2100 #define RT5645_JD_F_MX0B_12 (0x6)
2101
2102
2103 #define RT5645_RST_DSP (0x1 << 13)
2104 #define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12)
2105 #define RT5645_IF1_ADC1_IN1_SFT 12
2106 #define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11)
2107 #define RT5645_IF1_ADC1_IN2_SFT 11
2108 #define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10)
2109 #define RT5645_IF1_ADC2_IN1_SFT 10
2110 #define RT5645_DIG_GATE_CTRL 0x1
2111
2112
2113 #define RT5645_RXDC_SRC_MASK (0x1 << 7)
2114 #define RT5645_RXDC_SRC_STO (0x0 << 7)
2115 #define RT5645_RXDC_SRC_MONO (0x1 << 7)
2116 #define RT5645_RXDC_SRC_SFT (7)
2117 #define RT5645_MICBIAS1_POW_CTRL_SEL_MASK (0x1 << 5)
2118 #define RT5645_MICBIAS1_POW_CTRL_SEL_A (0x0 << 5)
2119 #define RT5645_MICBIAS1_POW_CTRL_SEL_M (0x1 << 5)
2120 #define RT5645_MICBIAS2_POW_CTRL_SEL_MASK (0x1 << 4)
2121 #define RT5645_MICBIAS2_POW_CTRL_SEL_A (0x0 << 4)
2122 #define RT5645_MICBIAS2_POW_CTRL_SEL_M (0x1 << 4)
2123 #define RT5645_RXDP2_SEL_MASK (0x1 << 3)
2124 #define RT5645_RXDP2_SEL_IF2 (0x0 << 3)
2125 #define RT5645_RXDP2_SEL_ADC (0x1 << 3)
2126 #define RT5645_RXDP2_SEL_SFT (3)
2127
2128
2129 #define RT5645_JD_PSV_MODE (0x1 << 12)
2130 #define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11)
2131 #define RT5645_DET_CLK_MASK (0x3 << 9)
2132 #define RT5645_DET_CLK_DIS (0x0 << 9)
2133 #define RT5645_DET_CLK_MODE1 (0x1 << 9)
2134 #define RT5645_DET_CLK_MODE2 (0x2 << 9)
2135 #define RT5645_MICINDET_MANU (0x1 << 7)
2136 #define RT5645_RING2_SLEEVE_GND (0x1 << 5)
2137
2138
2139 #define RT5645_VER_C 0x2
2140 #define RT5645_VER_D 0x3
2141
2142
2143
2144 #define RT5645_VOL_RSCL_MAX 0x27
2145 #define RT5645_VOL_RSCL_RANGE 0x1F
2146
2147 #define RT5645_REG_DISP_LEN 23
2148
2149
2150
2151 enum {
2152 RT5645_SCLK_S_MCLK,
2153 RT5645_SCLK_S_PLL1,
2154 RT5645_SCLK_S_RCCLK,
2155 };
2156
2157
2158 enum {
2159 RT5645_PLL1_S_MCLK,
2160 RT5645_PLL1_S_BCLK1,
2161 RT5645_PLL1_S_BCLK2,
2162 };
2163
2164 enum {
2165 RT5645_AIF1,
2166 RT5645_AIF2,
2167 RT5645_AIFS,
2168 };
2169
2170 enum {
2171 RT5645_DMIC1_DISABLE,
2172 RT5645_DMIC_DATA_IN2P,
2173 RT5645_DMIC_DATA_GPIO6,
2174 RT5645_DMIC_DATA_GPIO10,
2175 RT5645_DMIC_DATA_GPIO12,
2176 };
2177
2178 enum {
2179 RT5645_DMIC2_DISABLE,
2180 RT5645_DMIC_DATA_IN2N,
2181 RT5645_DMIC_DATA_GPIO5,
2182 RT5645_DMIC_DATA_GPIO11,
2183 };
2184
2185 enum {
2186 CODEC_TYPE_RT5645,
2187 CODEC_TYPE_RT5650,
2188 };
2189
2190
2191 enum {
2192 RT5645_DA_STEREO_FILTER = 0x1,
2193 RT5645_DA_MONO_L_FILTER = (0x1 << 1),
2194 RT5645_DA_MONO_R_FILTER = (0x1 << 2),
2195 RT5645_AD_STEREO_FILTER = (0x1 << 3),
2196 RT5645_AD_MONO_L_FILTER = (0x1 << 4),
2197 RT5645_AD_MONO_R_FILTER = (0x1 << 5),
2198 };
2199
2200 int rt5645_sel_asrc_clk_src(struct snd_soc_component *component,
2201 unsigned int filter_mask, unsigned int clk_src);
2202
2203 int rt5645_set_jack_detect(struct snd_soc_component *component,
2204 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
2205 struct snd_soc_jack *btn_jack);
2206 #endif