This source file includes following definitions.
- wm8962_volatile_register
- wm8962_readable_register
- wm8962_reset
- wm8962_dsp2_write_config
- wm8962_dsp2_set_enable
- wm8962_dsp2_start
- wm8962_dsp2_stop
- wm8962_dsp2_ena_info
- wm8962_dsp2_ena_get
- wm8962_dsp2_ena_put
- wm8962_put_hp_sw
- wm8962_put_spk_sw
- cp_event
- hp_event
- out_pga_event
- dsp2_event
- wm8962_add_widgets
- wm8962_configure_bclk
- wm8962_set_bias_level
- wm8962_hw_params
- wm8962_set_dai_sysclk
- wm8962_set_dai_fmt
- fll_factors
- wm8962_set_fll
- wm8962_mute
- wm8962_mic_work
- wm8962_irq
- wm8962_mic_detect
- wm8962_beep_work
- wm8962_beep_event
- wm8962_beep_set
- wm8962_init_beep
- wm8962_free_beep
- wm8962_set_gpio_mode
- wm8962_gpio_request
- wm8962_gpio_set
- wm8962_gpio_direction_out
- wm8962_init_gpio
- wm8962_free_gpio
- wm8962_init_gpio
- wm8962_free_gpio
- wm8962_probe
- wm8962_remove
- wm8962_set_pdata_from_of
- wm8962_i2c_probe
- wm8962_i2c_remove
- wm8962_runtime_resume
- wm8962_runtime_suspend
1
2
3
4
5
6
7
8
9
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/pm.h>
16 #include <linux/gcd.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/i2c.h>
19 #include <linux/input.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/workqueue.h>
25 #include <linux/mutex.h>
26 #include <sound/core.h>
27 #include <sound/jack.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <sound/wm8962.h>
34 #include <trace/events/asoc.h>
35
36 #include "wm8962.h"
37
38 #define WM8962_NUM_SUPPLIES 8
39 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
40 "DCVDD",
41 "DBVDD",
42 "AVDD",
43 "CPVDD",
44 "MICVDD",
45 "PLLVDD",
46 "SPKVDD1",
47 "SPKVDD2",
48 };
49
50
51 struct wm8962_priv {
52 struct wm8962_pdata pdata;
53 struct regmap *regmap;
54 struct snd_soc_component *component;
55
56 int sysclk;
57 int sysclk_rate;
58
59 int bclk;
60 int lrclk;
61
62 struct completion fll_lock;
63 int fll_src;
64 int fll_fref;
65 int fll_fout;
66
67 struct mutex dsp2_ena_lock;
68 u16 dsp2_ena;
69
70 struct delayed_work mic_work;
71 struct snd_soc_jack *jack;
72
73 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
74 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
75
76 struct input_dev *beep;
77 struct work_struct beep_work;
78 int beep_rate;
79
80 #ifdef CONFIG_GPIOLIB
81 struct gpio_chip gpio_chip;
82 #endif
83
84 int irq;
85 };
86
87
88
89
90
91 #define WM8962_REGULATOR_EVENT(n) \
92 static int wm8962_regulator_event_##n(struct notifier_block *nb, \
93 unsigned long event, void *data) \
94 { \
95 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
96 disable_nb[n]); \
97 if (event & REGULATOR_EVENT_DISABLE) { \
98 regcache_mark_dirty(wm8962->regmap); \
99 } \
100 return 0; \
101 }
102
103 WM8962_REGULATOR_EVENT(0)
104 WM8962_REGULATOR_EVENT(1)
105 WM8962_REGULATOR_EVENT(2)
106 WM8962_REGULATOR_EVENT(3)
107 WM8962_REGULATOR_EVENT(4)
108 WM8962_REGULATOR_EVENT(5)
109 WM8962_REGULATOR_EVENT(6)
110 WM8962_REGULATOR_EVENT(7)
111
112 static const struct reg_default wm8962_reg[] = {
113 { 0, 0x009F },
114 { 1, 0x049F },
115 { 2, 0x0000 },
116 { 3, 0x0000 },
117
118 { 5, 0x0018 },
119 { 6, 0x2008 },
120 { 7, 0x000A },
121
122 { 9, 0x0300 },
123 { 10, 0x00C0 },
124 { 11, 0x00C0 },
125
126 { 14, 0x0040 },
127 { 15, 0x6243 },
128
129 { 17, 0x007B },
130 { 18, 0x0000 },
131 { 19, 0x1C32 },
132 { 20, 0x3200 },
133 { 21, 0x00C0 },
134 { 22, 0x00C0 },
135 { 23, 0x0160 },
136 { 24, 0x0000 },
137 { 25, 0x0000 },
138 { 26, 0x0000 },
139 { 27, 0x0010 },
140 { 28, 0x0000 },
141
142 { 30, 0x005E },
143 { 31, 0x0000 },
144 { 32, 0x0145 },
145 { 33, 0x0145 },
146 { 34, 0x0009 },
147 { 35, 0x0003 },
148 { 37, 0x0008 },
149 { 38, 0x0008 },
150
151 { 40, 0x0000 },
152 { 41, 0x0000 },
153
154 { 49, 0x0010 },
155 { 51, 0x0003 },
156
157 { 56, 0x0506 },
158 { 57, 0x0000 },
159 { 58, 0x0000 },
160
161 { 60, 0x0300 },
162 { 61, 0x0300 },
163
164 { 64, 0x0810 },
165
166 { 68, 0x001B },
167 { 69, 0x0000 },
168
169 { 71, 0x01FB },
170 { 72, 0x0000 },
171
172 { 82, 0x0004 },
173
174 { 87, 0x0000 },
175
176 { 90, 0x0000 },
177
178 { 93, 0x0000 },
179 { 94, 0x0000 },
180
181 { 99, 0x0000 },
182 { 100, 0x0000 },
183 { 101, 0x0000 },
184 { 102, 0x013F },
185 { 103, 0x013F },
186
187 { 105, 0x0000 },
188 { 106, 0x0000 },
189 { 107, 0x013F },
190 { 108, 0x013F },
191 { 109, 0x0003 },
192 { 110, 0x0002 },
193
194 { 115, 0x0006 },
195 { 116, 0x0026 },
196
197 { 119, 0x0000 },
198
199 { 124, 0x0011 },
200 { 125, 0x004B },
201 { 126, 0x000D },
202 { 127, 0x0000 },
203
204 { 131, 0x0000 },
205
206 { 136, 0x0067 },
207 { 137, 0x001C },
208 { 138, 0x0071 },
209 { 139, 0x00C7 },
210 { 140, 0x0067 },
211 { 141, 0x0048 },
212 { 142, 0x0022 },
213 { 143, 0x0097 },
214
215 { 155, 0x000C },
216 { 156, 0x0039 },
217 { 157, 0x0180 },
218
219 { 159, 0x0032 },
220 { 160, 0x0018 },
221 { 161, 0x007D },
222 { 162, 0x0008 },
223
224 { 252, 0x0005 },
225
226 { 256, 0x0000 },
227 { 257, 0x0000 },
228 { 258, 0x0000 },
229 { 259, 0x0000 },
230 { 260, 0x0000 },
231 { 261, 0x0000 },
232 { 262, 0x0000 },
233
234 { 264, 0x0000 },
235 { 265, 0x0000 },
236
237 { 268, 0x0000 },
238 { 269, 0x0000 },
239 { 270, 0x0000 },
240 { 271, 0x0000 },
241
242 { 276, 0x000C },
243 { 277, 0x0925 },
244 { 278, 0x0000 },
245 { 279, 0x0000 },
246 { 280, 0x0000 },
247
248 { 285, 0x0000 },
249
250 { 335, 0x0004 },
251 { 336, 0x6318 },
252 { 337, 0x6300 },
253 { 338, 0x0FCA },
254 { 339, 0x0400 },
255 { 340, 0x00D8 },
256 { 341, 0x1EB5 },
257 { 342, 0xF145 },
258 { 343, 0x0B75 },
259 { 344, 0x01C5 },
260 { 345, 0x1C58 },
261 { 346, 0xF373 },
262 { 347, 0x0A54 },
263 { 348, 0x0558 },
264 { 349, 0x168E },
265 { 350, 0xF829 },
266 { 351, 0x07AD },
267 { 352, 0x1103 },
268 { 353, 0x0564 },
269 { 354, 0x0559 },
270 { 355, 0x4000 },
271 { 356, 0x6318 },
272 { 357, 0x6300 },
273 { 358, 0x0FCA },
274 { 359, 0x0400 },
275 { 360, 0x00D8 },
276 { 361, 0x1EB5 },
277 { 362, 0xF145 },
278 { 363, 0x0B75 },
279 { 364, 0x01C5 },
280 { 365, 0x1C58 },
281 { 366, 0xF373 },
282 { 367, 0x0A54 },
283 { 368, 0x0558 },
284 { 369, 0x168E },
285 { 370, 0xF829 },
286 { 371, 0x07AD },
287 { 372, 0x1103 },
288 { 373, 0x0564 },
289 { 374, 0x0559 },
290 { 375, 0x4000 },
291
292 { 513, 0x0000 },
293 { 514, 0x0000 },
294
295 { 516, 0x8100 },
296 { 517, 0x8100 },
297
298 { 568, 0x0030 },
299 { 569, 0xFFED },
300
301 { 576, 0x0000 },
302
303 { 584, 0x002D },
304
305 { 586, 0x0000 },
306
307 { 768, 0x1C00 },
308
309 { 8192, 0x0000 },
310
311 { 9216, 0x0030 },
312 { 9217, 0x0000 },
313 { 9218, 0x0000 },
314
315 { 12288, 0x0000 },
316 { 12289, 0x0000 },
317
318 { 13312, 0x0000 },
319 { 13313, 0x0000 },
320
321 { 14336, 0x0000 },
322 { 14337, 0x0000 },
323
324 { 15360, 0x000A },
325
326 { 16384, 0x0000 },
327 { 16385, 0x0000 },
328 { 16386, 0x0000 },
329 { 16387, 0x0000 },
330 { 16388, 0x0000 },
331 { 16389, 0x0000 },
332
333 { 16896, 0x0002 },
334 { 16897, 0xBD12 },
335 { 16898, 0x007C },
336 { 16899, 0x586C },
337 { 16900, 0x0053 },
338 { 16901, 0x8121 },
339 { 16902, 0x003F },
340 { 16903, 0x8BD8 },
341 { 16904, 0x0032 },
342 { 16905, 0xF52D },
343 { 16906, 0x0065 },
344 { 16907, 0xAC8C },
345 { 16908, 0x006B },
346 { 16909, 0xE087 },
347 { 16910, 0x0072 },
348 { 16911, 0x1483 },
349 { 16912, 0x0072 },
350 { 16913, 0x1483 },
351 { 16914, 0x0043 },
352 { 16915, 0x3525 },
353 { 16916, 0x0006 },
354 { 16917, 0x6A4A },
355 { 16918, 0x0043 },
356 { 16919, 0x6079 },
357 { 16920, 0x0008 },
358 { 16921, 0x0000 },
359 { 16922, 0x0001 },
360 { 16923, 0x0000 },
361 { 16924, 0x0059 },
362 { 16925, 0x999A },
363
364 { 17408, 0x0083 },
365 { 17409, 0x98AD },
366
367 { 17920, 0x007F },
368 { 17921, 0xFFFF },
369 { 17922, 0x0000 },
370 { 17923, 0x0000 },
371 { 17924, 0x0000 },
372 { 17925, 0x0000 },
373 { 17926, 0x0000 },
374 { 17927, 0x0000 },
375 { 17928, 0x0000 },
376 { 17929, 0x0000 },
377 { 17930, 0x0000 },
378 { 17931, 0x0000 },
379 { 17932, 0x0000 },
380 { 17933, 0x0000 },
381 { 17934, 0x0000 },
382 { 17935, 0x0000 },
383 { 17936, 0x0000 },
384 { 17937, 0x0000 },
385 { 17938, 0x0000 },
386 { 17939, 0x0000 },
387 { 17940, 0x0000 },
388 { 17941, 0x0000 },
389 { 17942, 0x0000 },
390 { 17943, 0x0000 },
391 { 17944, 0x0000 },
392 { 17945, 0x0000 },
393 { 17946, 0x0000 },
394 { 17947, 0x0000 },
395 { 17948, 0x0000 },
396 { 17949, 0x0000 },
397 { 17950, 0x0000 },
398 { 17951, 0x0000 },
399 { 17952, 0x0000 },
400 { 17953, 0x0000 },
401 { 17954, 0x0000 },
402 { 17955, 0x0000 },
403 { 17956, 0x0000 },
404 { 17957, 0x0000 },
405 { 17958, 0x0000 },
406 { 17959, 0x0000 },
407 { 17960, 0x0000 },
408 { 17961, 0x0000 },
409 { 17962, 0x0000 },
410 { 17963, 0x0000 },
411 { 17964, 0x0000 },
412 { 17965, 0x0000 },
413 { 17966, 0x0000 },
414 { 17967, 0x0000 },
415 { 17968, 0x0000 },
416 { 17969, 0x0000 },
417 { 17970, 0x0000 },
418 { 17971, 0x0000 },
419 { 17972, 0x0000 },
420 { 17973, 0x0000 },
421 { 17974, 0x0000 },
422 { 17975, 0x0000 },
423 { 17976, 0x0000 },
424 { 17977, 0x0000 },
425 { 17978, 0x0000 },
426 { 17979, 0x0000 },
427 { 17980, 0x0000 },
428 { 17981, 0x0000 },
429 { 17982, 0x0000 },
430 { 17983, 0x0000 },
431
432 { 18432, 0x0020 },
433 { 18433, 0x0000 },
434 { 18434, 0x0040 },
435 { 18435, 0x0000 },
436
437 { 18944, 0x007F },
438 { 18945, 0xFFFF },
439 { 18946, 0x0000 },
440 { 18947, 0x0000 },
441 { 18948, 0x0000 },
442 { 18949, 0x0000 },
443 { 18950, 0x0000 },
444 { 18951, 0x0000 },
445 { 18952, 0x0000 },
446 { 18953, 0x0000 },
447 { 18954, 0x0000 },
448 { 18955, 0x0000 },
449 { 18956, 0x0000 },
450 { 18957, 0x0000 },
451 { 18958, 0x0000 },
452 { 18959, 0x0000 },
453 { 18960, 0x0000 },
454 { 18961, 0x0000 },
455 { 18962, 0x0000 },
456 { 18963, 0x0000 },
457 { 18964, 0x0000 },
458 { 18965, 0x0000 },
459 { 18966, 0x0000 },
460 { 18967, 0x0000 },
461 { 18968, 0x0000 },
462 { 18969, 0x0000 },
463 { 18970, 0x0000 },
464 { 18971, 0x0000 },
465 { 18972, 0x0000 },
466 { 18973, 0x0000 },
467 { 18974, 0x0000 },
468 { 18975, 0x0000 },
469 { 18976, 0x0000 },
470 { 18977, 0x0000 },
471 { 18978, 0x0000 },
472 { 18979, 0x0000 },
473 { 18980, 0x0000 },
474 { 18981, 0x0000 },
475 { 18982, 0x0000 },
476 { 18983, 0x0000 },
477 { 18984, 0x0000 },
478 { 18985, 0x0000 },
479 { 18986, 0x0000 },
480 { 18987, 0x0000 },
481 { 18988, 0x0000 },
482 { 18989, 0x0000 },
483 { 18990, 0x0000 },
484 { 18991, 0x0000 },
485 { 18992, 0x0000 },
486 { 18993, 0x0000 },
487 { 18994, 0x0000 },
488 { 18995, 0x0000 },
489 { 18996, 0x0000 },
490 { 18997, 0x0000 },
491 { 18998, 0x0000 },
492 { 18999, 0x0000 },
493 { 19000, 0x0000 },
494 { 19001, 0x0000 },
495 { 19002, 0x0000 },
496 { 19003, 0x0000 },
497 { 19004, 0x0000 },
498 { 19005, 0x0000 },
499 { 19006, 0x0000 },
500 { 19007, 0x0000 },
501
502 { 19456, 0x007F },
503 { 19457, 0xFFFF },
504 { 19458, 0x0000 },
505 { 19459, 0x0000 },
506 { 19460, 0x0000 },
507 { 19461, 0x0000 },
508 { 19462, 0x0000 },
509 { 19463, 0x0000 },
510 { 19464, 0x0000 },
511 { 19465, 0x0000 },
512 { 19466, 0x0000 },
513 { 19467, 0x0000 },
514 { 19468, 0x0000 },
515 { 19469, 0x0000 },
516 { 19470, 0x0000 },
517 { 19471, 0x0000 },
518 { 19472, 0x0000 },
519 { 19473, 0x0000 },
520 { 19474, 0x0000 },
521 { 19475, 0x0000 },
522 { 19476, 0x0000 },
523 { 19477, 0x0000 },
524 { 19478, 0x0000 },
525 { 19479, 0x0000 },
526 { 19480, 0x0000 },
527 { 19481, 0x0000 },
528 { 19482, 0x0000 },
529 { 19483, 0x0000 },
530 { 19484, 0x0000 },
531 { 19485, 0x0000 },
532 { 19486, 0x0000 },
533 { 19487, 0x0000 },
534 { 19488, 0x0000 },
535 { 19489, 0x0000 },
536 { 19490, 0x0000 },
537 { 19491, 0x0000 },
538 { 19492, 0x0000 },
539 { 19493, 0x0000 },
540 { 19494, 0x0000 },
541 { 19495, 0x0000 },
542 { 19496, 0x0000 },
543 { 19497, 0x0000 },
544 { 19498, 0x0000 },
545 { 19499, 0x0000 },
546 { 19500, 0x0000 },
547 { 19501, 0x0000 },
548 { 19502, 0x0000 },
549 { 19503, 0x0000 },
550 { 19504, 0x0000 },
551 { 19505, 0x0000 },
552 { 19506, 0x0000 },
553 { 19507, 0x0000 },
554 { 19508, 0x0000 },
555 { 19509, 0x0000 },
556 { 19510, 0x0000 },
557 { 19511, 0x0000 },
558 { 19512, 0x0000 },
559 { 19513, 0x0000 },
560 { 19514, 0x0000 },
561 { 19515, 0x0000 },
562 { 19516, 0x0000 },
563 { 19517, 0x0000 },
564 { 19518, 0x0000 },
565 { 19519, 0x0000 },
566
567 { 19968, 0x0020 },
568 { 19969, 0x0000 },
569 { 19970, 0x0040 },
570 { 19971, 0x0000 },
571
572 { 20480, 0x007F },
573 { 20481, 0xFFFF },
574 { 20482, 0x0000 },
575 { 20483, 0x0000 },
576 { 20484, 0x0000 },
577 { 20485, 0x0000 },
578 { 20486, 0x0000 },
579 { 20487, 0x0000 },
580 { 20488, 0x0000 },
581 { 20489, 0x0000 },
582 { 20490, 0x0000 },
583 { 20491, 0x0000 },
584 { 20492, 0x0000 },
585 { 20493, 0x0000 },
586 { 20494, 0x0000 },
587 { 20495, 0x0000 },
588 { 20496, 0x0000 },
589 { 20497, 0x0000 },
590 { 20498, 0x0000 },
591 { 20499, 0x0000 },
592 { 20500, 0x0000 },
593 { 20501, 0x0000 },
594 { 20502, 0x0000 },
595 { 20503, 0x0000 },
596 { 20504, 0x0000 },
597 { 20505, 0x0000 },
598 { 20506, 0x0000 },
599 { 20507, 0x0000 },
600 { 20508, 0x0000 },
601 { 20509, 0x0000 },
602 { 20510, 0x0000 },
603 { 20511, 0x0000 },
604 { 20512, 0x0000 },
605 { 20513, 0x0000 },
606 { 20514, 0x0000 },
607 { 20515, 0x0000 },
608 { 20516, 0x0000 },
609 { 20517, 0x0000 },
610 { 20518, 0x0000 },
611 { 20519, 0x0000 },
612 { 20520, 0x0000 },
613 { 20521, 0x0000 },
614 { 20522, 0x0000 },
615 { 20523, 0x0000 },
616 { 20524, 0x0000 },
617 { 20525, 0x0000 },
618 { 20526, 0x0000 },
619 { 20527, 0x0000 },
620 { 20528, 0x0000 },
621 { 20529, 0x0000 },
622 { 20530, 0x0000 },
623 { 20531, 0x0000 },
624 { 20532, 0x0000 },
625 { 20533, 0x0000 },
626 { 20534, 0x0000 },
627 { 20535, 0x0000 },
628 { 20536, 0x0000 },
629 { 20537, 0x0000 },
630 { 20538, 0x0000 },
631 { 20539, 0x0000 },
632 { 20540, 0x0000 },
633 { 20541, 0x0000 },
634 { 20542, 0x0000 },
635 { 20543, 0x0000 },
636
637 { 20992, 0x008C },
638 { 20993, 0x0200 },
639 { 20994, 0x0035 },
640 { 20995, 0x0700 },
641 { 20996, 0x003A },
642 { 20997, 0x4100 },
643 { 20998, 0x008B },
644 { 20999, 0x7D00 },
645 { 21000, 0x003A },
646 { 21001, 0x4100 },
647 { 21002, 0x008C },
648 { 21003, 0xFEE8 },
649 { 21004, 0x0078 },
650 { 21005, 0x0000 },
651 { 21006, 0x003F },
652 { 21007, 0xB260 },
653 { 21008, 0x002D },
654 { 21009, 0x1818 },
655 { 21010, 0x0020 },
656 { 21011, 0x0000 },
657 { 21012, 0x00F1 },
658 { 21013, 0x8340 },
659 { 21014, 0x00FB },
660 { 21015, 0x8300 },
661 { 21016, 0x00EE },
662 { 21017, 0xAEC0 },
663 { 21018, 0x00FB },
664 { 21019, 0xAC40 },
665 { 21020, 0x00F1 },
666 { 21021, 0x7F80 },
667 { 21022, 0x00F4 },
668 { 21023, 0x3B40 },
669 { 21024, 0x00F5 },
670 { 21025, 0xFB00 },
671 { 21026, 0x00EA },
672 { 21027, 0x10C0 },
673 { 21028, 0x00FC },
674 { 21029, 0xC580 },
675 { 21030, 0x00E2 },
676 { 21031, 0x75C0 },
677 { 21032, 0x0004 },
678 { 21033, 0xB480 },
679 { 21034, 0x00D4 },
680 { 21035, 0xF980 },
681 { 21036, 0x0004 },
682 { 21037, 0x9140 },
683 { 21038, 0x00D8 },
684 { 21039, 0xA480 },
685 { 21040, 0x0002 },
686 { 21041, 0x3DC0 },
687 { 21042, 0x00CF },
688 { 21043, 0x7A80 },
689 { 21044, 0x00DC },
690 { 21045, 0x0600 },
691 { 21046, 0x00F2 },
692 { 21047, 0xDAC0 },
693 { 21048, 0x00BA },
694 { 21049, 0xF340 },
695 { 21050, 0x000A },
696 { 21051, 0x7940 },
697 { 21052, 0x001C },
698 { 21053, 0x0680 },
699 { 21054, 0x00FD },
700 { 21055, 0x2D00 },
701 { 21056, 0x001C },
702 { 21057, 0xE840 },
703 { 21058, 0x000D },
704 { 21059, 0xDC40 },
705 { 21060, 0x00FC },
706 { 21061, 0x9D00 },
707 { 21062, 0x0009 },
708 { 21063, 0x5580 },
709 { 21064, 0x00FE },
710 { 21065, 0x7E80 },
711 { 21066, 0x000E },
712 { 21067, 0xAB40 },
713 { 21068, 0x00F9 },
714 { 21069, 0x9880 },
715 { 21070, 0x0009 },
716 { 21071, 0x87C0 },
717 { 21072, 0x00FD },
718 { 21073, 0x2C40 },
719 { 21074, 0x0009 },
720 { 21075, 0x4800 },
721 { 21076, 0x0003 },
722 { 21077, 0x5F40 },
723 { 21078, 0x0000 },
724 { 21079, 0x8700 },
725 { 21080, 0x00FA },
726 { 21081, 0xE4C0 },
727 { 21082, 0x0000 },
728 { 21083, 0x0B40 },
729 { 21084, 0x0004 },
730 { 21085, 0xE180 },
731 { 21086, 0x0001 },
732 { 21087, 0x1F40 },
733 { 21088, 0x00F8 },
734 { 21089, 0xB000 },
735 { 21090, 0x00FB },
736 { 21091, 0xCBC0 },
737 { 21092, 0x0004 },
738 { 21093, 0xF380 },
739 { 21094, 0x0007 },
740 { 21095, 0xDF40 },
741 { 21096, 0x00FF },
742 { 21097, 0x0700 },
743 { 21098, 0x00EF },
744 { 21099, 0xD700 },
745 { 21100, 0x00FB },
746 { 21101, 0xAF40 },
747 { 21102, 0x0010 },
748 { 21103, 0x8A80 },
749 { 21104, 0x0011 },
750 { 21105, 0x07C0 },
751 { 21106, 0x00E0 },
752 { 21107, 0x0800 },
753 { 21108, 0x00D2 },
754 { 21109, 0x7600 },
755 { 21110, 0x0020 },
756 { 21111, 0xCF40 },
757 { 21112, 0x0030 },
758 { 21113, 0x2340 },
759 { 21114, 0x00FD },
760 { 21115, 0x69C0 },
761 { 21116, 0x0028 },
762 { 21117, 0x3500 },
763 { 21118, 0x0006 },
764 { 21119, 0x3300 },
765 { 21120, 0x00D9 },
766 { 21121, 0xF6C0 },
767 { 21122, 0x00F3 },
768 { 21123, 0x3340 },
769 { 21124, 0x000F },
770 { 21125, 0x4200 },
771 { 21126, 0x0004 },
772 { 21127, 0x0C80 },
773 { 21128, 0x00FB },
774 { 21129, 0x3F80 },
775 { 21130, 0x00F7 },
776 { 21131, 0x57C0 },
777 { 21132, 0x0003 },
778 { 21133, 0x5400 },
779 { 21134, 0x0000 },
780 { 21135, 0xC6C0 },
781 { 21136, 0x0003 },
782 { 21137, 0x12C0 },
783 { 21138, 0x00FD },
784 { 21139, 0x8580 },
785 };
786
787 static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
788 {
789 switch (reg) {
790 case WM8962_CLOCKING1:
791 case WM8962_CLOCKING2:
792 case WM8962_SOFTWARE_RESET:
793 case WM8962_THERMAL_SHUTDOWN_STATUS:
794 case WM8962_ADDITIONAL_CONTROL_4:
795 case WM8962_DC_SERVO_6:
796 case WM8962_INTERRUPT_STATUS_1:
797 case WM8962_INTERRUPT_STATUS_2:
798 case WM8962_DSP2_EXECCONTROL:
799 return true;
800 default:
801 return false;
802 }
803 }
804
805 static bool wm8962_readable_register(struct device *dev, unsigned int reg)
806 {
807 switch (reg) {
808 case WM8962_LEFT_INPUT_VOLUME:
809 case WM8962_RIGHT_INPUT_VOLUME:
810 case WM8962_HPOUTL_VOLUME:
811 case WM8962_HPOUTR_VOLUME:
812 case WM8962_CLOCKING1:
813 case WM8962_ADC_DAC_CONTROL_1:
814 case WM8962_ADC_DAC_CONTROL_2:
815 case WM8962_AUDIO_INTERFACE_0:
816 case WM8962_CLOCKING2:
817 case WM8962_AUDIO_INTERFACE_1:
818 case WM8962_LEFT_DAC_VOLUME:
819 case WM8962_RIGHT_DAC_VOLUME:
820 case WM8962_AUDIO_INTERFACE_2:
821 case WM8962_SOFTWARE_RESET:
822 case WM8962_ALC1:
823 case WM8962_ALC2:
824 case WM8962_ALC3:
825 case WM8962_NOISE_GATE:
826 case WM8962_LEFT_ADC_VOLUME:
827 case WM8962_RIGHT_ADC_VOLUME:
828 case WM8962_ADDITIONAL_CONTROL_1:
829 case WM8962_ADDITIONAL_CONTROL_2:
830 case WM8962_PWR_MGMT_1:
831 case WM8962_PWR_MGMT_2:
832 case WM8962_ADDITIONAL_CONTROL_3:
833 case WM8962_ANTI_POP:
834 case WM8962_CLOCKING_3:
835 case WM8962_INPUT_MIXER_CONTROL_1:
836 case WM8962_LEFT_INPUT_MIXER_VOLUME:
837 case WM8962_RIGHT_INPUT_MIXER_VOLUME:
838 case WM8962_INPUT_MIXER_CONTROL_2:
839 case WM8962_INPUT_BIAS_CONTROL:
840 case WM8962_LEFT_INPUT_PGA_CONTROL:
841 case WM8962_RIGHT_INPUT_PGA_CONTROL:
842 case WM8962_SPKOUTL_VOLUME:
843 case WM8962_SPKOUTR_VOLUME:
844 case WM8962_THERMAL_SHUTDOWN_STATUS:
845 case WM8962_ADDITIONAL_CONTROL_4:
846 case WM8962_CLASS_D_CONTROL_1:
847 case WM8962_CLASS_D_CONTROL_2:
848 case WM8962_CLOCKING_4:
849 case WM8962_DAC_DSP_MIXING_1:
850 case WM8962_DAC_DSP_MIXING_2:
851 case WM8962_DC_SERVO_0:
852 case WM8962_DC_SERVO_1:
853 case WM8962_DC_SERVO_4:
854 case WM8962_DC_SERVO_6:
855 case WM8962_ANALOGUE_PGA_BIAS:
856 case WM8962_ANALOGUE_HP_0:
857 case WM8962_ANALOGUE_HP_2:
858 case WM8962_CHARGE_PUMP_1:
859 case WM8962_CHARGE_PUMP_B:
860 case WM8962_WRITE_SEQUENCER_CONTROL_1:
861 case WM8962_WRITE_SEQUENCER_CONTROL_2:
862 case WM8962_WRITE_SEQUENCER_CONTROL_3:
863 case WM8962_CONTROL_INTERFACE:
864 case WM8962_MIXER_ENABLES:
865 case WM8962_HEADPHONE_MIXER_1:
866 case WM8962_HEADPHONE_MIXER_2:
867 case WM8962_HEADPHONE_MIXER_3:
868 case WM8962_HEADPHONE_MIXER_4:
869 case WM8962_SPEAKER_MIXER_1:
870 case WM8962_SPEAKER_MIXER_2:
871 case WM8962_SPEAKER_MIXER_3:
872 case WM8962_SPEAKER_MIXER_4:
873 case WM8962_SPEAKER_MIXER_5:
874 case WM8962_BEEP_GENERATOR_1:
875 case WM8962_OSCILLATOR_TRIM_3:
876 case WM8962_OSCILLATOR_TRIM_4:
877 case WM8962_OSCILLATOR_TRIM_7:
878 case WM8962_ANALOGUE_CLOCKING1:
879 case WM8962_ANALOGUE_CLOCKING2:
880 case WM8962_ANALOGUE_CLOCKING3:
881 case WM8962_PLL_SOFTWARE_RESET:
882 case WM8962_PLL2:
883 case WM8962_PLL_4:
884 case WM8962_PLL_9:
885 case WM8962_PLL_10:
886 case WM8962_PLL_11:
887 case WM8962_PLL_12:
888 case WM8962_PLL_13:
889 case WM8962_PLL_14:
890 case WM8962_PLL_15:
891 case WM8962_PLL_16:
892 case WM8962_FLL_CONTROL_1:
893 case WM8962_FLL_CONTROL_2:
894 case WM8962_FLL_CONTROL_3:
895 case WM8962_FLL_CONTROL_5:
896 case WM8962_FLL_CONTROL_6:
897 case WM8962_FLL_CONTROL_7:
898 case WM8962_FLL_CONTROL_8:
899 case WM8962_GENERAL_TEST_1:
900 case WM8962_DF1:
901 case WM8962_DF2:
902 case WM8962_DF3:
903 case WM8962_DF4:
904 case WM8962_DF5:
905 case WM8962_DF6:
906 case WM8962_DF7:
907 case WM8962_LHPF1:
908 case WM8962_LHPF2:
909 case WM8962_THREED1:
910 case WM8962_THREED2:
911 case WM8962_THREED3:
912 case WM8962_THREED4:
913 case WM8962_DRC_1:
914 case WM8962_DRC_2:
915 case WM8962_DRC_3:
916 case WM8962_DRC_4:
917 case WM8962_DRC_5:
918 case WM8962_TLOOPBACK:
919 case WM8962_EQ1:
920 case WM8962_EQ2:
921 case WM8962_EQ3:
922 case WM8962_EQ4:
923 case WM8962_EQ5:
924 case WM8962_EQ6:
925 case WM8962_EQ7:
926 case WM8962_EQ8:
927 case WM8962_EQ9:
928 case WM8962_EQ10:
929 case WM8962_EQ11:
930 case WM8962_EQ12:
931 case WM8962_EQ13:
932 case WM8962_EQ14:
933 case WM8962_EQ15:
934 case WM8962_EQ16:
935 case WM8962_EQ17:
936 case WM8962_EQ18:
937 case WM8962_EQ19:
938 case WM8962_EQ20:
939 case WM8962_EQ21:
940 case WM8962_EQ22:
941 case WM8962_EQ23:
942 case WM8962_EQ24:
943 case WM8962_EQ25:
944 case WM8962_EQ26:
945 case WM8962_EQ27:
946 case WM8962_EQ28:
947 case WM8962_EQ29:
948 case WM8962_EQ30:
949 case WM8962_EQ31:
950 case WM8962_EQ32:
951 case WM8962_EQ33:
952 case WM8962_EQ34:
953 case WM8962_EQ35:
954 case WM8962_EQ36:
955 case WM8962_EQ37:
956 case WM8962_EQ38:
957 case WM8962_EQ39:
958 case WM8962_EQ40:
959 case WM8962_EQ41:
960 case WM8962_GPIO_BASE:
961 case WM8962_GPIO_2:
962 case WM8962_GPIO_3:
963 case WM8962_GPIO_5:
964 case WM8962_GPIO_6:
965 case WM8962_INTERRUPT_STATUS_1:
966 case WM8962_INTERRUPT_STATUS_2:
967 case WM8962_INTERRUPT_STATUS_1_MASK:
968 case WM8962_INTERRUPT_STATUS_2_MASK:
969 case WM8962_INTERRUPT_CONTROL:
970 case WM8962_IRQ_DEBOUNCE:
971 case WM8962_MICINT_SOURCE_POL:
972 case WM8962_DSP2_POWER_MANAGEMENT:
973 case WM8962_DSP2_EXECCONTROL:
974 case WM8962_DSP2_INSTRUCTION_RAM_0:
975 case WM8962_DSP2_ADDRESS_RAM_2:
976 case WM8962_DSP2_ADDRESS_RAM_1:
977 case WM8962_DSP2_ADDRESS_RAM_0:
978 case WM8962_DSP2_DATA1_RAM_1:
979 case WM8962_DSP2_DATA1_RAM_0:
980 case WM8962_DSP2_DATA2_RAM_1:
981 case WM8962_DSP2_DATA2_RAM_0:
982 case WM8962_DSP2_DATA3_RAM_1:
983 case WM8962_DSP2_DATA3_RAM_0:
984 case WM8962_DSP2_COEFF_RAM_0:
985 case WM8962_RETUNEADC_SHARED_COEFF_1:
986 case WM8962_RETUNEADC_SHARED_COEFF_0:
987 case WM8962_RETUNEDAC_SHARED_COEFF_1:
988 case WM8962_RETUNEDAC_SHARED_COEFF_0:
989 case WM8962_SOUNDSTAGE_ENABLES_1:
990 case WM8962_SOUNDSTAGE_ENABLES_0:
991 case WM8962_HDBASS_AI_1:
992 case WM8962_HDBASS_AI_0:
993 case WM8962_HDBASS_AR_1:
994 case WM8962_HDBASS_AR_0:
995 case WM8962_HDBASS_B_1:
996 case WM8962_HDBASS_B_0:
997 case WM8962_HDBASS_K_1:
998 case WM8962_HDBASS_K_0:
999 case WM8962_HDBASS_N1_1:
1000 case WM8962_HDBASS_N1_0:
1001 case WM8962_HDBASS_N2_1:
1002 case WM8962_HDBASS_N2_0:
1003 case WM8962_HDBASS_N3_1:
1004 case WM8962_HDBASS_N3_0:
1005 case WM8962_HDBASS_N4_1:
1006 case WM8962_HDBASS_N4_0:
1007 case WM8962_HDBASS_N5_1:
1008 case WM8962_HDBASS_N5_0:
1009 case WM8962_HDBASS_X1_1:
1010 case WM8962_HDBASS_X1_0:
1011 case WM8962_HDBASS_X2_1:
1012 case WM8962_HDBASS_X2_0:
1013 case WM8962_HDBASS_X3_1:
1014 case WM8962_HDBASS_X3_0:
1015 case WM8962_HDBASS_ATK_1:
1016 case WM8962_HDBASS_ATK_0:
1017 case WM8962_HDBASS_DCY_1:
1018 case WM8962_HDBASS_DCY_0:
1019 case WM8962_HDBASS_PG_1:
1020 case WM8962_HDBASS_PG_0:
1021 case WM8962_HPF_C_1:
1022 case WM8962_HPF_C_0:
1023 case WM8962_ADCL_RETUNE_C1_1:
1024 case WM8962_ADCL_RETUNE_C1_0:
1025 case WM8962_ADCL_RETUNE_C2_1:
1026 case WM8962_ADCL_RETUNE_C2_0:
1027 case WM8962_ADCL_RETUNE_C3_1:
1028 case WM8962_ADCL_RETUNE_C3_0:
1029 case WM8962_ADCL_RETUNE_C4_1:
1030 case WM8962_ADCL_RETUNE_C4_0:
1031 case WM8962_ADCL_RETUNE_C5_1:
1032 case WM8962_ADCL_RETUNE_C5_0:
1033 case WM8962_ADCL_RETUNE_C6_1:
1034 case WM8962_ADCL_RETUNE_C6_0:
1035 case WM8962_ADCL_RETUNE_C7_1:
1036 case WM8962_ADCL_RETUNE_C7_0:
1037 case WM8962_ADCL_RETUNE_C8_1:
1038 case WM8962_ADCL_RETUNE_C8_0:
1039 case WM8962_ADCL_RETUNE_C9_1:
1040 case WM8962_ADCL_RETUNE_C9_0:
1041 case WM8962_ADCL_RETUNE_C10_1:
1042 case WM8962_ADCL_RETUNE_C10_0:
1043 case WM8962_ADCL_RETUNE_C11_1:
1044 case WM8962_ADCL_RETUNE_C11_0:
1045 case WM8962_ADCL_RETUNE_C12_1:
1046 case WM8962_ADCL_RETUNE_C12_0:
1047 case WM8962_ADCL_RETUNE_C13_1:
1048 case WM8962_ADCL_RETUNE_C13_0:
1049 case WM8962_ADCL_RETUNE_C14_1:
1050 case WM8962_ADCL_RETUNE_C14_0:
1051 case WM8962_ADCL_RETUNE_C15_1:
1052 case WM8962_ADCL_RETUNE_C15_0:
1053 case WM8962_ADCL_RETUNE_C16_1:
1054 case WM8962_ADCL_RETUNE_C16_0:
1055 case WM8962_ADCL_RETUNE_C17_1:
1056 case WM8962_ADCL_RETUNE_C17_0:
1057 case WM8962_ADCL_RETUNE_C18_1:
1058 case WM8962_ADCL_RETUNE_C18_0:
1059 case WM8962_ADCL_RETUNE_C19_1:
1060 case WM8962_ADCL_RETUNE_C19_0:
1061 case WM8962_ADCL_RETUNE_C20_1:
1062 case WM8962_ADCL_RETUNE_C20_0:
1063 case WM8962_ADCL_RETUNE_C21_1:
1064 case WM8962_ADCL_RETUNE_C21_0:
1065 case WM8962_ADCL_RETUNE_C22_1:
1066 case WM8962_ADCL_RETUNE_C22_0:
1067 case WM8962_ADCL_RETUNE_C23_1:
1068 case WM8962_ADCL_RETUNE_C23_0:
1069 case WM8962_ADCL_RETUNE_C24_1:
1070 case WM8962_ADCL_RETUNE_C24_0:
1071 case WM8962_ADCL_RETUNE_C25_1:
1072 case WM8962_ADCL_RETUNE_C25_0:
1073 case WM8962_ADCL_RETUNE_C26_1:
1074 case WM8962_ADCL_RETUNE_C26_0:
1075 case WM8962_ADCL_RETUNE_C27_1:
1076 case WM8962_ADCL_RETUNE_C27_0:
1077 case WM8962_ADCL_RETUNE_C28_1:
1078 case WM8962_ADCL_RETUNE_C28_0:
1079 case WM8962_ADCL_RETUNE_C29_1:
1080 case WM8962_ADCL_RETUNE_C29_0:
1081 case WM8962_ADCL_RETUNE_C30_1:
1082 case WM8962_ADCL_RETUNE_C30_0:
1083 case WM8962_ADCL_RETUNE_C31_1:
1084 case WM8962_ADCL_RETUNE_C31_0:
1085 case WM8962_ADCL_RETUNE_C32_1:
1086 case WM8962_ADCL_RETUNE_C32_0:
1087 case WM8962_RETUNEADC_PG2_1:
1088 case WM8962_RETUNEADC_PG2_0:
1089 case WM8962_RETUNEADC_PG_1:
1090 case WM8962_RETUNEADC_PG_0:
1091 case WM8962_ADCR_RETUNE_C1_1:
1092 case WM8962_ADCR_RETUNE_C1_0:
1093 case WM8962_ADCR_RETUNE_C2_1:
1094 case WM8962_ADCR_RETUNE_C2_0:
1095 case WM8962_ADCR_RETUNE_C3_1:
1096 case WM8962_ADCR_RETUNE_C3_0:
1097 case WM8962_ADCR_RETUNE_C4_1:
1098 case WM8962_ADCR_RETUNE_C4_0:
1099 case WM8962_ADCR_RETUNE_C5_1:
1100 case WM8962_ADCR_RETUNE_C5_0:
1101 case WM8962_ADCR_RETUNE_C6_1:
1102 case WM8962_ADCR_RETUNE_C6_0:
1103 case WM8962_ADCR_RETUNE_C7_1:
1104 case WM8962_ADCR_RETUNE_C7_0:
1105 case WM8962_ADCR_RETUNE_C8_1:
1106 case WM8962_ADCR_RETUNE_C8_0:
1107 case WM8962_ADCR_RETUNE_C9_1:
1108 case WM8962_ADCR_RETUNE_C9_0:
1109 case WM8962_ADCR_RETUNE_C10_1:
1110 case WM8962_ADCR_RETUNE_C10_0:
1111 case WM8962_ADCR_RETUNE_C11_1:
1112 case WM8962_ADCR_RETUNE_C11_0:
1113 case WM8962_ADCR_RETUNE_C12_1:
1114 case WM8962_ADCR_RETUNE_C12_0:
1115 case WM8962_ADCR_RETUNE_C13_1:
1116 case WM8962_ADCR_RETUNE_C13_0:
1117 case WM8962_ADCR_RETUNE_C14_1:
1118 case WM8962_ADCR_RETUNE_C14_0:
1119 case WM8962_ADCR_RETUNE_C15_1:
1120 case WM8962_ADCR_RETUNE_C15_0:
1121 case WM8962_ADCR_RETUNE_C16_1:
1122 case WM8962_ADCR_RETUNE_C16_0:
1123 case WM8962_ADCR_RETUNE_C17_1:
1124 case WM8962_ADCR_RETUNE_C17_0:
1125 case WM8962_ADCR_RETUNE_C18_1:
1126 case WM8962_ADCR_RETUNE_C18_0:
1127 case WM8962_ADCR_RETUNE_C19_1:
1128 case WM8962_ADCR_RETUNE_C19_0:
1129 case WM8962_ADCR_RETUNE_C20_1:
1130 case WM8962_ADCR_RETUNE_C20_0:
1131 case WM8962_ADCR_RETUNE_C21_1:
1132 case WM8962_ADCR_RETUNE_C21_0:
1133 case WM8962_ADCR_RETUNE_C22_1:
1134 case WM8962_ADCR_RETUNE_C22_0:
1135 case WM8962_ADCR_RETUNE_C23_1:
1136 case WM8962_ADCR_RETUNE_C23_0:
1137 case WM8962_ADCR_RETUNE_C24_1:
1138 case WM8962_ADCR_RETUNE_C24_0:
1139 case WM8962_ADCR_RETUNE_C25_1:
1140 case WM8962_ADCR_RETUNE_C25_0:
1141 case WM8962_ADCR_RETUNE_C26_1:
1142 case WM8962_ADCR_RETUNE_C26_0:
1143 case WM8962_ADCR_RETUNE_C27_1:
1144 case WM8962_ADCR_RETUNE_C27_0:
1145 case WM8962_ADCR_RETUNE_C28_1:
1146 case WM8962_ADCR_RETUNE_C28_0:
1147 case WM8962_ADCR_RETUNE_C29_1:
1148 case WM8962_ADCR_RETUNE_C29_0:
1149 case WM8962_ADCR_RETUNE_C30_1:
1150 case WM8962_ADCR_RETUNE_C30_0:
1151 case WM8962_ADCR_RETUNE_C31_1:
1152 case WM8962_ADCR_RETUNE_C31_0:
1153 case WM8962_ADCR_RETUNE_C32_1:
1154 case WM8962_ADCR_RETUNE_C32_0:
1155 case WM8962_DACL_RETUNE_C1_1:
1156 case WM8962_DACL_RETUNE_C1_0:
1157 case WM8962_DACL_RETUNE_C2_1:
1158 case WM8962_DACL_RETUNE_C2_0:
1159 case WM8962_DACL_RETUNE_C3_1:
1160 case WM8962_DACL_RETUNE_C3_0:
1161 case WM8962_DACL_RETUNE_C4_1:
1162 case WM8962_DACL_RETUNE_C4_0:
1163 case WM8962_DACL_RETUNE_C5_1:
1164 case WM8962_DACL_RETUNE_C5_0:
1165 case WM8962_DACL_RETUNE_C6_1:
1166 case WM8962_DACL_RETUNE_C6_0:
1167 case WM8962_DACL_RETUNE_C7_1:
1168 case WM8962_DACL_RETUNE_C7_0:
1169 case WM8962_DACL_RETUNE_C8_1:
1170 case WM8962_DACL_RETUNE_C8_0:
1171 case WM8962_DACL_RETUNE_C9_1:
1172 case WM8962_DACL_RETUNE_C9_0:
1173 case WM8962_DACL_RETUNE_C10_1:
1174 case WM8962_DACL_RETUNE_C10_0:
1175 case WM8962_DACL_RETUNE_C11_1:
1176 case WM8962_DACL_RETUNE_C11_0:
1177 case WM8962_DACL_RETUNE_C12_1:
1178 case WM8962_DACL_RETUNE_C12_0:
1179 case WM8962_DACL_RETUNE_C13_1:
1180 case WM8962_DACL_RETUNE_C13_0:
1181 case WM8962_DACL_RETUNE_C14_1:
1182 case WM8962_DACL_RETUNE_C14_0:
1183 case WM8962_DACL_RETUNE_C15_1:
1184 case WM8962_DACL_RETUNE_C15_0:
1185 case WM8962_DACL_RETUNE_C16_1:
1186 case WM8962_DACL_RETUNE_C16_0:
1187 case WM8962_DACL_RETUNE_C17_1:
1188 case WM8962_DACL_RETUNE_C17_0:
1189 case WM8962_DACL_RETUNE_C18_1:
1190 case WM8962_DACL_RETUNE_C18_0:
1191 case WM8962_DACL_RETUNE_C19_1:
1192 case WM8962_DACL_RETUNE_C19_0:
1193 case WM8962_DACL_RETUNE_C20_1:
1194 case WM8962_DACL_RETUNE_C20_0:
1195 case WM8962_DACL_RETUNE_C21_1:
1196 case WM8962_DACL_RETUNE_C21_0:
1197 case WM8962_DACL_RETUNE_C22_1:
1198 case WM8962_DACL_RETUNE_C22_0:
1199 case WM8962_DACL_RETUNE_C23_1:
1200 case WM8962_DACL_RETUNE_C23_0:
1201 case WM8962_DACL_RETUNE_C24_1:
1202 case WM8962_DACL_RETUNE_C24_0:
1203 case WM8962_DACL_RETUNE_C25_1:
1204 case WM8962_DACL_RETUNE_C25_0:
1205 case WM8962_DACL_RETUNE_C26_1:
1206 case WM8962_DACL_RETUNE_C26_0:
1207 case WM8962_DACL_RETUNE_C27_1:
1208 case WM8962_DACL_RETUNE_C27_0:
1209 case WM8962_DACL_RETUNE_C28_1:
1210 case WM8962_DACL_RETUNE_C28_0:
1211 case WM8962_DACL_RETUNE_C29_1:
1212 case WM8962_DACL_RETUNE_C29_0:
1213 case WM8962_DACL_RETUNE_C30_1:
1214 case WM8962_DACL_RETUNE_C30_0:
1215 case WM8962_DACL_RETUNE_C31_1:
1216 case WM8962_DACL_RETUNE_C31_0:
1217 case WM8962_DACL_RETUNE_C32_1:
1218 case WM8962_DACL_RETUNE_C32_0:
1219 case WM8962_RETUNEDAC_PG2_1:
1220 case WM8962_RETUNEDAC_PG2_0:
1221 case WM8962_RETUNEDAC_PG_1:
1222 case WM8962_RETUNEDAC_PG_0:
1223 case WM8962_DACR_RETUNE_C1_1:
1224 case WM8962_DACR_RETUNE_C1_0:
1225 case WM8962_DACR_RETUNE_C2_1:
1226 case WM8962_DACR_RETUNE_C2_0:
1227 case WM8962_DACR_RETUNE_C3_1:
1228 case WM8962_DACR_RETUNE_C3_0:
1229 case WM8962_DACR_RETUNE_C4_1:
1230 case WM8962_DACR_RETUNE_C4_0:
1231 case WM8962_DACR_RETUNE_C5_1:
1232 case WM8962_DACR_RETUNE_C5_0:
1233 case WM8962_DACR_RETUNE_C6_1:
1234 case WM8962_DACR_RETUNE_C6_0:
1235 case WM8962_DACR_RETUNE_C7_1:
1236 case WM8962_DACR_RETUNE_C7_0:
1237 case WM8962_DACR_RETUNE_C8_1:
1238 case WM8962_DACR_RETUNE_C8_0:
1239 case WM8962_DACR_RETUNE_C9_1:
1240 case WM8962_DACR_RETUNE_C9_0:
1241 case WM8962_DACR_RETUNE_C10_1:
1242 case WM8962_DACR_RETUNE_C10_0:
1243 case WM8962_DACR_RETUNE_C11_1:
1244 case WM8962_DACR_RETUNE_C11_0:
1245 case WM8962_DACR_RETUNE_C12_1:
1246 case WM8962_DACR_RETUNE_C12_0:
1247 case WM8962_DACR_RETUNE_C13_1:
1248 case WM8962_DACR_RETUNE_C13_0:
1249 case WM8962_DACR_RETUNE_C14_1:
1250 case WM8962_DACR_RETUNE_C14_0:
1251 case WM8962_DACR_RETUNE_C15_1:
1252 case WM8962_DACR_RETUNE_C15_0:
1253 case WM8962_DACR_RETUNE_C16_1:
1254 case WM8962_DACR_RETUNE_C16_0:
1255 case WM8962_DACR_RETUNE_C17_1:
1256 case WM8962_DACR_RETUNE_C17_0:
1257 case WM8962_DACR_RETUNE_C18_1:
1258 case WM8962_DACR_RETUNE_C18_0:
1259 case WM8962_DACR_RETUNE_C19_1:
1260 case WM8962_DACR_RETUNE_C19_0:
1261 case WM8962_DACR_RETUNE_C20_1:
1262 case WM8962_DACR_RETUNE_C20_0:
1263 case WM8962_DACR_RETUNE_C21_1:
1264 case WM8962_DACR_RETUNE_C21_0:
1265 case WM8962_DACR_RETUNE_C22_1:
1266 case WM8962_DACR_RETUNE_C22_0:
1267 case WM8962_DACR_RETUNE_C23_1:
1268 case WM8962_DACR_RETUNE_C23_0:
1269 case WM8962_DACR_RETUNE_C24_1:
1270 case WM8962_DACR_RETUNE_C24_0:
1271 case WM8962_DACR_RETUNE_C25_1:
1272 case WM8962_DACR_RETUNE_C25_0:
1273 case WM8962_DACR_RETUNE_C26_1:
1274 case WM8962_DACR_RETUNE_C26_0:
1275 case WM8962_DACR_RETUNE_C27_1:
1276 case WM8962_DACR_RETUNE_C27_0:
1277 case WM8962_DACR_RETUNE_C28_1:
1278 case WM8962_DACR_RETUNE_C28_0:
1279 case WM8962_DACR_RETUNE_C29_1:
1280 case WM8962_DACR_RETUNE_C29_0:
1281 case WM8962_DACR_RETUNE_C30_1:
1282 case WM8962_DACR_RETUNE_C30_0:
1283 case WM8962_DACR_RETUNE_C31_1:
1284 case WM8962_DACR_RETUNE_C31_0:
1285 case WM8962_DACR_RETUNE_C32_1:
1286 case WM8962_DACR_RETUNE_C32_0:
1287 case WM8962_VSS_XHD2_1:
1288 case WM8962_VSS_XHD2_0:
1289 case WM8962_VSS_XHD3_1:
1290 case WM8962_VSS_XHD3_0:
1291 case WM8962_VSS_XHN1_1:
1292 case WM8962_VSS_XHN1_0:
1293 case WM8962_VSS_XHN2_1:
1294 case WM8962_VSS_XHN2_0:
1295 case WM8962_VSS_XHN3_1:
1296 case WM8962_VSS_XHN3_0:
1297 case WM8962_VSS_XLA_1:
1298 case WM8962_VSS_XLA_0:
1299 case WM8962_VSS_XLB_1:
1300 case WM8962_VSS_XLB_0:
1301 case WM8962_VSS_XLG_1:
1302 case WM8962_VSS_XLG_0:
1303 case WM8962_VSS_PG2_1:
1304 case WM8962_VSS_PG2_0:
1305 case WM8962_VSS_PG_1:
1306 case WM8962_VSS_PG_0:
1307 case WM8962_VSS_XTD1_1:
1308 case WM8962_VSS_XTD1_0:
1309 case WM8962_VSS_XTD2_1:
1310 case WM8962_VSS_XTD2_0:
1311 case WM8962_VSS_XTD3_1:
1312 case WM8962_VSS_XTD3_0:
1313 case WM8962_VSS_XTD4_1:
1314 case WM8962_VSS_XTD4_0:
1315 case WM8962_VSS_XTD5_1:
1316 case WM8962_VSS_XTD5_0:
1317 case WM8962_VSS_XTD6_1:
1318 case WM8962_VSS_XTD6_0:
1319 case WM8962_VSS_XTD7_1:
1320 case WM8962_VSS_XTD7_0:
1321 case WM8962_VSS_XTD8_1:
1322 case WM8962_VSS_XTD8_0:
1323 case WM8962_VSS_XTD9_1:
1324 case WM8962_VSS_XTD9_0:
1325 case WM8962_VSS_XTD10_1:
1326 case WM8962_VSS_XTD10_0:
1327 case WM8962_VSS_XTD11_1:
1328 case WM8962_VSS_XTD11_0:
1329 case WM8962_VSS_XTD12_1:
1330 case WM8962_VSS_XTD12_0:
1331 case WM8962_VSS_XTD13_1:
1332 case WM8962_VSS_XTD13_0:
1333 case WM8962_VSS_XTD14_1:
1334 case WM8962_VSS_XTD14_0:
1335 case WM8962_VSS_XTD15_1:
1336 case WM8962_VSS_XTD15_0:
1337 case WM8962_VSS_XTD16_1:
1338 case WM8962_VSS_XTD16_0:
1339 case WM8962_VSS_XTD17_1:
1340 case WM8962_VSS_XTD17_0:
1341 case WM8962_VSS_XTD18_1:
1342 case WM8962_VSS_XTD18_0:
1343 case WM8962_VSS_XTD19_1:
1344 case WM8962_VSS_XTD19_0:
1345 case WM8962_VSS_XTD20_1:
1346 case WM8962_VSS_XTD20_0:
1347 case WM8962_VSS_XTD21_1:
1348 case WM8962_VSS_XTD21_0:
1349 case WM8962_VSS_XTD22_1:
1350 case WM8962_VSS_XTD22_0:
1351 case WM8962_VSS_XTD23_1:
1352 case WM8962_VSS_XTD23_0:
1353 case WM8962_VSS_XTD24_1:
1354 case WM8962_VSS_XTD24_0:
1355 case WM8962_VSS_XTD25_1:
1356 case WM8962_VSS_XTD25_0:
1357 case WM8962_VSS_XTD26_1:
1358 case WM8962_VSS_XTD26_0:
1359 case WM8962_VSS_XTD27_1:
1360 case WM8962_VSS_XTD27_0:
1361 case WM8962_VSS_XTD28_1:
1362 case WM8962_VSS_XTD28_0:
1363 case WM8962_VSS_XTD29_1:
1364 case WM8962_VSS_XTD29_0:
1365 case WM8962_VSS_XTD30_1:
1366 case WM8962_VSS_XTD30_0:
1367 case WM8962_VSS_XTD31_1:
1368 case WM8962_VSS_XTD31_0:
1369 case WM8962_VSS_XTD32_1:
1370 case WM8962_VSS_XTD32_0:
1371 case WM8962_VSS_XTS1_1:
1372 case WM8962_VSS_XTS1_0:
1373 case WM8962_VSS_XTS2_1:
1374 case WM8962_VSS_XTS2_0:
1375 case WM8962_VSS_XTS3_1:
1376 case WM8962_VSS_XTS3_0:
1377 case WM8962_VSS_XTS4_1:
1378 case WM8962_VSS_XTS4_0:
1379 case WM8962_VSS_XTS5_1:
1380 case WM8962_VSS_XTS5_0:
1381 case WM8962_VSS_XTS6_1:
1382 case WM8962_VSS_XTS6_0:
1383 case WM8962_VSS_XTS7_1:
1384 case WM8962_VSS_XTS7_0:
1385 case WM8962_VSS_XTS8_1:
1386 case WM8962_VSS_XTS8_0:
1387 case WM8962_VSS_XTS9_1:
1388 case WM8962_VSS_XTS9_0:
1389 case WM8962_VSS_XTS10_1:
1390 case WM8962_VSS_XTS10_0:
1391 case WM8962_VSS_XTS11_1:
1392 case WM8962_VSS_XTS11_0:
1393 case WM8962_VSS_XTS12_1:
1394 case WM8962_VSS_XTS12_0:
1395 case WM8962_VSS_XTS13_1:
1396 case WM8962_VSS_XTS13_0:
1397 case WM8962_VSS_XTS14_1:
1398 case WM8962_VSS_XTS14_0:
1399 case WM8962_VSS_XTS15_1:
1400 case WM8962_VSS_XTS15_0:
1401 case WM8962_VSS_XTS16_1:
1402 case WM8962_VSS_XTS16_0:
1403 case WM8962_VSS_XTS17_1:
1404 case WM8962_VSS_XTS17_0:
1405 case WM8962_VSS_XTS18_1:
1406 case WM8962_VSS_XTS18_0:
1407 case WM8962_VSS_XTS19_1:
1408 case WM8962_VSS_XTS19_0:
1409 case WM8962_VSS_XTS20_1:
1410 case WM8962_VSS_XTS20_0:
1411 case WM8962_VSS_XTS21_1:
1412 case WM8962_VSS_XTS21_0:
1413 case WM8962_VSS_XTS22_1:
1414 case WM8962_VSS_XTS22_0:
1415 case WM8962_VSS_XTS23_1:
1416 case WM8962_VSS_XTS23_0:
1417 case WM8962_VSS_XTS24_1:
1418 case WM8962_VSS_XTS24_0:
1419 case WM8962_VSS_XTS25_1:
1420 case WM8962_VSS_XTS25_0:
1421 case WM8962_VSS_XTS26_1:
1422 case WM8962_VSS_XTS26_0:
1423 case WM8962_VSS_XTS27_1:
1424 case WM8962_VSS_XTS27_0:
1425 case WM8962_VSS_XTS28_1:
1426 case WM8962_VSS_XTS28_0:
1427 case WM8962_VSS_XTS29_1:
1428 case WM8962_VSS_XTS29_0:
1429 case WM8962_VSS_XTS30_1:
1430 case WM8962_VSS_XTS30_0:
1431 case WM8962_VSS_XTS31_1:
1432 case WM8962_VSS_XTS31_0:
1433 case WM8962_VSS_XTS32_1:
1434 case WM8962_VSS_XTS32_0:
1435 return true;
1436 default:
1437 return false;
1438 }
1439 }
1440
1441 static int wm8962_reset(struct wm8962_priv *wm8962)
1442 {
1443 int ret;
1444
1445 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
1446 if (ret != 0)
1447 return ret;
1448
1449 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
1450 }
1451
1452 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1453 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1454 static const DECLARE_TLV_DB_RANGE(mixinpga_tlv,
1455 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1456 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1457 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1458 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1459 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0)
1460 );
1461 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1462 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1463 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1464 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1465 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1466 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1467 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1468 static const DECLARE_TLV_DB_RANGE(classd_tlv,
1469 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1470 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0)
1471 );
1472 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1473
1474 static int wm8962_dsp2_write_config(struct snd_soc_component *component)
1475 {
1476 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1477
1478 return regcache_sync_region(wm8962->regmap,
1479 WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
1480 }
1481
1482 static int wm8962_dsp2_set_enable(struct snd_soc_component *component, u16 val)
1483 {
1484 u16 adcl = snd_soc_component_read32(component, WM8962_LEFT_ADC_VOLUME);
1485 u16 adcr = snd_soc_component_read32(component, WM8962_RIGHT_ADC_VOLUME);
1486 u16 dac = snd_soc_component_read32(component, WM8962_ADC_DAC_CONTROL_1);
1487
1488
1489 snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, 0);
1490 snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1491 snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
1492 WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1493
1494 snd_soc_component_write(component, WM8962_SOUNDSTAGE_ENABLES_0, val);
1495
1496
1497 snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, adcl);
1498 snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, adcr);
1499 snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
1500 WM8962_DAC_MUTE, dac);
1501
1502 return 0;
1503 }
1504
1505 static int wm8962_dsp2_start(struct snd_soc_component *component)
1506 {
1507 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1508
1509 wm8962_dsp2_write_config(component);
1510
1511 snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1512
1513 wm8962_dsp2_set_enable(component, wm8962->dsp2_ena);
1514
1515 return 0;
1516 }
1517
1518 static int wm8962_dsp2_stop(struct snd_soc_component *component)
1519 {
1520 wm8962_dsp2_set_enable(component, 0);
1521
1522 snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1523
1524 return 0;
1525 }
1526
1527 #define WM8962_DSP2_ENABLE(xname, xshift) \
1528 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1529 .info = wm8962_dsp2_ena_info, \
1530 .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1531 .private_value = xshift }
1532
1533 static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1534 struct snd_ctl_elem_info *uinfo)
1535 {
1536 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1537
1538 uinfo->count = 1;
1539 uinfo->value.integer.min = 0;
1540 uinfo->value.integer.max = 1;
1541
1542 return 0;
1543 }
1544
1545 static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1546 struct snd_ctl_elem_value *ucontrol)
1547 {
1548 int shift = kcontrol->private_value;
1549 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1550 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1551
1552 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1553
1554 return 0;
1555 }
1556
1557 static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1558 struct snd_ctl_elem_value *ucontrol)
1559 {
1560 int shift = kcontrol->private_value;
1561 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1562 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1563 int old = wm8962->dsp2_ena;
1564 int ret = 0;
1565 int dsp2_running = snd_soc_component_read32(component, WM8962_DSP2_POWER_MANAGEMENT) &
1566 WM8962_DSP2_ENA;
1567
1568 mutex_lock(&wm8962->dsp2_ena_lock);
1569
1570 if (ucontrol->value.integer.value[0])
1571 wm8962->dsp2_ena |= 1 << shift;
1572 else
1573 wm8962->dsp2_ena &= ~(1 << shift);
1574
1575 if (wm8962->dsp2_ena == old)
1576 goto out;
1577
1578 ret = 1;
1579
1580 if (dsp2_running) {
1581 if (wm8962->dsp2_ena)
1582 wm8962_dsp2_set_enable(component, wm8962->dsp2_ena);
1583 else
1584 wm8962_dsp2_stop(component);
1585 }
1586
1587 out:
1588 mutex_unlock(&wm8962->dsp2_ena_lock);
1589
1590 return ret;
1591 }
1592
1593
1594
1595
1596 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1597 struct snd_ctl_elem_value *ucontrol)
1598 {
1599 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1600 int ret;
1601
1602
1603 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1604 if (ret == 0)
1605 return 0;
1606
1607
1608 ret = snd_soc_component_read32(component, WM8962_PWR_MGMT_2);
1609 if (ret & WM8962_HPOUTL_PGA_ENA) {
1610 snd_soc_component_write(component, WM8962_HPOUTL_VOLUME,
1611 snd_soc_component_read32(component, WM8962_HPOUTL_VOLUME));
1612 return 1;
1613 }
1614
1615
1616 if (ret & WM8962_HPOUTR_PGA_ENA)
1617 snd_soc_component_write(component, WM8962_HPOUTR_VOLUME,
1618 snd_soc_component_read32(component, WM8962_HPOUTR_VOLUME));
1619
1620 return 1;
1621 }
1622
1623
1624
1625
1626 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1627 struct snd_ctl_elem_value *ucontrol)
1628 {
1629 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1630 int ret;
1631
1632
1633 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1634 if (ret == 0)
1635 return 0;
1636
1637
1638 ret = snd_soc_component_read32(component, WM8962_PWR_MGMT_2);
1639 if (ret & WM8962_SPKOUTL_PGA_ENA) {
1640 snd_soc_component_write(component, WM8962_SPKOUTL_VOLUME,
1641 snd_soc_component_read32(component, WM8962_SPKOUTL_VOLUME));
1642 return 1;
1643 }
1644
1645
1646 if (ret & WM8962_SPKOUTR_PGA_ENA)
1647 snd_soc_component_write(component, WM8962_SPKOUTR_VOLUME,
1648 snd_soc_component_read32(component, WM8962_SPKOUTR_VOLUME));
1649
1650 return 1;
1651 }
1652
1653 static const char *cap_hpf_mode_text[] = {
1654 "Hi-fi", "Application"
1655 };
1656
1657 static SOC_ENUM_SINGLE_DECL(cap_hpf_mode,
1658 WM8962_ADC_DAC_CONTROL_2, 10, cap_hpf_mode_text);
1659
1660
1661 static const char *cap_lhpf_mode_text[] = {
1662 "LPF", "HPF"
1663 };
1664
1665 static SOC_ENUM_SINGLE_DECL(cap_lhpf_mode,
1666 WM8962_LHPF1, 1, cap_lhpf_mode_text);
1667
1668 static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1669 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1670
1671 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1672 mixin_tlv),
1673 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1674 mixinpga_tlv),
1675 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1676 mixin_tlv),
1677
1678 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1679 mixin_tlv),
1680 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1681 mixinpga_tlv),
1682 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1683 mixin_tlv),
1684
1685 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1686 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1687 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1688 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1689 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1690 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1691 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1692 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
1693 SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1694 SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1695 SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
1696 SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1697 SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
1698
1699 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1700 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1701
1702 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1703 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1704 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
1705 SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1706 SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
1707
1708 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1709 5, 1, 0),
1710
1711 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1712
1713 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1714 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1715 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1716 snd_soc_get_volsw, wm8962_put_hp_sw),
1717 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1718 7, 1, 0),
1719 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1720 hp_tlv),
1721
1722 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1723 WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1724
1725 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1726 3, 7, 0, bypass_tlv),
1727 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1728 0, 7, 0, bypass_tlv),
1729 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1730 7, 1, 1, inmix_tlv),
1731 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1732 6, 1, 1, inmix_tlv),
1733
1734 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1735 3, 7, 0, bypass_tlv),
1736 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1737 0, 7, 0, bypass_tlv),
1738 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1739 7, 1, 1, inmix_tlv),
1740 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1741 6, 1, 1, inmix_tlv),
1742
1743 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1744 classd_tlv),
1745
1746 SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1747 SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1748 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1749 SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1750 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1751 SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1752 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1753 SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1754 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1755 SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1756 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
1757 SND_SOC_BYTES("EQL Coefficients", WM8962_EQ4, 18),
1758 SND_SOC_BYTES("EQR Coefficients", WM8962_EQ24, 18),
1759
1760
1761 SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
1762 SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
1763
1764 SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
1765 SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
1766
1767 SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
1768 SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
1769
1770 WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1771 SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
1772 WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1773 WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1774 SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
1775 WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
1776 SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
1777
1778 SOC_DOUBLE("ALC Switch", WM8962_ALC1, WM8962_ALCL_ENA_SHIFT,
1779 WM8962_ALCR_ENA_SHIFT, 1, 0),
1780 SND_SOC_BYTES_MASK("ALC Coefficients", WM8962_ALC1, 4,
1781 WM8962_ALCL_ENA_MASK | WM8962_ALCR_ENA_MASK),
1782 };
1783
1784 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1785 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1786 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1787 snd_soc_get_volsw, wm8962_put_spk_sw),
1788 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1789
1790 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1791 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1792 3, 7, 0, bypass_tlv),
1793 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1794 0, 7, 0, bypass_tlv),
1795 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1796 7, 1, 1, inmix_tlv),
1797 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1798 6, 1, 1, inmix_tlv),
1799 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1800 7, 1, 0, inmix_tlv),
1801 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1802 6, 1, 0, inmix_tlv),
1803 };
1804
1805 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1806 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1807 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1808 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1809 snd_soc_get_volsw, wm8962_put_spk_sw),
1810 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1811 7, 1, 0),
1812
1813 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1814 WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1815
1816 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1817 3, 7, 0, bypass_tlv),
1818 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1819 0, 7, 0, bypass_tlv),
1820 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1821 7, 1, 1, inmix_tlv),
1822 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1823 6, 1, 1, inmix_tlv),
1824 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1825 7, 1, 0, inmix_tlv),
1826 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1827 6, 1, 0, inmix_tlv),
1828
1829 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1830 3, 7, 0, bypass_tlv),
1831 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1832 0, 7, 0, bypass_tlv),
1833 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1834 7, 1, 1, inmix_tlv),
1835 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1836 6, 1, 1, inmix_tlv),
1837 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1838 5, 1, 0, inmix_tlv),
1839 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1840 4, 1, 0, inmix_tlv),
1841 };
1842
1843 static int cp_event(struct snd_soc_dapm_widget *w,
1844 struct snd_kcontrol *kcontrol, int event)
1845 {
1846 switch (event) {
1847 case SND_SOC_DAPM_POST_PMU:
1848 msleep(5);
1849 break;
1850
1851 default:
1852 WARN(1, "Invalid event %d\n", event);
1853 return -EINVAL;
1854 }
1855
1856 return 0;
1857 }
1858
1859 static int hp_event(struct snd_soc_dapm_widget *w,
1860 struct snd_kcontrol *kcontrol, int event)
1861 {
1862 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1863 int timeout;
1864 int reg;
1865 int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1866 WM8962_DCS_STARTUP_DONE_HP1R);
1867
1868 switch (event) {
1869 case SND_SOC_DAPM_POST_PMU:
1870 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1871 WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1872 WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1873 udelay(20);
1874
1875 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1876 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1877 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1878
1879
1880 snd_soc_component_update_bits(component, WM8962_DC_SERVO_1,
1881 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1882 WM8962_HP1L_DCS_STARTUP |
1883 WM8962_HP1R_DCS_STARTUP,
1884 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1885 WM8962_HP1L_DCS_STARTUP |
1886 WM8962_HP1R_DCS_STARTUP);
1887
1888
1889 timeout = 0;
1890 do {
1891 msleep(1);
1892 reg = snd_soc_component_read32(component, WM8962_DC_SERVO_6);
1893 if (reg < 0) {
1894 dev_err(component->dev,
1895 "Failed to read DCS status: %d\n",
1896 reg);
1897 continue;
1898 }
1899 dev_dbg(component->dev, "DCS status: %x\n", reg);
1900 } while (++timeout < 200 && (reg & expected) != expected);
1901
1902 if ((reg & expected) != expected)
1903 dev_err(component->dev, "DC servo timed out\n");
1904 else
1905 dev_dbg(component->dev, "DC servo complete after %dms\n",
1906 timeout);
1907
1908 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1909 WM8962_HP1L_ENA_OUTP |
1910 WM8962_HP1R_ENA_OUTP,
1911 WM8962_HP1L_ENA_OUTP |
1912 WM8962_HP1R_ENA_OUTP);
1913 udelay(20);
1914
1915 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1916 WM8962_HP1L_RMV_SHORT |
1917 WM8962_HP1R_RMV_SHORT,
1918 WM8962_HP1L_RMV_SHORT |
1919 WM8962_HP1R_RMV_SHORT);
1920 break;
1921
1922 case SND_SOC_DAPM_PRE_PMD:
1923 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1924 WM8962_HP1L_RMV_SHORT |
1925 WM8962_HP1R_RMV_SHORT, 0);
1926
1927 udelay(20);
1928
1929 snd_soc_component_update_bits(component, WM8962_DC_SERVO_1,
1930 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1931 WM8962_HP1L_DCS_STARTUP |
1932 WM8962_HP1R_DCS_STARTUP,
1933 0);
1934
1935 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1936 WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1937 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1938 WM8962_HP1L_ENA_OUTP |
1939 WM8962_HP1R_ENA_OUTP, 0);
1940
1941 break;
1942
1943 default:
1944 WARN(1, "Invalid event %d\n", event);
1945 return -EINVAL;
1946
1947 }
1948
1949 return 0;
1950 }
1951
1952
1953 static int out_pga_event(struct snd_soc_dapm_widget *w,
1954 struct snd_kcontrol *kcontrol, int event)
1955 {
1956 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1957 int reg;
1958
1959 switch (w->shift) {
1960 case WM8962_HPOUTR_PGA_ENA_SHIFT:
1961 reg = WM8962_HPOUTR_VOLUME;
1962 break;
1963 case WM8962_HPOUTL_PGA_ENA_SHIFT:
1964 reg = WM8962_HPOUTL_VOLUME;
1965 break;
1966 case WM8962_SPKOUTR_PGA_ENA_SHIFT:
1967 reg = WM8962_SPKOUTR_VOLUME;
1968 break;
1969 case WM8962_SPKOUTL_PGA_ENA_SHIFT:
1970 reg = WM8962_SPKOUTL_VOLUME;
1971 break;
1972 default:
1973 WARN(1, "Invalid shift %d\n", w->shift);
1974 return -EINVAL;
1975 }
1976
1977 switch (event) {
1978 case SND_SOC_DAPM_POST_PMU:
1979 return snd_soc_component_write(component, reg, snd_soc_component_read32(component, reg));
1980 default:
1981 WARN(1, "Invalid event %d\n", event);
1982 return -EINVAL;
1983 }
1984 }
1985
1986 static int dsp2_event(struct snd_soc_dapm_widget *w,
1987 struct snd_kcontrol *kcontrol, int event)
1988 {
1989 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1990 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1991
1992 switch (event) {
1993 case SND_SOC_DAPM_POST_PMU:
1994 if (wm8962->dsp2_ena)
1995 wm8962_dsp2_start(component);
1996 break;
1997
1998 case SND_SOC_DAPM_PRE_PMD:
1999 if (wm8962->dsp2_ena)
2000 wm8962_dsp2_stop(component);
2001 break;
2002
2003 default:
2004 WARN(1, "Invalid event %d\n", event);
2005 return -EINVAL;
2006 }
2007
2008 return 0;
2009 }
2010
2011 static const char *st_text[] = { "None", "Left", "Right" };
2012
2013 static SOC_ENUM_SINGLE_DECL(str_enum,
2014 WM8962_DAC_DSP_MIXING_1, 2, st_text);
2015
2016 static const struct snd_kcontrol_new str_mux =
2017 SOC_DAPM_ENUM("Right Sidetone", str_enum);
2018
2019 static SOC_ENUM_SINGLE_DECL(stl_enum,
2020 WM8962_DAC_DSP_MIXING_2, 2, st_text);
2021
2022 static const struct snd_kcontrol_new stl_mux =
2023 SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2024
2025 static const char *outmux_text[] = { "DAC", "Mixer" };
2026
2027 static SOC_ENUM_SINGLE_DECL(spkoutr_enum,
2028 WM8962_SPEAKER_MIXER_2, 7, outmux_text);
2029
2030 static const struct snd_kcontrol_new spkoutr_mux =
2031 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2032
2033 static SOC_ENUM_SINGLE_DECL(spkoutl_enum,
2034 WM8962_SPEAKER_MIXER_1, 7, outmux_text);
2035
2036 static const struct snd_kcontrol_new spkoutl_mux =
2037 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2038
2039 static SOC_ENUM_SINGLE_DECL(hpoutr_enum,
2040 WM8962_HEADPHONE_MIXER_2, 7, outmux_text);
2041
2042 static const struct snd_kcontrol_new hpoutr_mux =
2043 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2044
2045 static SOC_ENUM_SINGLE_DECL(hpoutl_enum,
2046 WM8962_HEADPHONE_MIXER_1, 7, outmux_text);
2047
2048 static const struct snd_kcontrol_new hpoutl_mux =
2049 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2050
2051 static const struct snd_kcontrol_new inpgal[] = {
2052 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2053 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2054 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2055 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2056 };
2057
2058 static const struct snd_kcontrol_new inpgar[] = {
2059 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2060 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2061 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2062 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2063 };
2064
2065 static const struct snd_kcontrol_new mixinl[] = {
2066 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2067 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2068 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2069 };
2070
2071 static const struct snd_kcontrol_new mixinr[] = {
2072 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2073 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2074 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2075 };
2076
2077 static const struct snd_kcontrol_new hpmixl[] = {
2078 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2079 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2080 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2081 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2082 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2083 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2084 };
2085
2086 static const struct snd_kcontrol_new hpmixr[] = {
2087 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2088 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2089 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2090 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2091 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2092 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2093 };
2094
2095 static const struct snd_kcontrol_new spkmixl[] = {
2096 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2097 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2098 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2099 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2100 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2101 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2102 };
2103
2104 static const struct snd_kcontrol_new spkmixr[] = {
2105 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2106 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2107 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2108 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2109 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2110 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2111 };
2112
2113 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2114 SND_SOC_DAPM_INPUT("IN1L"),
2115 SND_SOC_DAPM_INPUT("IN1R"),
2116 SND_SOC_DAPM_INPUT("IN2L"),
2117 SND_SOC_DAPM_INPUT("IN2R"),
2118 SND_SOC_DAPM_INPUT("IN3L"),
2119 SND_SOC_DAPM_INPUT("IN3R"),
2120 SND_SOC_DAPM_INPUT("IN4L"),
2121 SND_SOC_DAPM_INPUT("IN4R"),
2122 SND_SOC_DAPM_SIGGEN("Beep"),
2123 SND_SOC_DAPM_INPUT("DMICDAT"),
2124
2125 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
2126
2127 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
2128 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
2129 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2130 SND_SOC_DAPM_POST_PMU),
2131 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
2132 SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2133 WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2134 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2135 SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2136 SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
2137
2138 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2139 inpgal, ARRAY_SIZE(inpgal)),
2140 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2141 inpgar, ARRAY_SIZE(inpgar)),
2142 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2143 mixinl, ARRAY_SIZE(mixinl)),
2144 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2145 mixinr, ARRAY_SIZE(mixinr)),
2146
2147 SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
2148
2149 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2150 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2151
2152 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2153 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2154
2155 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2156 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2157
2158 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2159 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2160
2161 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2162 hpmixl, ARRAY_SIZE(hpmixl)),
2163 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2164 hpmixr, ARRAY_SIZE(hpmixr)),
2165
2166 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2167 out_pga_event, SND_SOC_DAPM_POST_PMU),
2168 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2169 out_pga_event, SND_SOC_DAPM_POST_PMU),
2170
2171 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2172 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2173
2174 SND_SOC_DAPM_OUTPUT("HPOUTL"),
2175 SND_SOC_DAPM_OUTPUT("HPOUTR"),
2176 };
2177
2178 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2179 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2180 spkmixl, ARRAY_SIZE(spkmixl)),
2181 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2182 out_pga_event, SND_SOC_DAPM_POST_PMU),
2183 SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2184 SND_SOC_DAPM_OUTPUT("SPKOUT"),
2185 };
2186
2187 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2188 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2189 spkmixl, ARRAY_SIZE(spkmixl)),
2190 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2191 spkmixr, ARRAY_SIZE(spkmixr)),
2192
2193 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2194 out_pga_event, SND_SOC_DAPM_POST_PMU),
2195 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2196 out_pga_event, SND_SOC_DAPM_POST_PMU),
2197
2198 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2199 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2200
2201 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2202 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2203 };
2204
2205 static const struct snd_soc_dapm_route wm8962_intercon[] = {
2206 { "INPGAL", "IN1L Switch", "IN1L" },
2207 { "INPGAL", "IN2L Switch", "IN2L" },
2208 { "INPGAL", "IN3L Switch", "IN3L" },
2209 { "INPGAL", "IN4L Switch", "IN4L" },
2210
2211 { "INPGAR", "IN1R Switch", "IN1R" },
2212 { "INPGAR", "IN2R Switch", "IN2R" },
2213 { "INPGAR", "IN3R Switch", "IN3R" },
2214 { "INPGAR", "IN4R Switch", "IN4R" },
2215
2216 { "MIXINL", "IN2L Switch", "IN2L" },
2217 { "MIXINL", "IN3L Switch", "IN3L" },
2218 { "MIXINL", "PGA Switch", "INPGAL" },
2219
2220 { "MIXINR", "IN2R Switch", "IN2R" },
2221 { "MIXINR", "IN3R Switch", "IN3R" },
2222 { "MIXINR", "PGA Switch", "INPGAR" },
2223
2224 { "MICBIAS", NULL, "SYSCLK" },
2225
2226 { "DMIC_ENA", NULL, "DMICDAT" },
2227
2228 { "ADCL", NULL, "SYSCLK" },
2229 { "ADCL", NULL, "TOCLK" },
2230 { "ADCL", NULL, "MIXINL" },
2231 { "ADCL", NULL, "DMIC_ENA" },
2232 { "ADCL", NULL, "DSP2" },
2233
2234 { "ADCR", NULL, "SYSCLK" },
2235 { "ADCR", NULL, "TOCLK" },
2236 { "ADCR", NULL, "MIXINR" },
2237 { "ADCR", NULL, "DMIC_ENA" },
2238 { "ADCR", NULL, "DSP2" },
2239
2240 { "STL", "Left", "ADCL" },
2241 { "STL", "Right", "ADCR" },
2242 { "STL", NULL, "Class G" },
2243
2244 { "STR", "Left", "ADCL" },
2245 { "STR", "Right", "ADCR" },
2246 { "STR", NULL, "Class G" },
2247
2248 { "DACL", NULL, "SYSCLK" },
2249 { "DACL", NULL, "TOCLK" },
2250 { "DACL", NULL, "Beep" },
2251 { "DACL", NULL, "STL" },
2252 { "DACL", NULL, "DSP2" },
2253
2254 { "DACR", NULL, "SYSCLK" },
2255 { "DACR", NULL, "TOCLK" },
2256 { "DACR", NULL, "Beep" },
2257 { "DACR", NULL, "STR" },
2258 { "DACR", NULL, "DSP2" },
2259
2260 { "HPMIXL", "IN4L Switch", "IN4L" },
2261 { "HPMIXL", "IN4R Switch", "IN4R" },
2262 { "HPMIXL", "DACL Switch", "DACL" },
2263 { "HPMIXL", "DACR Switch", "DACR" },
2264 { "HPMIXL", "MIXINL Switch", "MIXINL" },
2265 { "HPMIXL", "MIXINR Switch", "MIXINR" },
2266
2267 { "HPMIXR", "IN4L Switch", "IN4L" },
2268 { "HPMIXR", "IN4R Switch", "IN4R" },
2269 { "HPMIXR", "DACL Switch", "DACL" },
2270 { "HPMIXR", "DACR Switch", "DACR" },
2271 { "HPMIXR", "MIXINL Switch", "MIXINL" },
2272 { "HPMIXR", "MIXINR Switch", "MIXINR" },
2273
2274 { "Left Bypass", NULL, "HPMIXL" },
2275 { "Left Bypass", NULL, "Class G" },
2276
2277 { "Right Bypass", NULL, "HPMIXR" },
2278 { "Right Bypass", NULL, "Class G" },
2279
2280 { "HPOUTL PGA", "Mixer", "Left Bypass" },
2281 { "HPOUTL PGA", "DAC", "DACL" },
2282
2283 { "HPOUTR PGA", "Mixer", "Right Bypass" },
2284 { "HPOUTR PGA", "DAC", "DACR" },
2285
2286 { "HPOUT", NULL, "HPOUTL PGA" },
2287 { "HPOUT", NULL, "HPOUTR PGA" },
2288 { "HPOUT", NULL, "Charge Pump" },
2289 { "HPOUT", NULL, "SYSCLK" },
2290 { "HPOUT", NULL, "TOCLK" },
2291
2292 { "HPOUTL", NULL, "HPOUT" },
2293 { "HPOUTR", NULL, "HPOUT" },
2294
2295 { "HPOUTL", NULL, "TEMP_HP" },
2296 { "HPOUTR", NULL, "TEMP_HP" },
2297 };
2298
2299 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2300 { "Speaker Mixer", "IN4L Switch", "IN4L" },
2301 { "Speaker Mixer", "IN4R Switch", "IN4R" },
2302 { "Speaker Mixer", "DACL Switch", "DACL" },
2303 { "Speaker Mixer", "DACR Switch", "DACR" },
2304 { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2305 { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2306
2307 { "Speaker PGA", "Mixer", "Speaker Mixer" },
2308 { "Speaker PGA", "DAC", "DACL" },
2309
2310 { "Speaker Output", NULL, "Speaker PGA" },
2311 { "Speaker Output", NULL, "SYSCLK" },
2312 { "Speaker Output", NULL, "TOCLK" },
2313 { "Speaker Output", NULL, "TEMP_SPK" },
2314
2315 { "SPKOUT", NULL, "Speaker Output" },
2316 };
2317
2318 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2319 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2320 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2321 { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2322 { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2323 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2324 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2325
2326 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2327 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2328 { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2329 { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2330 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2331 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2332
2333 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2334 { "SPKOUTL PGA", "DAC", "DACL" },
2335
2336 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2337 { "SPKOUTR PGA", "DAC", "DACR" },
2338
2339 { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2340 { "SPKOUTL Output", NULL, "SYSCLK" },
2341 { "SPKOUTL Output", NULL, "TOCLK" },
2342 { "SPKOUTL Output", NULL, "TEMP_SPK" },
2343
2344 { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2345 { "SPKOUTR Output", NULL, "SYSCLK" },
2346 { "SPKOUTR Output", NULL, "TOCLK" },
2347 { "SPKOUTR Output", NULL, "TEMP_SPK" },
2348
2349 { "SPKOUTL", NULL, "SPKOUTL Output" },
2350 { "SPKOUTR", NULL, "SPKOUTR Output" },
2351 };
2352
2353 static int wm8962_add_widgets(struct snd_soc_component *component)
2354 {
2355 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2356 struct wm8962_pdata *pdata = &wm8962->pdata;
2357 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2358
2359 snd_soc_add_component_controls(component, wm8962_snd_controls,
2360 ARRAY_SIZE(wm8962_snd_controls));
2361 if (pdata->spk_mono)
2362 snd_soc_add_component_controls(component, wm8962_spk_mono_controls,
2363 ARRAY_SIZE(wm8962_spk_mono_controls));
2364 else
2365 snd_soc_add_component_controls(component, wm8962_spk_stereo_controls,
2366 ARRAY_SIZE(wm8962_spk_stereo_controls));
2367
2368
2369 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
2370 ARRAY_SIZE(wm8962_dapm_widgets));
2371 if (pdata->spk_mono)
2372 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
2373 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2374 else
2375 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
2376 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2377
2378 snd_soc_dapm_add_routes(dapm, wm8962_intercon,
2379 ARRAY_SIZE(wm8962_intercon));
2380 if (pdata->spk_mono)
2381 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
2382 ARRAY_SIZE(wm8962_spk_mono_intercon));
2383 else
2384 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
2385 ARRAY_SIZE(wm8962_spk_stereo_intercon));
2386
2387
2388 snd_soc_dapm_disable_pin(dapm, "Beep");
2389
2390 return 0;
2391 }
2392
2393
2394 static const int bclk_divs[] = {
2395 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2396 };
2397
2398 static const int sysclk_rates[] = {
2399 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
2400 };
2401
2402 static void wm8962_configure_bclk(struct snd_soc_component *component)
2403 {
2404 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2405 int dspclk, i;
2406 int clocking2 = 0;
2407 int clocking4 = 0;
2408 int aif2 = 0;
2409
2410 if (!wm8962->sysclk_rate) {
2411 dev_dbg(component->dev, "No SYSCLK configured\n");
2412 return;
2413 }
2414
2415 if (!wm8962->bclk || !wm8962->lrclk) {
2416 dev_dbg(component->dev, "No audio clocks configured\n");
2417 return;
2418 }
2419
2420 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2421 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2422 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2423 break;
2424 }
2425 }
2426
2427 if (i == ARRAY_SIZE(sysclk_rates)) {
2428 dev_err(component->dev, "Unsupported sysclk ratio %d\n",
2429 wm8962->sysclk_rate / wm8962->lrclk);
2430 return;
2431 }
2432
2433 dev_dbg(component->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2434
2435 snd_soc_component_update_bits(component, WM8962_CLOCKING_4,
2436 WM8962_SYSCLK_RATE_MASK, clocking4);
2437
2438
2439
2440
2441
2442 if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
2443 snd_soc_component_update_bits(component, WM8962_CLOCKING2,
2444 WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
2445
2446 dspclk = snd_soc_component_read32(component, WM8962_CLOCKING1);
2447
2448 if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
2449 snd_soc_component_update_bits(component, WM8962_CLOCKING2,
2450 WM8962_SYSCLK_ENA_MASK, 0);
2451
2452 if (dspclk < 0) {
2453 dev_err(component->dev, "Failed to read DSPCLK: %d\n", dspclk);
2454 return;
2455 }
2456
2457 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2458 switch (dspclk) {
2459 case 0:
2460 dspclk = wm8962->sysclk_rate;
2461 break;
2462 case 1:
2463 dspclk = wm8962->sysclk_rate / 2;
2464 break;
2465 case 2:
2466 dspclk = wm8962->sysclk_rate / 4;
2467 break;
2468 default:
2469 dev_warn(component->dev, "Unknown DSPCLK divisor read back\n");
2470 dspclk = wm8962->sysclk_rate;
2471 }
2472
2473 dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2474
2475
2476 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2477 if (bclk_divs[i] < 0)
2478 continue;
2479
2480 if (dspclk / bclk_divs[i] == wm8962->bclk) {
2481 dev_dbg(component->dev, "Selected BCLK_DIV %d for %dHz\n",
2482 bclk_divs[i], wm8962->bclk);
2483 clocking2 |= i;
2484 break;
2485 }
2486 }
2487 if (i == ARRAY_SIZE(bclk_divs)) {
2488 dev_err(component->dev, "Unsupported BCLK ratio %d\n",
2489 dspclk / wm8962->bclk);
2490 return;
2491 }
2492
2493 aif2 |= wm8962->bclk / wm8962->lrclk;
2494 dev_dbg(component->dev, "Selected LRCLK divisor %d for %dHz\n",
2495 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2496
2497 snd_soc_component_update_bits(component, WM8962_CLOCKING2,
2498 WM8962_BCLK_DIV_MASK, clocking2);
2499 snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_2,
2500 WM8962_AIF_RATE_MASK, aif2);
2501 }
2502
2503 static int wm8962_set_bias_level(struct snd_soc_component *component,
2504 enum snd_soc_bias_level level)
2505 {
2506 switch (level) {
2507 case SND_SOC_BIAS_ON:
2508 break;
2509
2510 case SND_SOC_BIAS_PREPARE:
2511
2512 snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1,
2513 WM8962_VMID_SEL_MASK, 0x80);
2514
2515 wm8962_configure_bclk(component);
2516 break;
2517
2518 case SND_SOC_BIAS_STANDBY:
2519
2520 snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1,
2521 WM8962_VMID_SEL_MASK, 0x100);
2522
2523 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
2524 msleep(100);
2525 break;
2526
2527 case SND_SOC_BIAS_OFF:
2528 break;
2529 }
2530
2531 return 0;
2532 }
2533
2534 static const struct {
2535 int rate;
2536 int reg;
2537 } sr_vals[] = {
2538 { 48000, 0 },
2539 { 44100, 0 },
2540 { 32000, 1 },
2541 { 22050, 2 },
2542 { 24000, 2 },
2543 { 16000, 3 },
2544 { 11025, 4 },
2545 { 12000, 4 },
2546 { 8000, 5 },
2547 { 88200, 6 },
2548 { 96000, 6 },
2549 };
2550
2551 static int wm8962_hw_params(struct snd_pcm_substream *substream,
2552 struct snd_pcm_hw_params *params,
2553 struct snd_soc_dai *dai)
2554 {
2555 struct snd_soc_component *component = dai->component;
2556 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2557 int i;
2558 int aif0 = 0;
2559 int adctl3 = 0;
2560
2561 wm8962->bclk = snd_soc_params_to_bclk(params);
2562 if (params_channels(params) == 1)
2563 wm8962->bclk *= 2;
2564
2565 wm8962->lrclk = params_rate(params);
2566
2567 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
2568 if (sr_vals[i].rate == wm8962->lrclk) {
2569 adctl3 |= sr_vals[i].reg;
2570 break;
2571 }
2572 }
2573 if (i == ARRAY_SIZE(sr_vals)) {
2574 dev_err(component->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
2575 return -EINVAL;
2576 }
2577
2578 if (wm8962->lrclk % 8000 == 0)
2579 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2580
2581 switch (params_width(params)) {
2582 case 16:
2583 break;
2584 case 20:
2585 aif0 |= 0x4;
2586 break;
2587 case 24:
2588 aif0 |= 0x8;
2589 break;
2590 case 32:
2591 aif0 |= 0xc;
2592 break;
2593 default:
2594 return -EINVAL;
2595 }
2596
2597 snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0,
2598 WM8962_WL_MASK, aif0);
2599 snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_3,
2600 WM8962_SAMPLE_RATE_INT_MODE |
2601 WM8962_SAMPLE_RATE_MASK, adctl3);
2602
2603 dev_dbg(component->dev, "hw_params set BCLK %dHz LRCLK %dHz\n",
2604 wm8962->bclk, wm8962->lrclk);
2605
2606 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON)
2607 wm8962_configure_bclk(component);
2608
2609 return 0;
2610 }
2611
2612 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2613 unsigned int freq, int dir)
2614 {
2615 struct snd_soc_component *component = dai->component;
2616 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2617 int src;
2618
2619 switch (clk_id) {
2620 case WM8962_SYSCLK_MCLK:
2621 wm8962->sysclk = WM8962_SYSCLK_MCLK;
2622 src = 0;
2623 break;
2624 case WM8962_SYSCLK_FLL:
2625 wm8962->sysclk = WM8962_SYSCLK_FLL;
2626 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
2627 break;
2628 default:
2629 return -EINVAL;
2630 }
2631
2632 snd_soc_component_update_bits(component, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2633 src);
2634
2635 wm8962->sysclk_rate = freq;
2636
2637 return 0;
2638 }
2639
2640 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2641 {
2642 struct snd_soc_component *component = dai->component;
2643 int aif0 = 0;
2644
2645 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2646 case SND_SOC_DAIFMT_DSP_B:
2647 aif0 |= WM8962_LRCLK_INV | 3;
2648
2649 case SND_SOC_DAIFMT_DSP_A:
2650 aif0 |= 3;
2651
2652 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2653 case SND_SOC_DAIFMT_NB_NF:
2654 case SND_SOC_DAIFMT_IB_NF:
2655 break;
2656 default:
2657 return -EINVAL;
2658 }
2659 break;
2660
2661 case SND_SOC_DAIFMT_RIGHT_J:
2662 break;
2663 case SND_SOC_DAIFMT_LEFT_J:
2664 aif0 |= 1;
2665 break;
2666 case SND_SOC_DAIFMT_I2S:
2667 aif0 |= 2;
2668 break;
2669 default:
2670 return -EINVAL;
2671 }
2672
2673 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2674 case SND_SOC_DAIFMT_NB_NF:
2675 break;
2676 case SND_SOC_DAIFMT_IB_NF:
2677 aif0 |= WM8962_BCLK_INV;
2678 break;
2679 case SND_SOC_DAIFMT_NB_IF:
2680 aif0 |= WM8962_LRCLK_INV;
2681 break;
2682 case SND_SOC_DAIFMT_IB_IF:
2683 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2684 break;
2685 default:
2686 return -EINVAL;
2687 }
2688
2689 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2690 case SND_SOC_DAIFMT_CBM_CFM:
2691 aif0 |= WM8962_MSTR;
2692 break;
2693 case SND_SOC_DAIFMT_CBS_CFS:
2694 break;
2695 default:
2696 return -EINVAL;
2697 }
2698
2699 snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0,
2700 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2701 WM8962_LRCLK_INV, aif0);
2702
2703 return 0;
2704 }
2705
2706 struct _fll_div {
2707 u16 fll_fratio;
2708 u16 fll_outdiv;
2709 u16 fll_refclk_div;
2710 u16 n;
2711 u16 theta;
2712 u16 lambda;
2713 };
2714
2715
2716
2717 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2718
2719 static struct {
2720 unsigned int min;
2721 unsigned int max;
2722 u16 fll_fratio;
2723 int ratio;
2724 } fll_fratios[] = {
2725 { 0, 64000, 4, 16 },
2726 { 64000, 128000, 3, 8 },
2727 { 128000, 256000, 2, 4 },
2728 { 256000, 1000000, 1, 2 },
2729 { 1000000, 13500000, 0, 1 },
2730 };
2731
2732 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2733 unsigned int Fout)
2734 {
2735 unsigned int target;
2736 unsigned int div;
2737 unsigned int fratio, gcd_fll;
2738 int i;
2739
2740
2741 div = 1;
2742 fll_div->fll_refclk_div = 0;
2743 while ((Fref / div) > 13500000) {
2744 div *= 2;
2745 fll_div->fll_refclk_div++;
2746
2747 if (div > 4) {
2748 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2749 Fref);
2750 return -EINVAL;
2751 }
2752 }
2753
2754 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2755
2756
2757 Fref /= div;
2758
2759
2760 div = 2;
2761 while (Fout * div < 90000000) {
2762 div++;
2763 if (div > 64) {
2764 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2765 Fout);
2766 return -EINVAL;
2767 }
2768 }
2769 target = Fout * div;
2770 fll_div->fll_outdiv = div - 1;
2771
2772 pr_debug("FLL Fvco=%dHz\n", target);
2773
2774
2775 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2776 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2777 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2778 fratio = fll_fratios[i].ratio;
2779 break;
2780 }
2781 }
2782 if (i == ARRAY_SIZE(fll_fratios)) {
2783 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2784 return -EINVAL;
2785 }
2786
2787 fll_div->n = target / (fratio * Fref);
2788
2789 if (target % Fref == 0) {
2790 fll_div->theta = 0;
2791 fll_div->lambda = 1;
2792 } else {
2793 gcd_fll = gcd(target, fratio * Fref);
2794
2795 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2796 / gcd_fll;
2797 fll_div->lambda = (fratio * Fref) / gcd_fll;
2798 }
2799
2800 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2801 fll_div->n, fll_div->theta, fll_div->lambda);
2802 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2803 fll_div->fll_fratio, fll_div->fll_outdiv,
2804 fll_div->fll_refclk_div);
2805
2806 return 0;
2807 }
2808
2809 static int wm8962_set_fll(struct snd_soc_component *component, int fll_id, int source,
2810 unsigned int Fref, unsigned int Fout)
2811 {
2812 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2813 struct _fll_div fll_div;
2814 unsigned long timeout;
2815 int ret;
2816 int fll1 = 0;
2817
2818
2819 if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2820 Fout == wm8962->fll_fout)
2821 return 0;
2822
2823 if (Fout == 0) {
2824 dev_dbg(component->dev, "FLL disabled\n");
2825
2826 wm8962->fll_fref = 0;
2827 wm8962->fll_fout = 0;
2828
2829 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2830 WM8962_FLL_ENA, 0);
2831
2832 pm_runtime_put(component->dev);
2833
2834 return 0;
2835 }
2836
2837 ret = fll_factors(&fll_div, Fref, Fout);
2838 if (ret != 0)
2839 return ret;
2840
2841
2842 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2843
2844 switch (fll_id) {
2845 case WM8962_FLL_MCLK:
2846 case WM8962_FLL_BCLK:
2847 case WM8962_FLL_OSC:
2848 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2849 break;
2850 case WM8962_FLL_INT:
2851 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2852 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2853 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_5,
2854 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2855 break;
2856 default:
2857 dev_err(component->dev, "Unknown FLL source %d\n", ret);
2858 return -EINVAL;
2859 }
2860
2861 if (fll_div.theta)
2862 fll1 |= WM8962_FLL_FRAC;
2863
2864
2865 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2866
2867 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_2,
2868 WM8962_FLL_OUTDIV_MASK |
2869 WM8962_FLL_REFCLK_DIV_MASK,
2870 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2871 (fll_div.fll_refclk_div));
2872
2873 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_3,
2874 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2875
2876 snd_soc_component_write(component, WM8962_FLL_CONTROL_6, fll_div.theta);
2877 snd_soc_component_write(component, WM8962_FLL_CONTROL_7, fll_div.lambda);
2878 snd_soc_component_write(component, WM8962_FLL_CONTROL_8, fll_div.n);
2879
2880 reinit_completion(&wm8962->fll_lock);
2881
2882 ret = pm_runtime_get_sync(component->dev);
2883 if (ret < 0) {
2884 dev_err(component->dev, "Failed to resume device: %d\n", ret);
2885 return ret;
2886 }
2887
2888 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2889 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
2890 WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
2891
2892 dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2893
2894
2895
2896
2897 if (wm8962->irq)
2898 timeout = msecs_to_jiffies(5);
2899 else
2900 timeout = msecs_to_jiffies(1);
2901
2902 timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2903 timeout);
2904
2905 if (timeout == 0 && wm8962->irq) {
2906 dev_err(component->dev, "FLL lock timed out");
2907 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2908 WM8962_FLL_ENA, 0);
2909 pm_runtime_put(component->dev);
2910 return -ETIMEDOUT;
2911 }
2912
2913 wm8962->fll_fref = Fref;
2914 wm8962->fll_fout = Fout;
2915 wm8962->fll_src = source;
2916
2917 return 0;
2918 }
2919
2920 static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2921 {
2922 struct snd_soc_component *component = dai->component;
2923 int val, ret;
2924
2925 if (mute)
2926 val = WM8962_DAC_MUTE | WM8962_DAC_MUTE_ALT;
2927 else
2928 val = 0;
2929
2930
2931
2932
2933
2934 ret = snd_soc_component_update_bits(component, WM8962_CLASS_D_CONTROL_1,
2935 WM8962_DAC_MUTE_ALT, val);
2936 if (ret < 0)
2937 return ret;
2938
2939 return snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
2940 WM8962_DAC_MUTE, val);
2941 }
2942
2943 #define WM8962_RATES (SNDRV_PCM_RATE_8000_48000 |\
2944 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
2945
2946 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2947 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2948
2949 static const struct snd_soc_dai_ops wm8962_dai_ops = {
2950 .hw_params = wm8962_hw_params,
2951 .set_sysclk = wm8962_set_dai_sysclk,
2952 .set_fmt = wm8962_set_dai_fmt,
2953 .digital_mute = wm8962_mute,
2954 };
2955
2956 static struct snd_soc_dai_driver wm8962_dai = {
2957 .name = "wm8962",
2958 .playback = {
2959 .stream_name = "Playback",
2960 .channels_min = 1,
2961 .channels_max = 2,
2962 .rates = WM8962_RATES,
2963 .formats = WM8962_FORMATS,
2964 },
2965 .capture = {
2966 .stream_name = "Capture",
2967 .channels_min = 1,
2968 .channels_max = 2,
2969 .rates = WM8962_RATES,
2970 .formats = WM8962_FORMATS,
2971 },
2972 .ops = &wm8962_dai_ops,
2973 .symmetric_rates = 1,
2974 };
2975
2976 static void wm8962_mic_work(struct work_struct *work)
2977 {
2978 struct wm8962_priv *wm8962 = container_of(work,
2979 struct wm8962_priv,
2980 mic_work.work);
2981 struct snd_soc_component *component = wm8962->component;
2982 int status = 0;
2983 int irq_pol = 0;
2984 int reg;
2985
2986 reg = snd_soc_component_read32(component, WM8962_ADDITIONAL_CONTROL_4);
2987
2988 if (reg & WM8962_MICDET_STS) {
2989 status |= SND_JACK_MICROPHONE;
2990 irq_pol |= WM8962_MICD_IRQ_POL;
2991 }
2992
2993 if (reg & WM8962_MICSHORT_STS) {
2994 status |= SND_JACK_BTN_0;
2995 irq_pol |= WM8962_MICSCD_IRQ_POL;
2996 }
2997
2998 snd_soc_jack_report(wm8962->jack, status,
2999 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3000
3001 snd_soc_component_update_bits(component, WM8962_MICINT_SOURCE_POL,
3002 WM8962_MICSCD_IRQ_POL |
3003 WM8962_MICD_IRQ_POL, irq_pol);
3004 }
3005
3006 static irqreturn_t wm8962_irq(int irq, void *data)
3007 {
3008 struct device *dev = data;
3009 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3010 unsigned int mask;
3011 unsigned int active;
3012 int reg, ret;
3013
3014 ret = pm_runtime_get_sync(dev);
3015 if (ret < 0) {
3016 dev_err(dev, "Failed to resume: %d\n", ret);
3017 return IRQ_NONE;
3018 }
3019
3020 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
3021 &mask);
3022 if (ret != 0) {
3023 pm_runtime_put(dev);
3024 dev_err(dev, "Failed to read interrupt mask: %d\n",
3025 ret);
3026 return IRQ_NONE;
3027 }
3028
3029 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
3030 if (ret != 0) {
3031 pm_runtime_put(dev);
3032 dev_err(dev, "Failed to read interrupt: %d\n", ret);
3033 return IRQ_NONE;
3034 }
3035
3036 active &= ~mask;
3037
3038 if (!active) {
3039 pm_runtime_put(dev);
3040 return IRQ_NONE;
3041 }
3042
3043
3044 ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
3045 if (ret != 0)
3046 dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
3047
3048 if (active & WM8962_FLL_LOCK_EINT) {
3049 dev_dbg(dev, "FLL locked\n");
3050 complete(&wm8962->fll_lock);
3051 }
3052
3053 if (active & WM8962_FIFOS_ERR_EINT)
3054 dev_err(dev, "FIFO error\n");
3055
3056 if (active & WM8962_TEMP_SHUT_EINT) {
3057 dev_crit(dev, "Thermal shutdown\n");
3058
3059 ret = regmap_read(wm8962->regmap,
3060 WM8962_THERMAL_SHUTDOWN_STATUS, ®);
3061 if (ret != 0) {
3062 dev_warn(dev, "Failed to read thermal status: %d\n",
3063 ret);
3064 reg = 0;
3065 }
3066
3067 if (reg & WM8962_TEMP_ERR_HP)
3068 dev_crit(dev, "Headphone thermal error\n");
3069 if (reg & WM8962_TEMP_WARN_HP)
3070 dev_crit(dev, "Headphone thermal warning\n");
3071 if (reg & WM8962_TEMP_ERR_SPK)
3072 dev_crit(dev, "Speaker thermal error\n");
3073 if (reg & WM8962_TEMP_WARN_SPK)
3074 dev_crit(dev, "Speaker thermal warning\n");
3075 }
3076
3077 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3078 dev_dbg(dev, "Microphone event detected\n");
3079
3080 #ifndef CONFIG_SND_SOC_WM8962_MODULE
3081 trace_snd_soc_jack_irq(dev_name(dev));
3082 #endif
3083
3084 pm_wakeup_event(dev, 300);
3085
3086 queue_delayed_work(system_power_efficient_wq,
3087 &wm8962->mic_work,
3088 msecs_to_jiffies(250));
3089 }
3090
3091 pm_runtime_put(dev);
3092
3093 return IRQ_HANDLED;
3094 }
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109 int wm8962_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack)
3110 {
3111 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3112 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3113 int irq_mask, enable;
3114
3115 wm8962->jack = jack;
3116 if (jack) {
3117 irq_mask = 0;
3118 enable = WM8962_MICDET_ENA;
3119 } else {
3120 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3121 enable = 0;
3122 }
3123
3124 snd_soc_component_update_bits(component, WM8962_INTERRUPT_STATUS_2_MASK,
3125 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3126 snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_4,
3127 WM8962_MICDET_ENA, enable);
3128
3129
3130 snd_soc_jack_report(wm8962->jack, 0,
3131 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3132
3133 snd_soc_dapm_mutex_lock(dapm);
3134
3135 if (jack) {
3136 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
3137 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
3138 } else {
3139 snd_soc_dapm_disable_pin_unlocked(dapm, "SYSCLK");
3140 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
3141 }
3142
3143 snd_soc_dapm_mutex_unlock(dapm);
3144
3145 return 0;
3146 }
3147 EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3148
3149 static int beep_rates[] = {
3150 500, 1000, 2000, 4000,
3151 };
3152
3153 static void wm8962_beep_work(struct work_struct *work)
3154 {
3155 struct wm8962_priv *wm8962 =
3156 container_of(work, struct wm8962_priv, beep_work);
3157 struct snd_soc_component *component = wm8962->component;
3158 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3159 int i;
3160 int reg = 0;
3161 int best = 0;
3162
3163 if (wm8962->beep_rate) {
3164 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3165 if (abs(wm8962->beep_rate - beep_rates[i]) <
3166 abs(wm8962->beep_rate - beep_rates[best]))
3167 best = i;
3168 }
3169
3170 dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n",
3171 beep_rates[best], wm8962->beep_rate);
3172
3173 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3174
3175 snd_soc_dapm_enable_pin(dapm, "Beep");
3176 } else {
3177 dev_dbg(component->dev, "Disabling beep\n");
3178 snd_soc_dapm_disable_pin(dapm, "Beep");
3179 }
3180
3181 snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1,
3182 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3183
3184 snd_soc_dapm_sync(dapm);
3185 }
3186
3187
3188
3189
3190 static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3191 unsigned int code, int hz)
3192 {
3193 struct snd_soc_component *component = input_get_drvdata(dev);
3194 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3195
3196 dev_dbg(component->dev, "Beep event %x %x\n", code, hz);
3197
3198 switch (code) {
3199 case SND_BELL:
3200 if (hz)
3201 hz = 1000;
3202 case SND_TONE:
3203 break;
3204 default:
3205 return -1;
3206 }
3207
3208
3209 wm8962->beep_rate = hz;
3210 schedule_work(&wm8962->beep_work);
3211 return 0;
3212 }
3213
3214 static ssize_t wm8962_beep_set(struct device *dev,
3215 struct device_attribute *attr,
3216 const char *buf, size_t count)
3217 {
3218 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3219 long int time;
3220 int ret;
3221
3222 ret = kstrtol(buf, 10, &time);
3223 if (ret != 0)
3224 return ret;
3225
3226 input_event(wm8962->beep, EV_SND, SND_TONE, time);
3227
3228 return count;
3229 }
3230
3231 static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
3232
3233 static void wm8962_init_beep(struct snd_soc_component *component)
3234 {
3235 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3236 int ret;
3237
3238 wm8962->beep = devm_input_allocate_device(component->dev);
3239 if (!wm8962->beep) {
3240 dev_err(component->dev, "Failed to allocate beep device\n");
3241 return;
3242 }
3243
3244 INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3245 wm8962->beep_rate = 0;
3246
3247 wm8962->beep->name = "WM8962 Beep Generator";
3248 wm8962->beep->phys = dev_name(component->dev);
3249 wm8962->beep->id.bustype = BUS_I2C;
3250
3251 wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3252 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3253 wm8962->beep->event = wm8962_beep_event;
3254 wm8962->beep->dev.parent = component->dev;
3255 input_set_drvdata(wm8962->beep, component);
3256
3257 ret = input_register_device(wm8962->beep);
3258 if (ret != 0) {
3259 wm8962->beep = NULL;
3260 dev_err(component->dev, "Failed to register beep device\n");
3261 }
3262
3263 ret = device_create_file(component->dev, &dev_attr_beep);
3264 if (ret != 0) {
3265 dev_err(component->dev, "Failed to create keyclick file: %d\n",
3266 ret);
3267 }
3268 }
3269
3270 static void wm8962_free_beep(struct snd_soc_component *component)
3271 {
3272 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3273
3274 device_remove_file(component->dev, &dev_attr_beep);
3275 cancel_work_sync(&wm8962->beep_work);
3276 wm8962->beep = NULL;
3277
3278 snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3279 }
3280
3281 static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio)
3282 {
3283 int mask = 0;
3284 int val = 0;
3285
3286
3287
3288 switch (gpio) {
3289 case 2:
3290 mask = WM8962_CLKOUT2_SEL_MASK;
3291 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3292 break;
3293 case 3:
3294 mask = WM8962_CLKOUT3_SEL_MASK;
3295 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3296 break;
3297 default:
3298 break;
3299 }
3300
3301 if (mask)
3302 regmap_update_bits(wm8962->regmap, WM8962_ANALOGUE_CLOCKING1,
3303 mask, val);
3304 }
3305
3306 #ifdef CONFIG_GPIOLIB
3307 static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3308 {
3309 struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
3310
3311
3312
3313
3314
3315 switch (offset + 1) {
3316 case 2:
3317 case 3:
3318 case 5:
3319 case 6:
3320 break;
3321 default:
3322 return -EINVAL;
3323 }
3324
3325 wm8962_set_gpio_mode(wm8962, offset + 1);
3326
3327 return 0;
3328 }
3329
3330 static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3331 {
3332 struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
3333 struct snd_soc_component *component = wm8962->component;
3334
3335 snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset,
3336 WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
3337 }
3338
3339 static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3340 unsigned offset, int value)
3341 {
3342 struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
3343 struct snd_soc_component *component = wm8962->component;
3344 int ret, val;
3345
3346
3347 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3348
3349 ret = snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset,
3350 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3351 if (ret < 0)
3352 return ret;
3353
3354 return 0;
3355 }
3356
3357 static const struct gpio_chip wm8962_template_chip = {
3358 .label = "wm8962",
3359 .owner = THIS_MODULE,
3360 .request = wm8962_gpio_request,
3361 .direction_output = wm8962_gpio_direction_out,
3362 .set = wm8962_gpio_set,
3363 .can_sleep = 1,
3364 };
3365
3366 static void wm8962_init_gpio(struct snd_soc_component *component)
3367 {
3368 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3369 struct wm8962_pdata *pdata = &wm8962->pdata;
3370 int ret;
3371
3372 wm8962->gpio_chip = wm8962_template_chip;
3373 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3374 wm8962->gpio_chip.parent = component->dev;
3375
3376 if (pdata->gpio_base)
3377 wm8962->gpio_chip.base = pdata->gpio_base;
3378 else
3379 wm8962->gpio_chip.base = -1;
3380
3381 ret = gpiochip_add_data(&wm8962->gpio_chip, wm8962);
3382 if (ret != 0)
3383 dev_err(component->dev, "Failed to add GPIOs: %d\n", ret);
3384 }
3385
3386 static void wm8962_free_gpio(struct snd_soc_component *component)
3387 {
3388 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3389
3390 gpiochip_remove(&wm8962->gpio_chip);
3391 }
3392 #else
3393 static void wm8962_init_gpio(struct snd_soc_component *component)
3394 {
3395 }
3396
3397 static void wm8962_free_gpio(struct snd_soc_component *component)
3398 {
3399 }
3400 #endif
3401
3402 static int wm8962_probe(struct snd_soc_component *component)
3403 {
3404 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3405 int ret;
3406 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3407 int i;
3408 bool dmicclk, dmicdat;
3409
3410 wm8962->component = component;
3411
3412 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3413 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3414 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3415 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3416 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3417 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3418 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3419 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3420
3421
3422 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3423 ret = devm_regulator_register_notifier(
3424 wm8962->supplies[i].consumer,
3425 &wm8962->disable_nb[i]);
3426 if (ret != 0) {
3427 dev_err(component->dev,
3428 "Failed to register regulator notifier: %d\n",
3429 ret);
3430 }
3431 }
3432
3433 wm8962_add_widgets(component);
3434
3435
3436 dmicclk = false;
3437 dmicdat = false;
3438 for (i = 0; i < WM8962_MAX_GPIO; i++) {
3439 switch (snd_soc_component_read32(component, WM8962_GPIO_BASE + i)
3440 & WM8962_GP2_FN_MASK) {
3441 case WM8962_GPIO_FN_DMICCLK:
3442 dmicclk = true;
3443 break;
3444 case WM8962_GPIO_FN_DMICDAT:
3445 dmicdat = true;
3446 break;
3447 default:
3448 break;
3449 }
3450 }
3451 if (!dmicclk || !dmicdat) {
3452 dev_dbg(component->dev, "DMIC not in use, disabling\n");
3453 snd_soc_dapm_nc_pin(dapm, "DMICDAT");
3454 }
3455 if (dmicclk != dmicdat)
3456 dev_warn(component->dev, "DMIC GPIOs partially configured\n");
3457
3458 wm8962_init_beep(component);
3459 wm8962_init_gpio(component);
3460
3461 return 0;
3462 }
3463
3464 static void wm8962_remove(struct snd_soc_component *component)
3465 {
3466 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3467
3468 cancel_delayed_work_sync(&wm8962->mic_work);
3469
3470 wm8962_free_gpio(component);
3471 wm8962_free_beep(component);
3472 }
3473
3474 static const struct snd_soc_component_driver soc_component_dev_wm8962 = {
3475 .probe = wm8962_probe,
3476 .remove = wm8962_remove,
3477 .set_bias_level = wm8962_set_bias_level,
3478 .set_pll = wm8962_set_fll,
3479 .use_pmdown_time = 1,
3480 .endianness = 1,
3481 .non_legacy_dai_naming = 1,
3482 };
3483
3484
3485 static const struct reg_sequence wm8962_dc_measure[] = {
3486 { 0xfd, 0x1 },
3487 { 0xcc, 0x40 },
3488 { 0xfd, 0 },
3489 };
3490
3491 static const struct regmap_config wm8962_regmap = {
3492 .reg_bits = 16,
3493 .val_bits = 16,
3494
3495 .max_register = WM8962_MAX_REGISTER,
3496 .reg_defaults = wm8962_reg,
3497 .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3498 .volatile_reg = wm8962_volatile_register,
3499 .readable_reg = wm8962_readable_register,
3500 .cache_type = REGCACHE_RBTREE,
3501 };
3502
3503 static int wm8962_set_pdata_from_of(struct i2c_client *i2c,
3504 struct wm8962_pdata *pdata)
3505 {
3506 const struct device_node *np = i2c->dev.of_node;
3507 u32 val32;
3508 int i;
3509
3510 if (of_property_read_bool(np, "spk-mono"))
3511 pdata->spk_mono = true;
3512
3513 if (of_property_read_u32(np, "mic-cfg", &val32) >= 0)
3514 pdata->mic_cfg = val32;
3515
3516 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init,
3517 ARRAY_SIZE(pdata->gpio_init)) >= 0)
3518 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) {
3519
3520
3521
3522
3523
3524 if (pdata->gpio_init[i] > 0xffff)
3525 pdata->gpio_init[i] = 0x0;
3526 }
3527
3528 pdata->mclk = devm_clk_get(&i2c->dev, NULL);
3529
3530 return 0;
3531 }
3532
3533 static int wm8962_i2c_probe(struct i2c_client *i2c,
3534 const struct i2c_device_id *id)
3535 {
3536 struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
3537 struct wm8962_priv *wm8962;
3538 unsigned int reg;
3539 int ret, i, irq_pol, trigger;
3540
3541 wm8962 = devm_kzalloc(&i2c->dev, sizeof(*wm8962), GFP_KERNEL);
3542 if (wm8962 == NULL)
3543 return -ENOMEM;
3544
3545 mutex_init(&wm8962->dsp2_ena_lock);
3546
3547 i2c_set_clientdata(i2c, wm8962);
3548
3549 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3550 init_completion(&wm8962->fll_lock);
3551 wm8962->irq = i2c->irq;
3552
3553
3554 if (pdata) {
3555 memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata));
3556 } else if (i2c->dev.of_node) {
3557 ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata);
3558 if (ret != 0)
3559 return ret;
3560 }
3561
3562
3563 if (IS_ERR(wm8962->pdata.mclk)) {
3564
3565 if (PTR_ERR(wm8962->pdata.mclk) == -EPROBE_DEFER)
3566 return -EPROBE_DEFER;
3567 wm8962->pdata.mclk = NULL;
3568 }
3569
3570 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3571 wm8962->supplies[i].supply = wm8962_supply_names[i];
3572
3573 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
3574 wm8962->supplies);
3575 if (ret != 0) {
3576 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3577 goto err;
3578 }
3579
3580 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3581 wm8962->supplies);
3582 if (ret != 0) {
3583 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3584 return ret;
3585 }
3586
3587 wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap);
3588 if (IS_ERR(wm8962->regmap)) {
3589 ret = PTR_ERR(wm8962->regmap);
3590 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3591 goto err_enable;
3592 }
3593
3594
3595
3596
3597
3598
3599 regcache_cache_bypass(wm8962->regmap, true);
3600
3601 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, ®);
3602 if (ret < 0) {
3603 dev_err(&i2c->dev, "Failed to read ID register\n");
3604 goto err_enable;
3605 }
3606 if (reg != 0x6243) {
3607 dev_err(&i2c->dev,
3608 "Device is not a WM8962, ID %x != 0x6243\n", reg);
3609 ret = -EINVAL;
3610 goto err_enable;
3611 }
3612
3613 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, ®);
3614 if (ret < 0) {
3615 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3616 ret);
3617 goto err_enable;
3618 }
3619
3620 dev_info(&i2c->dev, "customer id %x revision %c\n",
3621 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3622 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3623 + 'A');
3624
3625 regcache_cache_bypass(wm8962->regmap, false);
3626
3627 ret = wm8962_reset(wm8962);
3628 if (ret < 0) {
3629 dev_err(&i2c->dev, "Failed to issue reset\n");
3630 goto err_enable;
3631 }
3632
3633
3634
3635
3636 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3637 WM8962_SYSCLK_ENA, 0);
3638
3639
3640 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3641 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3642
3643
3644 regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3645 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3646 0);
3647
3648
3649 for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++)
3650 if (wm8962->pdata.gpio_init[i]) {
3651 wm8962_set_gpio_mode(wm8962, i + 1);
3652 regmap_write(wm8962->regmap, 0x200 + i,
3653 wm8962->pdata.gpio_init[i] & 0xffff);
3654 }
3655
3656
3657
3658 if (wm8962->pdata.spk_mono)
3659 regmap_update_bits(wm8962->regmap, WM8962_CLASS_D_CONTROL_2,
3660 WM8962_SPK_MONO_MASK, WM8962_SPK_MONO);
3661
3662
3663
3664 if (wm8962->pdata.mic_cfg)
3665 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3666 WM8962_MICDET_ENA |
3667 WM8962_MICDET_THR_MASK |
3668 WM8962_MICSHORT_THR_MASK |
3669 WM8962_MICBIAS_LVL,
3670 wm8962->pdata.mic_cfg);
3671
3672
3673 regmap_update_bits(wm8962->regmap, WM8962_LEFT_INPUT_VOLUME,
3674 WM8962_IN_VU, WM8962_IN_VU);
3675 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME,
3676 WM8962_IN_VU, WM8962_IN_VU);
3677 regmap_update_bits(wm8962->regmap, WM8962_LEFT_ADC_VOLUME,
3678 WM8962_ADC_VU, WM8962_ADC_VU);
3679 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_ADC_VOLUME,
3680 WM8962_ADC_VU, WM8962_ADC_VU);
3681 regmap_update_bits(wm8962->regmap, WM8962_LEFT_DAC_VOLUME,
3682 WM8962_DAC_VU, WM8962_DAC_VU);
3683 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_DAC_VOLUME,
3684 WM8962_DAC_VU, WM8962_DAC_VU);
3685 regmap_update_bits(wm8962->regmap, WM8962_SPKOUTL_VOLUME,
3686 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3687 regmap_update_bits(wm8962->regmap, WM8962_SPKOUTR_VOLUME,
3688 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3689 regmap_update_bits(wm8962->regmap, WM8962_HPOUTL_VOLUME,
3690 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3691 regmap_update_bits(wm8962->regmap, WM8962_HPOUTR_VOLUME,
3692 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3693
3694
3695 regmap_update_bits(wm8962->regmap, WM8962_EQ1,
3696 WM8962_EQ_SHARED_COEFF, 0);
3697
3698
3699 regmap_update_bits(wm8962->regmap, WM8962_IRQ_DEBOUNCE,
3700 WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3701 WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3702 0);
3703
3704 if (wm8962->pdata.in4_dc_measure) {
3705 ret = regmap_register_patch(wm8962->regmap,
3706 wm8962_dc_measure,
3707 ARRAY_SIZE(wm8962_dc_measure));
3708 if (ret != 0)
3709 dev_err(&i2c->dev,
3710 "Failed to configure for DC measurement: %d\n",
3711 ret);
3712 }
3713
3714 if (wm8962->irq) {
3715 if (wm8962->pdata.irq_active_low) {
3716 trigger = IRQF_TRIGGER_LOW;
3717 irq_pol = WM8962_IRQ_POL;
3718 } else {
3719 trigger = IRQF_TRIGGER_HIGH;
3720 irq_pol = 0;
3721 }
3722
3723 regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL,
3724 WM8962_IRQ_POL, irq_pol);
3725
3726 ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL,
3727 wm8962_irq,
3728 trigger | IRQF_ONESHOT,
3729 "wm8962", &i2c->dev);
3730 if (ret != 0) {
3731 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
3732 wm8962->irq, ret);
3733 wm8962->irq = 0;
3734
3735 } else {
3736
3737 regmap_update_bits(wm8962->regmap,
3738 WM8962_INTERRUPT_STATUS_2_MASK,
3739 WM8962_FLL_LOCK_EINT |
3740 WM8962_TEMP_SHUT_EINT |
3741 WM8962_FIFOS_ERR_EINT, 0);
3742 }
3743 }
3744
3745 pm_runtime_enable(&i2c->dev);
3746 pm_request_idle(&i2c->dev);
3747
3748 ret = devm_snd_soc_register_component(&i2c->dev,
3749 &soc_component_dev_wm8962, &wm8962_dai, 1);
3750 if (ret < 0)
3751 goto err_pm_runtime;
3752
3753 regcache_cache_only(wm8962->regmap, true);
3754
3755
3756 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3757
3758 return 0;
3759
3760 err_pm_runtime:
3761 pm_runtime_disable(&i2c->dev);
3762 err_enable:
3763 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3764 err:
3765 return ret;
3766 }
3767
3768 static int wm8962_i2c_remove(struct i2c_client *client)
3769 {
3770 pm_runtime_disable(&client->dev);
3771 return 0;
3772 }
3773
3774 #ifdef CONFIG_PM
3775 static int wm8962_runtime_resume(struct device *dev)
3776 {
3777 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3778 int ret;
3779
3780 ret = clk_prepare_enable(wm8962->pdata.mclk);
3781 if (ret) {
3782 dev_err(dev, "Failed to enable MCLK: %d\n", ret);
3783 return ret;
3784 }
3785
3786 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3787 wm8962->supplies);
3788 if (ret != 0) {
3789 dev_err(dev, "Failed to enable supplies: %d\n", ret);
3790 goto disable_clock;
3791 }
3792
3793 regcache_cache_only(wm8962->regmap, false);
3794
3795 wm8962_reset(wm8962);
3796
3797 regcache_mark_dirty(wm8962->regmap);
3798
3799
3800
3801
3802 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3803 WM8962_SYSCLK_ENA, 0);
3804
3805
3806 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3807 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3808
3809
3810 regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3811 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3812 0);
3813
3814 regcache_sync(wm8962->regmap);
3815
3816 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3817 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
3818 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
3819
3820
3821 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3822 WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK,
3823 WM8962_BIAS_ENA | 0x180);
3824
3825 msleep(5);
3826
3827 return 0;
3828
3829 disable_clock:
3830 clk_disable_unprepare(wm8962->pdata.mclk);
3831 return ret;
3832 }
3833
3834 static int wm8962_runtime_suspend(struct device *dev)
3835 {
3836 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3837
3838 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3839 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3840
3841 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3842 WM8962_STARTUP_BIAS_ENA |
3843 WM8962_VMID_BUF_ENA, 0);
3844
3845 regcache_cache_only(wm8962->regmap, true);
3846
3847 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3848 wm8962->supplies);
3849
3850 clk_disable_unprepare(wm8962->pdata.mclk);
3851
3852 return 0;
3853 }
3854 #endif
3855
3856 static const struct dev_pm_ops wm8962_pm = {
3857 SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3858 };
3859
3860 static const struct i2c_device_id wm8962_i2c_id[] = {
3861 { "wm8962", 0 },
3862 { }
3863 };
3864 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3865
3866 static const struct of_device_id wm8962_of_match[] = {
3867 { .compatible = "wlf,wm8962", },
3868 { }
3869 };
3870 MODULE_DEVICE_TABLE(of, wm8962_of_match);
3871
3872 static struct i2c_driver wm8962_i2c_driver = {
3873 .driver = {
3874 .name = "wm8962",
3875 .of_match_table = wm8962_of_match,
3876 .pm = &wm8962_pm,
3877 },
3878 .probe = wm8962_i2c_probe,
3879 .remove = wm8962_i2c_remove,
3880 .id_table = wm8962_i2c_id,
3881 };
3882
3883 module_i2c_driver(wm8962_i2c_driver);
3884
3885 MODULE_DESCRIPTION("ASoC WM8962 driver");
3886 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3887 MODULE_LICENSE("GPL");