root/sound/soc/codecs/cs35l32.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * cs35l32.h -- CS35L32 ALSA SoC audio driver
   4  *
   5  * Copyright 2014 CirrusLogic, Inc.
   6  *
   7  * Author: Brian Austin <brian.austin@cirrus.com>
   8  */
   9 
  10 #ifndef __CS35L32_H__
  11 #define __CS35L32_H__
  12 
  13 struct cs35l32_platform_data {
  14         /* Low Battery Threshold */
  15         unsigned int batt_thresh;
  16         /* Low Battery Recovery */
  17         unsigned int batt_recov;
  18         /* LED Current Management*/
  19         unsigned int led_mng;
  20         /* Audio Gain w/ LED */
  21         unsigned int audiogain_mng;
  22         /* Boost Management */
  23         unsigned int boost_mng;
  24         /* Data CFG for DUAL device */
  25         unsigned int sdout_datacfg;
  26         /* SDOUT Sharing */
  27         unsigned int sdout_share;
  28 };
  29 
  30 #define CS35L32_CHIP_ID         0x00035A32
  31 #define CS35L32_DEVID_AB        0x01    /* Device ID A & B [RO] */
  32 #define CS35L32_DEVID_CD        0x02    /* Device ID C & D [RO] */
  33 #define CS35L32_DEVID_E         0x03    /* Device ID E [RO] */
  34 #define CS35L32_FAB_ID          0x04    /* Fab ID [RO] */
  35 #define CS35L32_REV_ID          0x05    /* Revision ID [RO] */
  36 #define CS35L32_PWRCTL1         0x06    /* Power Ctl 1 */
  37 #define CS35L32_PWRCTL2         0x07    /* Power Ctl 2 */
  38 #define CS35L32_CLK_CTL         0x08    /* Clock Ctl */
  39 #define CS35L32_BATT_THRESHOLD  0x09    /* Low Battery Threshold */
  40 #define CS35L32_VMON            0x0A    /* Voltage Monitor [RO] */
  41 #define CS35L32_BST_CPCP_CTL    0x0B    /* Conv Peak Curr Protection CTL */
  42 #define CS35L32_IMON_SCALING    0x0C    /* IMON Scaling */
  43 #define CS35L32_AUDIO_LED_MNGR  0x0D    /* Audio/LED Pwr Manager */
  44 #define CS35L32_ADSP_CTL        0x0F    /* Serial Port Control */
  45 #define CS35L32_CLASSD_CTL      0x10    /* Class D Amp CTL */
  46 #define CS35L32_PROTECT_CTL     0x11    /* Protection Release CTL */
  47 #define CS35L32_INT_MASK_1      0x12    /* Interrupt Mask 1 */
  48 #define CS35L32_INT_MASK_2      0x13    /* Interrupt Mask 2 */
  49 #define CS35L32_INT_MASK_3      0x14    /* Interrupt Mask 3 */
  50 #define CS35L32_INT_STATUS_1    0x15    /* Interrupt Status 1 [RO] */
  51 #define CS35L32_INT_STATUS_2    0x16    /* Interrupt Status 2 [RO] */
  52 #define CS35L32_INT_STATUS_3    0x17    /* Interrupt Status 3 [RO] */
  53 #define CS35L32_LED_STATUS      0x18    /* LED Lighting Status [RO] */
  54 #define CS35L32_FLASH_MODE      0x19    /* LED Flash Mode Current */
  55 #define CS35L32_MOVIE_MODE      0x1A    /* LED Movie Mode Current */
  56 #define CS35L32_FLASH_TIMER     0x1B    /* LED Flash Timer */
  57 #define CS35L32_FLASH_INHIBIT   0x1C    /* LED Flash Inhibit Current */
  58 #define CS35L32_MAX_REGISTER    0x1C
  59 
  60 #define CS35L32_MCLK_DIV2       0x01
  61 #define CS35L32_MCLK_RATIO      0x01
  62 #define CS35L32_MCLKDIS         0x80
  63 #define CS35L32_PDN_ALL         0x01
  64 #define CS35L32_PDN_AMP         0x80
  65 #define CS35L32_PDN_BOOST       0x04
  66 #define CS35L32_PDN_IMON        0x40
  67 #define CS35L32_PDN_VMON        0x80
  68 #define CS35L32_PDN_VPMON       0x20
  69 #define CS35L32_PDN_ADSP        0x08
  70 
  71 #define CS35L32_MCLK_DIV2_MASK          0x40
  72 #define CS35L32_MCLK_RATIO_MASK         0x01
  73 #define CS35L32_MCLK_MASK               0x41
  74 #define CS35L32_ADSP_MASTER_MASK        0x40
  75 #define CS35L32_BOOST_MASK              0x03
  76 #define CS35L32_GAIN_MGR_MASK           0x08
  77 #define CS35L32_ADSP_SHARE_MASK         0x08
  78 #define CS35L32_ADSP_DATACFG_MASK       0x30
  79 #define CS35L32_SDOUT_3ST               0x08
  80 #define CS35L32_BATT_REC_MASK           0x0E
  81 #define CS35L32_BATT_THRESH_MASK        0x30
  82 
  83 #define CS35L32_RATES (SNDRV_PCM_RATE_48000)
  84 #define CS35L32_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  85                         SNDRV_PCM_FMTBIT_S24_LE | \
  86                         SNDRV_PCM_FMTBIT_S32_LE)
  87 
  88 
  89 #endif