sound/soc/codecs/rt5677-spi.c

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This source file includes following definitions.
rt5677_spi_select_cmd
rt5677_spi_reverse
rt5677_spi_read
rt5677_spi_write
rt5677_spi_write_firmware
rt5677_spi_probe
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * rt5677-spi.c  --  RT5677 ALSA SoC audio codec driver
   4  *
   5  * Copyright 2013 Realtek Semiconductor Corp.
   6  * Author: Oder Chiou <oder_chiou@realtek.com>
   7  */
   8 
   9 #include <linux/module.h>
  10 #include <linux/input.h>
  11 #include <linux/spi/spi.h>
  12 #include <linux/device.h>
  13 #include <linux/init.h>
  14 #include <linux/delay.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/slab.h>
  18 #include <linux/sched.h>
  19 #include <linux/uaccess.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/pm_qos.h>
  22 #include <linux/sysfs.h>
  23 #include <linux/clk.h>
  24 #include <linux/firmware.h>
  25 #include <linux/acpi.h>
  26 
  27 #include "rt5677-spi.h"
  28 
  29 #define DRV_NAME "rt5677spi"
  30 
  31 #define RT5677_SPI_BURST_LEN    240
  32 #define RT5677_SPI_HEADER       5
  33 #define RT5677_SPI_FREQ         6000000
  34 
  35 /* The AddressPhase and DataPhase of SPI commands are MSB first on the wire.
  36  * DataPhase word size of 16-bit commands is 2 bytes.
  37  * DataPhase word size of 32-bit commands is 4 bytes.
  38  * DataPhase word size of burst commands is 8 bytes.
  39  * The DSP CPU is little-endian.
  40  */
  41 #define RT5677_SPI_WRITE_BURST  0x5
  42 #define RT5677_SPI_READ_BURST   0x4
  43 #define RT5677_SPI_WRITE_32     0x3
  44 #define RT5677_SPI_READ_32      0x2
  45 #define RT5677_SPI_WRITE_16     0x1
  46 #define RT5677_SPI_READ_16      0x0
  47 
  48 static struct spi_device *g_spi;
  49 static DEFINE_MUTEX(spi_mutex);
  50 
  51 /* Select a suitable transfer command for the next transfer to ensure
  52  * the transfer address is always naturally aligned while minimizing
  53  * the total number of transfers required.
  54  *
  55  * 3 transfer commands are available:
  56  * RT5677_SPI_READ/WRITE_16:    Transfer 2 bytes
  57  * RT5677_SPI_READ/WRITE_32:    Transfer 4 bytes
  58  * RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes
  59  *
  60  * Note:
  61  * 16 Bit writes and reads are restricted to the address range
  62  * 0x18020000 ~ 0x18021000
  63  *
  64  * For example, reading 256 bytes at 0x60030004 uses the following commands:
  65  * 0x60030004 RT5677_SPI_READ_32        4 bytes
  66  * 0x60030008 RT5677_SPI_READ_BURST     240 bytes
  67  * 0x600300F8 RT5677_SPI_READ_BURST     8 bytes
  68  * 0x60030100 RT5677_SPI_READ_32        4 bytes
  69  *
  70  * Input:
  71  * @read: true for read commands; false for write commands
  72  * @align: alignment of the next transfer address
  73  * @remain: number of bytes remaining to transfer
  74  *
  75  * Output:
  76  * @len: number of bytes to transfer with the selected command
  77  * Returns the selected command
  78  */
  79 static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len)
  80 {
  81         u8 cmd;
  82 
  83         if (align == 4 || remain <= 4) {
  84                 cmd = RT5677_SPI_READ_32;
  85                 *len = 4;
  86         } else {
  87                 cmd = RT5677_SPI_READ_BURST;
  88                 *len = (((remain - 1) >> 3) + 1) << 3;
  89                 *len = min_t(u32, *len, RT5677_SPI_BURST_LEN);
  90         }
  91         return read ? cmd : cmd + 1;
  92 }
  93 
  94 /* Copy dstlen bytes from src to dst, while reversing byte order for each word.
  95  * If srclen < dstlen, zeros are padded.
  96  */
  97 static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen)
  98 {
  99         u32 w, i, si;
 100         u32 word_size = min_t(u32, dstlen, 8);
 101 
 102         for (w = 0; w < dstlen; w += word_size) {
 103                 for (i = 0; i < word_size && i + w < dstlen; i++) {
 104                         si = w + word_size - i - 1;
 105                         dst[w + i] = si < srclen ? src[si] : 0;
 106                 }
 107         }
 108 }
 109 
 110 /* Read DSP address space using SPI. addr and len have to be 4-byte aligned. */
 111 int rt5677_spi_read(u32 addr, void *rxbuf, size_t len)
 112 {
 113         u32 offset;
 114         int status = 0;
 115         struct spi_transfer t[2];
 116         struct spi_message m;
 117         /* +4 bytes is for the DummyPhase following the AddressPhase */
 118         u8 header[RT5677_SPI_HEADER + 4];
 119         u8 body[RT5677_SPI_BURST_LEN];
 120         u8 spi_cmd;
 121         u8 *cb = rxbuf;
 122 
 123         if (!g_spi)
 124                 return -ENODEV;
 125 
 126         if ((addr & 3) || (len & 3)) {
 127                 dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len);
 128                 return -EACCES;
 129         }
 130 
 131         memset(t, 0, sizeof(t));
 132         t[0].tx_buf = header;
 133         t[0].len = sizeof(header);
 134         t[0].speed_hz = RT5677_SPI_FREQ;
 135         t[1].rx_buf = body;
 136         t[1].speed_hz = RT5677_SPI_FREQ;
 137         spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
 138 
 139         for (offset = 0; offset < len; offset += t[1].len) {
 140                 spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7,
 141                                 len - offset, &t[1].len);
 142 
 143                 /* Construct SPI message header */
 144                 header[0] = spi_cmd;
 145                 header[1] = ((addr + offset) & 0xff000000) >> 24;
 146                 header[2] = ((addr + offset) & 0x00ff0000) >> 16;
 147                 header[3] = ((addr + offset) & 0x0000ff00) >> 8;
 148                 header[4] = ((addr + offset) & 0x000000ff) >> 0;
 149 
 150                 mutex_lock(&spi_mutex);
 151                 status |= spi_sync(g_spi, &m);
 152                 mutex_unlock(&spi_mutex);
 153 
 154 
 155                 /* Copy data back to caller buffer */
 156                 rt5677_spi_reverse(cb + offset, len - offset, body, t[1].len);
 157         }
 158         return status;
 159 }
 160 EXPORT_SYMBOL_GPL(rt5677_spi_read);
 161 
 162 /* Write DSP address space using SPI. addr has to be 4-byte aligned.
 163  * If len is not 4-byte aligned, then extra zeros are written at the end
 164  * as padding.
 165  */
 166 int rt5677_spi_write(u32 addr, const void *txbuf, size_t len)
 167 {
 168         u32 offset;
 169         int status = 0;
 170         struct spi_transfer t;
 171         struct spi_message m;
 172         /* +1 byte is for the DummyPhase following the DataPhase */
 173         u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1];
 174         u8 *body = buf + RT5677_SPI_HEADER;
 175         u8 spi_cmd;
 176         const u8 *cb = txbuf;
 177 
 178         if (!g_spi)
 179                 return -ENODEV;
 180 
 181         if (addr & 3) {
 182                 dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len);
 183                 return -EACCES;
 184         }
 185 
 186         memset(&t, 0, sizeof(t));
 187         t.tx_buf = buf;
 188         t.speed_hz = RT5677_SPI_FREQ;
 189         spi_message_init_with_transfers(&m, &t, 1);
 190 
 191         for (offset = 0; offset < len;) {
 192                 spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7,
 193                                 len - offset, &t.len);
 194 
 195                 /* Construct SPI message header */
 196                 buf[0] = spi_cmd;
 197                 buf[1] = ((addr + offset) & 0xff000000) >> 24;
 198                 buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
 199                 buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
 200                 buf[4] = ((addr + offset) & 0x000000ff) >> 0;
 201 
 202                 /* Fetch data from caller buffer */
 203                 rt5677_spi_reverse(body, t.len, cb + offset, len - offset);
 204                 offset += t.len;
 205                 t.len += RT5677_SPI_HEADER + 1;
 206 
 207                 mutex_lock(&spi_mutex);
 208                 status |= spi_sync(g_spi, &m);
 209                 mutex_unlock(&spi_mutex);
 210         }
 211         return status;
 212 }
 213 EXPORT_SYMBOL_GPL(rt5677_spi_write);
 214 
 215 int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw)
 216 {
 217         return rt5677_spi_write(addr, fw->data, fw->size);
 218 }
 219 EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware);
 220 
 221 static int rt5677_spi_probe(struct spi_device *spi)
 222 {
 223         g_spi = spi;
 224         return 0;
 225 }
 226 
 227 static const struct acpi_device_id rt5677_spi_acpi_id[] = {
 228         { "RT5677AA", 0 },
 229         { }
 230 };
 231 MODULE_DEVICE_TABLE(acpi, rt5677_spi_acpi_id);
 232 
 233 static struct spi_driver rt5677_spi_driver = {
 234         .driver = {
 235                 .name = DRV_NAME,
 236                 .acpi_match_table = ACPI_PTR(rt5677_spi_acpi_id),
 237         },
 238         .probe = rt5677_spi_probe,
 239 };
 240 module_spi_driver(rt5677_spi_driver);
 241 
 242 MODULE_DESCRIPTION("ASoC RT5677 SPI driver");
 243 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
 244 MODULE_LICENSE("GPL v2");
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root/sound/soc/codecs/rt5677-spi.c

DEFINITIONS
