This source file includes following definitions.
- rt286_volatile_register
- rt286_readable_register
- rt286_index_sync
- rt286_jack_detect
- rt286_jack_detect_work
- rt286_mic_detect
- is_mclk_mode
- rt286_spk_event
- rt286_set_dmic1_event
- rt286_ldo2_event
- rt286_mic1_event
- rt286_hw_params
- rt286_set_dai_fmt
- rt286_set_dai_sysclk
- rt286_set_bclk_ratio
- rt286_set_bias_level
- rt286_irq
- rt286_probe
- rt286_remove
- rt286_suspend
- rt286_resume
- rt286_i2c_probe
- rt286_i2c_remove
1
2
3
4
5
6
7
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/dmi.h>
18 #include <linux/acpi.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/soc-dapm.h>
24 #include <sound/initval.h>
25 #include <sound/tlv.h>
26 #include <sound/jack.h>
27 #include <linux/workqueue.h>
28 #include <sound/rt286.h>
29
30 #include "rl6347a.h"
31 #include "rt286.h"
32
33 #define RT286_VENDOR_ID 0x10ec0286
34 #define RT288_VENDOR_ID 0x10ec0288
35
36 struct rt286_priv {
37 struct reg_default *index_cache;
38 int index_cache_size;
39 struct regmap *regmap;
40 struct snd_soc_component *component;
41 struct rt286_platform_data pdata;
42 struct i2c_client *i2c;
43 struct snd_soc_jack *jack;
44 struct delayed_work jack_detect_work;
45 int sys_clk;
46 int clk_id;
47 };
48
49 static const struct reg_default rt286_index_def[] = {
50 { 0x01, 0xaaaa },
51 { 0x02, 0x8aaa },
52 { 0x03, 0x0002 },
53 { 0x04, 0xaf01 },
54 { 0x08, 0x000d },
55 { 0x09, 0xd810 },
56 { 0x0a, 0x0120 },
57 { 0x0b, 0x0000 },
58 { 0x0d, 0x2800 },
59 { 0x0f, 0x0000 },
60 { 0x19, 0x0a17 },
61 { 0x20, 0x0020 },
62 { 0x33, 0x0208 },
63 { 0x49, 0x0004 },
64 { 0x4f, 0x50e9 },
65 { 0x50, 0x2000 },
66 { 0x63, 0x2902 },
67 { 0x67, 0x1111 },
68 { 0x68, 0x1016 },
69 { 0x69, 0x273f },
70 };
71 #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
72
73 static const struct reg_default rt286_reg[] = {
74 { 0x00170500, 0x00000400 },
75 { 0x00220000, 0x00000031 },
76 { 0x00239000, 0x0000007f },
77 { 0x0023a000, 0x0000007f },
78 { 0x00270500, 0x00000400 },
79 { 0x00370500, 0x00000400 },
80 { 0x00870500, 0x00000400 },
81 { 0x00920000, 0x00000031 },
82 { 0x00935000, 0x000000c3 },
83 { 0x00936000, 0x000000c3 },
84 { 0x00970500, 0x00000400 },
85 { 0x00b37000, 0x00000097 },
86 { 0x00b37200, 0x00000097 },
87 { 0x00b37300, 0x00000097 },
88 { 0x00c37000, 0x00000000 },
89 { 0x00c37100, 0x00000080 },
90 { 0x01270500, 0x00000400 },
91 { 0x01370500, 0x00000400 },
92 { 0x01371f00, 0x411111f0 },
93 { 0x01439000, 0x00000080 },
94 { 0x0143a000, 0x00000080 },
95 { 0x01470700, 0x00000000 },
96 { 0x01470500, 0x00000400 },
97 { 0x01470c00, 0x00000000 },
98 { 0x01470100, 0x00000000 },
99 { 0x01837000, 0x00000000 },
100 { 0x01870500, 0x00000400 },
101 { 0x02050000, 0x00000000 },
102 { 0x02139000, 0x00000080 },
103 { 0x0213a000, 0x00000080 },
104 { 0x02170100, 0x00000000 },
105 { 0x02170500, 0x00000400 },
106 { 0x02170700, 0x00000000 },
107 { 0x02270100, 0x00000000 },
108 { 0x02370100, 0x00000000 },
109 { 0x01870700, 0x00000020 },
110 { 0x00830000, 0x000000c3 },
111 { 0x00930000, 0x000000c3 },
112 { 0x01270700, 0x00000000 },
113 };
114
115 static bool rt286_volatile_register(struct device *dev, unsigned int reg)
116 {
117 switch (reg) {
118 case 0 ... 0xff:
119 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
120 case RT286_GET_HP_SENSE:
121 case RT286_GET_MIC1_SENSE:
122 case RT286_PROC_COEF:
123 return true;
124 default:
125 return false;
126 }
127
128
129 }
130
131 static bool rt286_readable_register(struct device *dev, unsigned int reg)
132 {
133 switch (reg) {
134 case 0 ... 0xff:
135 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
136 case RT286_GET_HP_SENSE:
137 case RT286_GET_MIC1_SENSE:
138 case RT286_SET_AUDIO_POWER:
139 case RT286_SET_HPO_POWER:
140 case RT286_SET_SPK_POWER:
141 case RT286_SET_DMIC1_POWER:
142 case RT286_SPK_MUX:
143 case RT286_HPO_MUX:
144 case RT286_ADC0_MUX:
145 case RT286_ADC1_MUX:
146 case RT286_SET_MIC1:
147 case RT286_SET_PIN_HPO:
148 case RT286_SET_PIN_SPK:
149 case RT286_SET_PIN_DMIC1:
150 case RT286_SPK_EAPD:
151 case RT286_SET_AMP_GAIN_HPO:
152 case RT286_SET_DMIC2_DEFAULT:
153 case RT286_DACL_GAIN:
154 case RT286_DACR_GAIN:
155 case RT286_ADCL_GAIN:
156 case RT286_ADCR_GAIN:
157 case RT286_MIC_GAIN:
158 case RT286_SPOL_GAIN:
159 case RT286_SPOR_GAIN:
160 case RT286_HPOL_GAIN:
161 case RT286_HPOR_GAIN:
162 case RT286_F_DAC_SWITCH:
163 case RT286_F_RECMIX_SWITCH:
164 case RT286_REC_MIC_SWITCH:
165 case RT286_REC_I2S_SWITCH:
166 case RT286_REC_LINE_SWITCH:
167 case RT286_REC_BEEP_SWITCH:
168 case RT286_DAC_FORMAT:
169 case RT286_ADC_FORMAT:
170 case RT286_COEF_INDEX:
171 case RT286_PROC_COEF:
172 case RT286_SET_AMP_GAIN_ADC_IN1:
173 case RT286_SET_AMP_GAIN_ADC_IN2:
174 case RT286_SET_POWER(RT286_DAC_OUT1):
175 case RT286_SET_POWER(RT286_DAC_OUT2):
176 case RT286_SET_POWER(RT286_ADC_IN1):
177 case RT286_SET_POWER(RT286_ADC_IN2):
178 case RT286_SET_POWER(RT286_DMIC2):
179 case RT286_SET_POWER(RT286_MIC1):
180 return true;
181 default:
182 return false;
183 }
184 }
185
186 #ifdef CONFIG_PM
187 static void rt286_index_sync(struct snd_soc_component *component)
188 {
189 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
190 int i;
191
192 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
193 snd_soc_component_write(component, rt286->index_cache[i].reg,
194 rt286->index_cache[i].def);
195 }
196 }
197 #endif
198
199 static int rt286_support_power_controls[] = {
200 RT286_DAC_OUT1,
201 RT286_DAC_OUT2,
202 RT286_ADC_IN1,
203 RT286_ADC_IN2,
204 RT286_MIC1,
205 RT286_DMIC1,
206 RT286_DMIC2,
207 RT286_SPK_OUT,
208 RT286_HP_OUT,
209 };
210 #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
211
212 static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
213 {
214 struct snd_soc_dapm_context *dapm;
215 unsigned int val, buf;
216
217 *hp = false;
218 *mic = false;
219
220 if (!rt286->component)
221 return -EINVAL;
222
223 dapm = snd_soc_component_get_dapm(rt286->component);
224
225 if (rt286->pdata.cbj_en) {
226 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
227 *hp = buf & 0x80000000;
228 if (*hp) {
229
230 regmap_update_bits(rt286->regmap,
231 RT286_DC_GAIN, 0x200, 0x200);
232
233 snd_soc_dapm_force_enable_pin(dapm, "HV");
234 snd_soc_dapm_force_enable_pin(dapm, "VREF");
235
236 snd_soc_dapm_force_enable_pin(dapm, "LDO1");
237 snd_soc_dapm_sync(dapm);
238
239 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
240 msleep(50);
241
242 regmap_update_bits(rt286->regmap,
243 RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
244 msleep(300);
245 regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
246
247 if (0x0070 == (val & 0x0070)) {
248 *mic = true;
249 } else {
250 regmap_update_bits(rt286->regmap,
251 RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
252 msleep(300);
253 regmap_read(rt286->regmap,
254 RT286_CBJ_CTRL2, &val);
255 if (0x0070 == (val & 0x0070))
256 *mic = true;
257 else
258 *mic = false;
259 }
260 regmap_update_bits(rt286->regmap,
261 RT286_DC_GAIN, 0x200, 0x0);
262
263 } else {
264 *mic = false;
265 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
266 regmap_update_bits(rt286->regmap,
267 RT286_CBJ_CTRL1, 0x0400, 0x0000);
268 }
269 } else {
270 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
271 *hp = buf & 0x80000000;
272 regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
273 *mic = buf & 0x80000000;
274 }
275 if (!*mic) {
276 snd_soc_dapm_disable_pin(dapm, "HV");
277 snd_soc_dapm_disable_pin(dapm, "VREF");
278 }
279 if (!*hp)
280 snd_soc_dapm_disable_pin(dapm, "LDO1");
281 snd_soc_dapm_sync(dapm);
282
283 return 0;
284 }
285
286 static void rt286_jack_detect_work(struct work_struct *work)
287 {
288 struct rt286_priv *rt286 =
289 container_of(work, struct rt286_priv, jack_detect_work.work);
290 int status = 0;
291 bool hp = false;
292 bool mic = false;
293
294 rt286_jack_detect(rt286, &hp, &mic);
295
296 if (hp)
297 status |= SND_JACK_HEADPHONE;
298
299 if (mic)
300 status |= SND_JACK_MICROPHONE;
301
302 snd_soc_jack_report(rt286->jack, status,
303 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
304 }
305
306 int rt286_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack)
307 {
308 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
309 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
310
311 rt286->jack = jack;
312
313 if (jack) {
314
315 if (rt286->jack->status & SND_JACK_HEADPHONE)
316 snd_soc_dapm_force_enable_pin(dapm, "LDO1");
317 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2);
318
319 snd_soc_jack_report(rt286->jack, rt286->jack->status,
320 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
321 } else {
322
323 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0);
324 snd_soc_dapm_disable_pin(dapm, "LDO1");
325 }
326 snd_soc_dapm_sync(dapm);
327
328 return 0;
329 }
330 EXPORT_SYMBOL_GPL(rt286_mic_detect);
331
332 static int is_mclk_mode(struct snd_soc_dapm_widget *source,
333 struct snd_soc_dapm_widget *sink)
334 {
335 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
336 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
337
338 if (rt286->clk_id == RT286_SCLK_S_MCLK)
339 return 1;
340 else
341 return 0;
342 }
343
344 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
345 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
346
347 static const struct snd_kcontrol_new rt286_snd_controls[] = {
348 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
349 RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
350 SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
351 RT286_ADCR_GAIN, 7, 1, 1),
352 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
353 RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
354 SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
355 0, 0x3, 0, mic_vol_tlv),
356 SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
357 RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
358 };
359
360
361 static const struct snd_kcontrol_new rt286_front_mix[] = {
362 SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
363 RT286_MUTE_SFT, 1, 1),
364 SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
365 RT286_MUTE_SFT, 1, 1),
366 };
367
368
369 static const struct snd_kcontrol_new rt286_rec_mix[] = {
370 SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
371 RT286_MUTE_SFT, 1, 1),
372 SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
373 RT286_MUTE_SFT, 1, 1),
374 SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
375 RT286_MUTE_SFT, 1, 1),
376 SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
377 RT286_MUTE_SFT, 1, 1),
378 };
379
380 static const struct snd_kcontrol_new spo_enable_control =
381 SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
382 RT286_SET_PIN_SFT, 1, 0);
383
384 static const struct snd_kcontrol_new hpol_enable_control =
385 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
386 RT286_MUTE_SFT, 1, 1);
387
388 static const struct snd_kcontrol_new hpor_enable_control =
389 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
390 RT286_MUTE_SFT, 1, 1);
391
392
393 static const char * const rt286_adc_src[] = {
394 "Mic", "RECMIX", "Dmic"
395 };
396
397 static const int rt286_adc_values[] = {
398 0, 4, 5,
399 };
400
401 static SOC_VALUE_ENUM_SINGLE_DECL(
402 rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
403 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
404
405 static const struct snd_kcontrol_new rt286_adc0_mux =
406 SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
407
408 static SOC_VALUE_ENUM_SINGLE_DECL(
409 rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
410 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
411
412 static const struct snd_kcontrol_new rt286_adc1_mux =
413 SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
414
415 static const char * const rt286_dac_src[] = {
416 "Front", "Surround"
417 };
418
419 static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
420 0, rt286_dac_src);
421
422 static const struct snd_kcontrol_new rt286_hpo_mux =
423 SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
424
425
426 static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
427 0, rt286_dac_src);
428
429 static const struct snd_kcontrol_new rt286_spo_mux =
430 SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
431
432 static int rt286_spk_event(struct snd_soc_dapm_widget *w,
433 struct snd_kcontrol *kcontrol, int event)
434 {
435 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
436
437 switch (event) {
438 case SND_SOC_DAPM_POST_PMU:
439 snd_soc_component_write(component,
440 RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
441 break;
442 case SND_SOC_DAPM_PRE_PMD:
443 snd_soc_component_write(component,
444 RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
445 break;
446
447 default:
448 return 0;
449 }
450
451 return 0;
452 }
453
454 static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
455 struct snd_kcontrol *kcontrol, int event)
456 {
457 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
458
459 switch (event) {
460 case SND_SOC_DAPM_POST_PMU:
461 snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0x20);
462 break;
463 case SND_SOC_DAPM_PRE_PMD:
464 snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0);
465 break;
466 default:
467 return 0;
468 }
469
470 return 0;
471 }
472
473 static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
474 struct snd_kcontrol *kcontrol, int event)
475 {
476 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
477
478 switch (event) {
479 case SND_SOC_DAPM_POST_PMU:
480 snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x08);
481 break;
482 case SND_SOC_DAPM_PRE_PMD:
483 snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x30);
484 break;
485 default:
486 return 0;
487 }
488
489 return 0;
490 }
491
492 static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
493 struct snd_kcontrol *kcontrol, int event)
494 {
495 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
496
497 switch (event) {
498 case SND_SOC_DAPM_PRE_PMU:
499 snd_soc_component_update_bits(component,
500 RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
501 snd_soc_component_update_bits(component,
502 RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
503 break;
504 case SND_SOC_DAPM_POST_PMD:
505 snd_soc_component_update_bits(component,
506 RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
507 snd_soc_component_update_bits(component,
508 RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
509 break;
510 default:
511 return 0;
512 }
513
514 return 0;
515 }
516
517 static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
518 SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
519 12, 1, NULL, 0),
520 SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
521 0, 1, NULL, 0),
522 SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
523 2, 0, NULL, 0),
524 SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
525 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
526 SND_SOC_DAPM_POST_PMU),
527 SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
528 5, 0, NULL, 0),
529 SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
530 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
531 SND_SOC_DAPM_POST_PMD),
532
533
534 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
535 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
536 SND_SOC_DAPM_INPUT("MIC1"),
537 SND_SOC_DAPM_INPUT("LINE1"),
538 SND_SOC_DAPM_INPUT("Beep"),
539
540
541 SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
542 NULL, 0, rt286_set_dmic1_event,
543 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
544 SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
545 NULL, 0),
546 SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
547 0, 0, NULL, 0),
548
549
550 SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
551 rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
552
553
554 SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
555 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
556
557
558 SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
559 &rt286_adc0_mux),
560 SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
561 &rt286_adc1_mux),
562
563
564 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
565 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
566 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
567 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
568
569
570
571 SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
572 SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
573
574
575 SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
576 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
577
578 SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
579 RT286_SET_PIN_SFT, 0, NULL, 0),
580
581
582 SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
583 rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
584 SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
585 NULL, 0),
586
587
588 SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
589 &spo_enable_control, rt286_spk_event,
590 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
591 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
592 &hpol_enable_control),
593 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
594 &hpor_enable_control),
595
596
597 SND_SOC_DAPM_OUTPUT("SPOL"),
598 SND_SOC_DAPM_OUTPUT("SPOR"),
599 SND_SOC_DAPM_OUTPUT("HPO Pin"),
600 SND_SOC_DAPM_OUTPUT("SPDIF"),
601 };
602
603 static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
604 {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
605 {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
606 {"Front", NULL, "MCLK MODE", is_mclk_mode},
607 {"Surround", NULL, "MCLK MODE", is_mclk_mode},
608
609 {"HP Power", NULL, "LDO1"},
610 {"HP Power", NULL, "LDO2"},
611
612 {"MIC1", NULL, "LDO1"},
613 {"MIC1", NULL, "LDO2"},
614 {"MIC1", NULL, "HV"},
615 {"MIC1", NULL, "VREF"},
616 {"MIC1", NULL, "MIC1 Input Buffer"},
617
618 {"SPO", NULL, "LDO1"},
619 {"SPO", NULL, "LDO2"},
620 {"SPO", NULL, "HV"},
621 {"SPO", NULL, "VREF"},
622
623 {"DMIC1", NULL, "DMIC1 Pin"},
624 {"DMIC2", NULL, "DMIC2 Pin"},
625 {"DMIC1", NULL, "DMIC Receiver"},
626 {"DMIC2", NULL, "DMIC Receiver"},
627
628 {"RECMIX", "Beep Switch", "Beep"},
629 {"RECMIX", "Line1 Switch", "LINE1"},
630 {"RECMIX", "Mic1 Switch", "MIC1"},
631
632 {"ADC 0 Mux", "Dmic", "DMIC1"},
633 {"ADC 0 Mux", "RECMIX", "RECMIX"},
634 {"ADC 0 Mux", "Mic", "MIC1"},
635 {"ADC 1 Mux", "Dmic", "DMIC2"},
636 {"ADC 1 Mux", "RECMIX", "RECMIX"},
637 {"ADC 1 Mux", "Mic", "MIC1"},
638
639 {"ADC 0", NULL, "ADC 0 Mux"},
640 {"ADC 1", NULL, "ADC 1 Mux"},
641
642 {"AIF1TX", NULL, "ADC 0"},
643 {"AIF2TX", NULL, "ADC 1"},
644
645 {"DAC 0", NULL, "AIF1RX"},
646 {"DAC 1", NULL, "AIF2RX"},
647
648 {"Front", "DAC Switch", "DAC 0"},
649 {"Front", "RECMIX Switch", "RECMIX"},
650
651 {"Surround", NULL, "DAC 1"},
652
653 {"SPK Mux", "Front", "Front"},
654 {"SPK Mux", "Surround", "Surround"},
655
656 {"HPO Mux", "Front", "Front"},
657 {"HPO Mux", "Surround", "Surround"},
658
659 {"SPO", "Switch", "SPK Mux"},
660 {"HPO L", "Switch", "HPO Mux"},
661 {"HPO R", "Switch", "HPO Mux"},
662 {"HPO L", NULL, "HP Power"},
663 {"HPO R", NULL, "HP Power"},
664
665 {"SPOL", NULL, "SPO"},
666 {"SPOR", NULL, "SPO"},
667 {"HPO Pin", NULL, "HPO L"},
668 {"HPO Pin", NULL, "HPO R"},
669 };
670
671 static int rt286_hw_params(struct snd_pcm_substream *substream,
672 struct snd_pcm_hw_params *params,
673 struct snd_soc_dai *dai)
674 {
675 struct snd_soc_component *component = dai->component;
676 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
677 unsigned int val = 0;
678 int d_len_code;
679
680 switch (params_rate(params)) {
681
682 case 44100:
683 val |= 0x4000;
684 break;
685 case 48000:
686 break;
687 default:
688 dev_err(component->dev, "Unsupported sample rate %d\n",
689 params_rate(params));
690 return -EINVAL;
691 }
692 switch (rt286->sys_clk) {
693 case 12288000:
694 case 24576000:
695 if (params_rate(params) != 48000) {
696 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
697 params_rate(params), rt286->sys_clk);
698 return -EINVAL;
699 }
700 break;
701 case 11289600:
702 case 22579200:
703 if (params_rate(params) != 44100) {
704 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
705 params_rate(params), rt286->sys_clk);
706 return -EINVAL;
707 }
708 break;
709 }
710
711 if (params_channels(params) <= 16) {
712
713 val |= (params_channels(params) - 1);
714 } else {
715 dev_err(component->dev, "Unsupported channels %d\n",
716 params_channels(params));
717 return -EINVAL;
718 }
719
720 d_len_code = 0;
721 switch (params_width(params)) {
722
723 case 16:
724 d_len_code = 0;
725 val |= (0x1 << 4);
726 break;
727 case 32:
728 d_len_code = 2;
729 val |= (0x4 << 4);
730 break;
731 case 20:
732 d_len_code = 1;
733 val |= (0x2 << 4);
734 break;
735 case 24:
736 d_len_code = 2;
737 val |= (0x3 << 4);
738 break;
739 case 8:
740 d_len_code = 3;
741 break;
742 default:
743 return -EINVAL;
744 }
745
746 snd_soc_component_update_bits(component,
747 RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
748 dev_dbg(component->dev, "format val = 0x%x\n", val);
749
750 snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x407f, val);
751 snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x407f, val);
752
753 return 0;
754 }
755
756 static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
757 {
758 struct snd_soc_component *component = dai->component;
759
760 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
761 case SND_SOC_DAIFMT_CBM_CFM:
762 snd_soc_component_update_bits(component,
763 RT286_I2S_CTRL1, 0x800, 0x800);
764 break;
765 case SND_SOC_DAIFMT_CBS_CFS:
766 snd_soc_component_update_bits(component,
767 RT286_I2S_CTRL1, 0x800, 0x0);
768 break;
769 default:
770 return -EINVAL;
771 }
772
773 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
774 case SND_SOC_DAIFMT_I2S:
775 snd_soc_component_update_bits(component,
776 RT286_I2S_CTRL1, 0x300, 0x0);
777 break;
778 case SND_SOC_DAIFMT_LEFT_J:
779 snd_soc_component_update_bits(component,
780 RT286_I2S_CTRL1, 0x300, 0x1 << 8);
781 break;
782 case SND_SOC_DAIFMT_DSP_A:
783 snd_soc_component_update_bits(component,
784 RT286_I2S_CTRL1, 0x300, 0x2 << 8);
785 break;
786 case SND_SOC_DAIFMT_DSP_B:
787 snd_soc_component_update_bits(component,
788 RT286_I2S_CTRL1, 0x300, 0x3 << 8);
789 break;
790 default:
791 return -EINVAL;
792 }
793
794 snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x8000, 0);
795 snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x8000, 0);
796
797 return 0;
798 }
799
800 static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
801 int clk_id, unsigned int freq, int dir)
802 {
803 struct snd_soc_component *component = dai->component;
804 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
805
806 dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);
807
808 if (RT286_SCLK_S_MCLK == clk_id) {
809 snd_soc_component_update_bits(component,
810 RT286_I2S_CTRL2, 0x0100, 0x0);
811 snd_soc_component_update_bits(component,
812 RT286_PLL_CTRL1, 0x20, 0x20);
813 } else {
814 snd_soc_component_update_bits(component,
815 RT286_I2S_CTRL2, 0x0100, 0x0100);
816 snd_soc_component_update_bits(component,
817 RT286_PLL_CTRL, 0x4, 0x4);
818 snd_soc_component_update_bits(component,
819 RT286_PLL_CTRL1, 0x20, 0x0);
820 }
821
822 switch (freq) {
823 case 19200000:
824 if (RT286_SCLK_S_MCLK == clk_id) {
825 dev_err(component->dev, "Should not use MCLK\n");
826 return -EINVAL;
827 }
828 snd_soc_component_update_bits(component,
829 RT286_I2S_CTRL2, 0x40, 0x40);
830 break;
831 case 24000000:
832 if (RT286_SCLK_S_MCLK == clk_id) {
833 dev_err(component->dev, "Should not use MCLK\n");
834 return -EINVAL;
835 }
836 snd_soc_component_update_bits(component,
837 RT286_I2S_CTRL2, 0x40, 0x0);
838 break;
839 case 12288000:
840 case 11289600:
841 snd_soc_component_update_bits(component,
842 RT286_I2S_CTRL2, 0x8, 0x0);
843 snd_soc_component_update_bits(component,
844 RT286_CLK_DIV, 0xfc1e, 0x0004);
845 break;
846 case 24576000:
847 case 22579200:
848 snd_soc_component_update_bits(component,
849 RT286_I2S_CTRL2, 0x8, 0x8);
850 snd_soc_component_update_bits(component,
851 RT286_CLK_DIV, 0xfc1e, 0x5406);
852 break;
853 default:
854 dev_err(component->dev, "Unsupported system clock\n");
855 return -EINVAL;
856 }
857
858 rt286->sys_clk = freq;
859 rt286->clk_id = clk_id;
860
861 return 0;
862 }
863
864 static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
865 {
866 struct snd_soc_component *component = dai->component;
867
868 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
869 if (50 == ratio)
870 snd_soc_component_update_bits(component,
871 RT286_I2S_CTRL1, 0x1000, 0x1000);
872 else
873 snd_soc_component_update_bits(component,
874 RT286_I2S_CTRL1, 0x1000, 0x0);
875
876
877 return 0;
878 }
879
880 static int rt286_set_bias_level(struct snd_soc_component *component,
881 enum snd_soc_bias_level level)
882 {
883 switch (level) {
884 case SND_SOC_BIAS_PREPARE:
885 if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
886 snd_soc_component_write(component,
887 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
888 snd_soc_component_update_bits(component,
889 RT286_DC_GAIN, 0x200, 0x200);
890 }
891 break;
892
893 case SND_SOC_BIAS_ON:
894 mdelay(10);
895 snd_soc_component_update_bits(component,
896 RT286_DC_GAIN, 0x200, 0x0);
897
898 break;
899
900 case SND_SOC_BIAS_STANDBY:
901 snd_soc_component_write(component,
902 RT286_SET_AUDIO_POWER, AC_PWRST_D3);
903 break;
904
905 default:
906 break;
907 }
908
909 return 0;
910 }
911
912 static irqreturn_t rt286_irq(int irq, void *data)
913 {
914 struct rt286_priv *rt286 = data;
915 bool hp = false;
916 bool mic = false;
917 int status = 0;
918
919 rt286_jack_detect(rt286, &hp, &mic);
920
921
922 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
923
924 if (hp)
925 status |= SND_JACK_HEADPHONE;
926
927 if (mic)
928 status |= SND_JACK_MICROPHONE;
929
930 snd_soc_jack_report(rt286->jack, status,
931 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
932
933 pm_wakeup_event(&rt286->i2c->dev, 300);
934
935 return IRQ_HANDLED;
936 }
937
938 static int rt286_probe(struct snd_soc_component *component)
939 {
940 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
941
942 rt286->component = component;
943
944 if (rt286->i2c->irq) {
945 regmap_update_bits(rt286->regmap,
946 RT286_IRQ_CTRL, 0x2, 0x2);
947
948 INIT_DELAYED_WORK(&rt286->jack_detect_work,
949 rt286_jack_detect_work);
950 schedule_delayed_work(&rt286->jack_detect_work,
951 msecs_to_jiffies(1250));
952 }
953
954 return 0;
955 }
956
957 static void rt286_remove(struct snd_soc_component *component)
958 {
959 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
960
961 cancel_delayed_work_sync(&rt286->jack_detect_work);
962 }
963
964 #ifdef CONFIG_PM
965 static int rt286_suspend(struct snd_soc_component *component)
966 {
967 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
968
969 regcache_cache_only(rt286->regmap, true);
970 regcache_mark_dirty(rt286->regmap);
971
972 return 0;
973 }
974
975 static int rt286_resume(struct snd_soc_component *component)
976 {
977 struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component);
978
979 regcache_cache_only(rt286->regmap, false);
980 rt286_index_sync(component);
981 regcache_sync(rt286->regmap);
982
983 return 0;
984 }
985 #else
986 #define rt286_suspend NULL
987 #define rt286_resume NULL
988 #endif
989
990 #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
991 #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
992 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
993
994 static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
995 .hw_params = rt286_hw_params,
996 .set_fmt = rt286_set_dai_fmt,
997 .set_sysclk = rt286_set_dai_sysclk,
998 .set_bclk_ratio = rt286_set_bclk_ratio,
999 };
1000
1001 static struct snd_soc_dai_driver rt286_dai[] = {
1002 {
1003 .name = "rt286-aif1",
1004 .id = RT286_AIF1,
1005 .playback = {
1006 .stream_name = "AIF1 Playback",
1007 .channels_min = 1,
1008 .channels_max = 2,
1009 .rates = RT286_STEREO_RATES,
1010 .formats = RT286_FORMATS,
1011 },
1012 .capture = {
1013 .stream_name = "AIF1 Capture",
1014 .channels_min = 1,
1015 .channels_max = 2,
1016 .rates = RT286_STEREO_RATES,
1017 .formats = RT286_FORMATS,
1018 },
1019 .ops = &rt286_aif_dai_ops,
1020 .symmetric_rates = 1,
1021 },
1022 {
1023 .name = "rt286-aif2",
1024 .id = RT286_AIF2,
1025 .playback = {
1026 .stream_name = "AIF2 Playback",
1027 .channels_min = 1,
1028 .channels_max = 2,
1029 .rates = RT286_STEREO_RATES,
1030 .formats = RT286_FORMATS,
1031 },
1032 .capture = {
1033 .stream_name = "AIF2 Capture",
1034 .channels_min = 1,
1035 .channels_max = 2,
1036 .rates = RT286_STEREO_RATES,
1037 .formats = RT286_FORMATS,
1038 },
1039 .ops = &rt286_aif_dai_ops,
1040 .symmetric_rates = 1,
1041 },
1042
1043 };
1044
1045 static const struct snd_soc_component_driver soc_component_dev_rt286 = {
1046 .probe = rt286_probe,
1047 .remove = rt286_remove,
1048 .suspend = rt286_suspend,
1049 .resume = rt286_resume,
1050 .set_bias_level = rt286_set_bias_level,
1051 .controls = rt286_snd_controls,
1052 .num_controls = ARRAY_SIZE(rt286_snd_controls),
1053 .dapm_widgets = rt286_dapm_widgets,
1054 .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1055 .dapm_routes = rt286_dapm_routes,
1056 .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1057 .use_pmdown_time = 1,
1058 .endianness = 1,
1059 .non_legacy_dai_naming = 1,
1060 };
1061
1062 static const struct regmap_config rt286_regmap = {
1063 .reg_bits = 32,
1064 .val_bits = 32,
1065 .max_register = 0x02370100,
1066 .volatile_reg = rt286_volatile_register,
1067 .readable_reg = rt286_readable_register,
1068 .reg_write = rl6347a_hw_write,
1069 .reg_read = rl6347a_hw_read,
1070 .cache_type = REGCACHE_RBTREE,
1071 .reg_defaults = rt286_reg,
1072 .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1073 };
1074
1075 static const struct i2c_device_id rt286_i2c_id[] = {
1076 {"rt286", 0},
1077 {"rt288", 0},
1078 {}
1079 };
1080 MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1081
1082 static const struct acpi_device_id rt286_acpi_match[] = {
1083 { "INT343A", 0 },
1084 {},
1085 };
1086 MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1087
1088 static const struct dmi_system_id force_combo_jack_table[] = {
1089 {
1090 .ident = "Intel Wilson Beach",
1091 .matches = {
1092 DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1093 }
1094 },
1095 {
1096 .ident = "Intel Skylake RVP",
1097 .matches = {
1098 DMI_MATCH(DMI_PRODUCT_NAME, "Skylake Client platform")
1099 }
1100 },
1101 {
1102 .ident = "Intel Kabylake RVP",
1103 .matches = {
1104 DMI_MATCH(DMI_PRODUCT_NAME, "Kabylake Client platform")
1105 }
1106 },
1107 {
1108 .ident = "Thinkpad Helix 2nd",
1109 .matches = {
1110 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1111 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Helix 2nd")
1112 }
1113 },
1114
1115 { }
1116 };
1117
1118 static const struct dmi_system_id dmi_dell_dino[] = {
1119 {
1120 .ident = "Dell Dino",
1121 .matches = {
1122 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1123 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 13 9343")
1124 }
1125 },
1126 { }
1127 };
1128
1129 static int rt286_i2c_probe(struct i2c_client *i2c,
1130 const struct i2c_device_id *id)
1131 {
1132 struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1133 struct rt286_priv *rt286;
1134 int i, ret, val;
1135
1136 rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1137 GFP_KERNEL);
1138 if (NULL == rt286)
1139 return -ENOMEM;
1140
1141 rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1142 if (IS_ERR(rt286->regmap)) {
1143 ret = PTR_ERR(rt286->regmap);
1144 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1145 ret);
1146 return ret;
1147 }
1148
1149 ret = regmap_read(rt286->regmap,
1150 RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val);
1151 if (ret != 0) {
1152 dev_err(&i2c->dev, "I2C error %d\n", ret);
1153 return ret;
1154 }
1155 if (val != RT286_VENDOR_ID && val != RT288_VENDOR_ID) {
1156 dev_err(&i2c->dev,
1157 "Device with ID register %#x is not rt286\n", val);
1158 return -ENODEV;
1159 }
1160
1161 rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def,
1162 sizeof(rt286_index_def), GFP_KERNEL);
1163 if (!rt286->index_cache)
1164 return -ENOMEM;
1165
1166 rt286->index_cache_size = INDEX_CACHE_SIZE;
1167 rt286->i2c = i2c;
1168 i2c_set_clientdata(i2c, rt286);
1169
1170
1171 for (i = 0; i < INDEX_CACHE_SIZE; i++)
1172 regmap_write(rt286->regmap, rt286->index_cache[i].reg,
1173 rt286->index_cache[i].def);
1174 for (i = 0; i < ARRAY_SIZE(rt286_reg); i++)
1175 regmap_write(rt286->regmap, rt286_reg[i].reg,
1176 rt286_reg[i].def);
1177
1178 if (pdata)
1179 rt286->pdata = *pdata;
1180
1181 if (dmi_check_system(force_combo_jack_table) ||
1182 dmi_check_system(dmi_dell_dino))
1183 rt286->pdata.cbj_en = true;
1184
1185 regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1186
1187 for (i = 0; i < RT286_POWER_REG_LEN; i++)
1188 regmap_write(rt286->regmap,
1189 RT286_SET_POWER(rt286_support_power_controls[i]),
1190 AC_PWRST_D1);
1191
1192 if (!rt286->pdata.cbj_en) {
1193 regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1194 regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
1195 regmap_update_bits(rt286->regmap,
1196 RT286_CBJ_CTRL1, 0xf000, 0xb000);
1197 } else {
1198 regmap_update_bits(rt286->regmap,
1199 RT286_CBJ_CTRL1, 0xf000, 0x5000);
1200 }
1201
1202 mdelay(10);
1203
1204 if (!rt286->pdata.gpio2_en)
1205 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1206 else
1207 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1208
1209 mdelay(10);
1210
1211 regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
1212
1213 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1214 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
1215
1216
1217 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1218 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1219 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1220
1221 if (dmi_check_system(dmi_dell_dino)) {
1222 regmap_update_bits(rt286->regmap,
1223 RT286_SET_GPIO_MASK, 0x40, 0x40);
1224 regmap_update_bits(rt286->regmap,
1225 RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
1226 regmap_update_bits(rt286->regmap,
1227 RT286_SET_GPIO_DATA, 0x40, 0x40);
1228 regmap_update_bits(rt286->regmap,
1229 RT286_GPIO_CTRL, 0xc, 0x8);
1230 }
1231
1232 if (rt286->i2c->irq) {
1233 ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1234 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1235 if (ret != 0) {
1236 dev_err(&i2c->dev,
1237 "Failed to reguest IRQ: %d\n", ret);
1238 return ret;
1239 }
1240 }
1241
1242 ret = devm_snd_soc_register_component(&i2c->dev,
1243 &soc_component_dev_rt286,
1244 rt286_dai, ARRAY_SIZE(rt286_dai));
1245
1246 return ret;
1247 }
1248
1249 static int rt286_i2c_remove(struct i2c_client *i2c)
1250 {
1251 struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1252
1253 if (i2c->irq)
1254 free_irq(i2c->irq, rt286);
1255
1256 return 0;
1257 }
1258
1259
1260 static struct i2c_driver rt286_i2c_driver = {
1261 .driver = {
1262 .name = "rt286",
1263 .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1264 },
1265 .probe = rt286_i2c_probe,
1266 .remove = rt286_i2c_remove,
1267 .id_table = rt286_i2c_id,
1268 };
1269
1270 module_i2c_driver(rt286_i2c_driver);
1271
1272 MODULE_DESCRIPTION("ASoC RT286 driver");
1273 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1274 MODULE_LICENSE("GPL");