1
2
3
4
5
6
7
8
9 #ifndef __RT5670_DSP_H__
10 #define __RT5670_DSP_H__
11
12 #define RT5670_DSP_CTRL1 0xe0
13 #define RT5670_DSP_CTRL2 0xe1
14 #define RT5670_DSP_CTRL3 0xe2
15 #define RT5670_DSP_CTRL4 0xe3
16 #define RT5670_DSP_CTRL5 0xe4
17
18
19 #define RT5670_DSP_CMD_MASK (0xff << 8)
20 #define RT5670_DSP_CMD_PE (0x0d << 8)
21 #define RT5670_DSP_CMD_MW (0x3b << 8)
22 #define RT5670_DSP_CMD_MR (0x37 << 8)
23 #define RT5670_DSP_CMD_RR (0x60 << 8)
24 #define RT5670_DSP_CMD_RW (0x68 << 8)
25 #define RT5670_DSP_REG_DATHI (0x26 << 8)
26 #define RT5670_DSP_REG_DATLO (0x25 << 8)
27 #define RT5670_DSP_CLK_MASK (0x3 << 6)
28 #define RT5670_DSP_CLK_SFT 6
29 #define RT5670_DSP_CLK_768K (0x0 << 6)
30 #define RT5670_DSP_CLK_384K (0x1 << 6)
31 #define RT5670_DSP_CLK_192K (0x2 << 6)
32 #define RT5670_DSP_CLK_96K (0x3 << 6)
33 #define RT5670_DSP_BUSY_MASK (0x1 << 5)
34 #define RT5670_DSP_RW_MASK (0x1 << 4)
35 #define RT5670_DSP_DL_MASK (0x3 << 2)
36 #define RT5670_DSP_DL_0 (0x0 << 2)
37 #define RT5670_DSP_DL_1 (0x1 << 2)
38 #define RT5670_DSP_DL_2 (0x2 << 2)
39 #define RT5670_DSP_DL_3 (0x3 << 2)
40 #define RT5670_DSP_I2C_AL_16 (0x1 << 1)
41 #define RT5670_DSP_CMD_EN (0x1)
42
43 struct rt5670_dsp_param {
44 u16 cmd_fmt;
45 u16 addr;
46 u16 data;
47 u8 cmd;
48 };
49
50 #endif
51