root/sound/soc/codecs/msm8916-wcd-analog.c

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DEFINITIONS

This source file includes following definitions.
  1. pm8916_wcd_analog_micbias_enable
  2. pm8916_wcd_analog_enable_micbias_ext
  3. pm8916_wcd_analog_enable_micbias_int
  4. pm8916_wcd_analog_enable_micbias_ext1
  5. pm8916_wcd_analog_enable_micbias_ext2
  6. pm8916_wcd_analog_enable_micbias_int1
  7. pm8916_mbhc_configure_bias
  8. pm8916_wcd_setup_mbhc
  9. pm8916_wcd_analog_enable_micbias_int2
  10. pm8916_wcd_analog_enable_adc
  11. pm8916_wcd_analog_enable_spk_pa
  12. pm8916_wcd_analog_probe
  13. pm8916_wcd_analog_remove
  14. pm8916_wcd_analog_set_jack
  15. mbhc_btn_release_irq_handler
  16. mbhc_btn_press_irq_handler
  17. pm8916_mbhc_switch_irq_handler
  18. pm8916_wcd_analog_parse_dt
  19. pm8916_wcd_analog_spmi_probe
  20. pm8916_wcd_analog_spmi_remove

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2016, The Linux Foundation. All rights reserved.
   3 
   4 #include <linux/module.h>
   5 #include <linux/err.h>
   6 #include <linux/kernel.h>
   7 #include <linux/delay.h>
   8 #include <linux/regulator/consumer.h>
   9 #include <linux/types.h>
  10 #include <linux/clk.h>
  11 #include <linux/of.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/regmap.h>
  14 #include <sound/soc.h>
  15 #include <sound/pcm.h>
  16 #include <sound/pcm_params.h>
  17 #include <sound/tlv.h>
  18 #include <sound/jack.h>
  19 
  20 #define CDC_D_REVISION1                 (0xf000)
  21 #define CDC_D_PERPH_SUBTYPE             (0xf005)
  22 #define CDC_D_INT_EN_SET                (0x015)
  23 #define CDC_D_INT_EN_CLR                (0x016)
  24 #define MBHC_SWITCH_INT                 BIT(7)
  25 #define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6)
  26 #define MBHC_BUTTON_PRESS_DET           BIT(5)
  27 #define MBHC_BUTTON_RELEASE_DET         BIT(4)
  28 #define CDC_D_CDC_RST_CTL               (0xf046)
  29 #define RST_CTL_DIG_SW_RST_N_MASK       BIT(7)
  30 #define RST_CTL_DIG_SW_RST_N_RESET      0
  31 #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7)
  32 
  33 #define CDC_D_CDC_TOP_CLK_CTL           (0xf048)
  34 #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3))
  35 #define TOP_CLK_CTL_A_MCLK_EN_ENABLE     BIT(2)
  36 #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE   BIT(3)
  37 
  38 #define CDC_D_CDC_ANA_CLK_CTL           (0xf049)
  39 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
  40 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN     BIT(0)
  41 #define ANA_CLK_CTL_EAR_HPHL_CLK_EN     BIT(1)
  42 #define ANA_CLK_CTL_SPKR_CLK_EN_MASK    BIT(4)
  43 #define ANA_CLK_CTL_SPKR_CLK_EN BIT(4)
  44 #define ANA_CLK_CTL_TXA_CLK25_EN        BIT(5)
  45 
  46 #define CDC_D_CDC_DIG_CLK_CTL           (0xf04A)
  47 #define DIG_CLK_CTL_RXD1_CLK_EN         BIT(0)
  48 #define DIG_CLK_CTL_RXD2_CLK_EN         BIT(1)
  49 #define DIG_CLK_CTL_RXD3_CLK_EN         BIT(2)
  50 #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK  BIT(3)
  51 #define DIG_CLK_CTL_D_MBHC_CLK_EN       BIT(3)
  52 #define DIG_CLK_CTL_TXD_CLK_EN          BIT(4)
  53 #define DIG_CLK_CTL_NCP_CLK_EN_MASK     BIT(6)
  54 #define DIG_CLK_CTL_NCP_CLK_EN          BIT(6)
  55 #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7)
  56 #define DIG_CLK_CTL_RXD_PDM_CLK_EN      BIT(7)
  57 
  58 #define CDC_D_CDC_CONN_TX1_CTL          (0xf050)
  59 #define CONN_TX1_SERIAL_TX1_MUX         GENMASK(1, 0)
  60 #define CONN_TX1_SERIAL_TX1_ADC_1       0x0
  61 #define CONN_TX1_SERIAL_TX1_RX_PDM_LB   0x1
  62 #define CONN_TX1_SERIAL_TX1_ZERO        0x2
  63 
  64 #define CDC_D_CDC_CONN_TX2_CTL          (0xf051)
  65 #define CONN_TX2_SERIAL_TX2_MUX         GENMASK(1, 0)
  66 #define CONN_TX2_SERIAL_TX2_ADC_2       0x0
  67 #define CONN_TX2_SERIAL_TX2_RX_PDM_LB   0x1
  68 #define CONN_TX2_SERIAL_TX2_ZERO        0x2
  69 #define CDC_D_CDC_CONN_HPHR_DAC_CTL     (0xf052)
  70 #define CDC_D_CDC_CONN_RX1_CTL          (0xf053)
  71 #define CDC_D_CDC_CONN_RX2_CTL          (0xf054)
  72 #define CDC_D_CDC_CONN_RX3_CTL          (0xf055)
  73 #define CDC_D_CDC_CONN_RX_LB_CTL        (0xf056)
  74 #define CDC_D_SEC_ACCESS                (0xf0D0)
  75 #define CDC_D_PERPH_RESET_CTL3          (0xf0DA)
  76 #define CDC_D_PERPH_RESET_CTL4          (0xf0DB)
  77 #define CDC_A_REVISION1                 (0xf100)
  78 #define CDC_A_REVISION2                 (0xf101)
  79 #define CDC_A_REVISION3                 (0xf102)
  80 #define CDC_A_REVISION4                 (0xf103)
  81 #define CDC_A_PERPH_TYPE                (0xf104)
  82 #define CDC_A_PERPH_SUBTYPE             (0xf105)
  83 #define CDC_A_INT_RT_STS                (0xf110)
  84 #define CDC_A_INT_SET_TYPE              (0xf111)
  85 #define CDC_A_INT_POLARITY_HIGH         (0xf112)
  86 #define CDC_A_INT_POLARITY_LOW          (0xf113)
  87 #define CDC_A_INT_LATCHED_CLR           (0xf114)
  88 #define CDC_A_INT_EN_SET                (0xf115)
  89 #define CDC_A_INT_EN_CLR                (0xf116)
  90 #define CDC_A_INT_LATCHED_STS           (0xf118)
  91 #define CDC_A_INT_PENDING_STS           (0xf119)
  92 #define CDC_A_INT_MID_SEL               (0xf11A)
  93 #define CDC_A_INT_PRIORITY              (0xf11B)
  94 #define CDC_A_MICB_1_EN                 (0xf140)
  95 #define MICB_1_EN_MICB_ENABLE           BIT(7)
  96 #define MICB_1_EN_BYP_CAP_MASK          BIT(6)
  97 #define MICB_1_EN_NO_EXT_BYP_CAP        BIT(6)
  98 #define MICB_1_EN_EXT_BYP_CAP           0
  99 #define MICB_1_EN_PULL_DOWN_EN_MASK     BIT(5)
 100 #define MICB_1_EN_PULL_DOWN_EN_ENABLE   BIT(5)
 101 #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1)
 102 #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA     (0x4)
 103 #define MICB_1_EN_PULL_UP_EN_MASK       BIT(4)
 104 #define MICB_1_EN_TX3_GND_SEL_MASK      BIT(0)
 105 #define MICB_1_EN_TX3_GND_SEL_TX_GND    0
 106 
 107 #define CDC_A_MICB_1_VAL                (0xf141)
 108 #define MICB_MIN_VAL 1600
 109 #define MICB_STEP_SIZE 50
 110 #define MICB_VOLTAGE_REGVAL(v)          (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3)
 111 #define MICB_1_VAL_MICB_OUT_VAL_MASK    GENMASK(7, 3)
 112 #define MICB_1_VAL_MICB_OUT_VAL_V2P70V  ((0x16)  << 3)
 113 #define MICB_1_VAL_MICB_OUT_VAL_V1P80V  ((0x4)  << 3)
 114 #define CDC_A_MICB_1_CTL                (0xf142)
 115 
 116 #define MICB_1_CTL_CFILT_REF_SEL_MASK           BIT(1)
 117 #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF        BIT(1)
 118 #define MICB_1_CTL_EXT_PRECHARG_EN_MASK         BIT(5)
 119 #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE       BIT(5)
 120 #define MICB_1_CTL_INT_PRECHARG_BYP_MASK        BIT(6)
 121 #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL     BIT(6)
 122 
 123 #define CDC_A_MICB_1_INT_RBIAS                  (0xf143)
 124 #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK        BIT(7)
 125 #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE      BIT(7)
 126 #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE     0
 127 
 128 #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK       BIT(6)
 129 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6)
 130 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND        0
 131 
 132 #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK        BIT(4)
 133 #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE      BIT(4)
 134 #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE     0
 135 #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK       BIT(3)
 136 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3)
 137 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND        0
 138 
 139 #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK        BIT(1)
 140 #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE      BIT(1)
 141 #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE     0
 142 #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK       BIT(0)
 143 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)
 144 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND        0
 145 
 146 #define CDC_A_MICB_2_EN                 (0xf144)
 147 #define CDC_A_MICB_2_EN_ENABLE          BIT(7)
 148 #define CDC_A_MICB_2_PULL_DOWN_EN_MASK  BIT(5)
 149 #define CDC_A_MICB_2_PULL_DOWN_EN       BIT(5)
 150 #define CDC_A_TX_1_2_ATEST_CTL_2        (0xf145)
 151 #define CDC_A_MASTER_BIAS_CTL           (0xf146)
 152 #define CDC_A_MBHC_DET_CTL_1            (0xf147)
 153 #define CDC_A_MBHC_DET_CTL_L_DET_EN                     BIT(7)
 154 #define CDC_A_MBHC_DET_CTL_GND_DET_EN                   BIT(6)
 155 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION      BIT(5)
 156 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL        (0)
 157 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK           BIT(5)
 158 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT          (5)
 159 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO           BIT(4)
 160 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL         BIT(3)
 161 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK           GENMASK(4, 3)
 162 #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN                 BIT(2)
 163 #define CDC_A_MBHC_DET_CTL_2            (0xf150)
 164 #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0  (BIT(7) | BIT(6))
 165 #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5)
 166 #define CDC_A_PLUG_TYPE_MASK                            GENMASK(4, 3)
 167 #define CDC_A_HPHL_PLUG_TYPE_NO                         BIT(4)
 168 #define CDC_A_GND_PLUG_TYPE_NO                          BIT(3)
 169 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK     BIT(0)
 170 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN          BIT(0)
 171 #define CDC_A_MBHC_FSM_CTL              (0xf151)
 172 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN                  BIT(7)
 173 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK             BIT(7)
 174 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA        (0x3 << 4)
 175 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK           GENMASK(6, 4)
 176 #define CDC_A_MBHC_DBNC_TIMER           (0xf152)
 177 #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS           BIT(3)
 178 #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS      (0x9 << 4)
 179 #define CDC_A_MBHC_BTN0_ZDET_CTL_0      (0xf153)
 180 #define CDC_A_MBHC_BTN1_ZDET_CTL_1      (0xf154)
 181 #define CDC_A_MBHC_BTN2_ZDET_CTL_2      (0xf155)
 182 #define CDC_A_MBHC_BTN3_CTL             (0xf156)
 183 #define CDC_A_MBHC_BTN4_CTL             (0xf157)
 184 #define CDC_A_MBHC_BTN_VREF_FINE_SHIFT  (2)
 185 #define CDC_A_MBHC_BTN_VREF_FINE_MASK   GENMASK(4, 2)
 186 #define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5)
 187 #define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5)
 188 #define CDC_A_MBHC_BTN_VREF_MASK        (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \
 189                                         CDC_A_MBHC_BTN_VREF_FINE_MASK)
 190 #define CDC_A_MBHC_RESULT_1             (0xf158)
 191 #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK     GENMASK(4, 0)
 192 #define CDC_A_TX_1_EN                   (0xf160)
 193 #define CDC_A_TX_2_EN                   (0xf161)
 194 #define CDC_A_TX_1_2_TEST_CTL_1         (0xf162)
 195 #define CDC_A_TX_1_2_TEST_CTL_2         (0xf163)
 196 #define CDC_A_TX_1_2_ATEST_CTL          (0xf164)
 197 #define CDC_A_TX_1_2_OPAMP_BIAS         (0xf165)
 198 #define CDC_A_TX_3_EN                   (0xf167)
 199 #define CDC_A_NCP_EN                    (0xf180)
 200 #define CDC_A_NCP_CLK                   (0xf181)
 201 #define CDC_A_NCP_FBCTRL                (0xf183)
 202 #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK        BIT(5)
 203 #define CDC_A_NCP_FBCTRL_FB_CLK_INV             BIT(5)
 204 #define CDC_A_NCP_BIAS                  (0xf184)
 205 #define CDC_A_NCP_VCTRL                 (0xf185)
 206 #define CDC_A_NCP_TEST                  (0xf186)
 207 #define CDC_A_NCP_CLIM_ADDR             (0xf187)
 208 #define CDC_A_RX_CLOCK_DIVIDER          (0xf190)
 209 #define CDC_A_RX_COM_OCP_CTL            (0xf191)
 210 #define CDC_A_RX_COM_OCP_COUNT          (0xf192)
 211 #define CDC_A_RX_COM_BIAS_DAC           (0xf193)
 212 #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK         BIT(7)
 213 #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE       BIT(7)
 214 #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK         BIT(0)
 215 #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE       BIT(0)
 216 
 217 #define CDC_A_RX_HPH_BIAS_PA            (0xf194)
 218 #define CDC_A_RX_HPH_BIAS_LDO_OCP       (0xf195)
 219 #define CDC_A_RX_HPH_BIAS_CNP           (0xf196)
 220 #define CDC_A_RX_HPH_CNP_EN             (0xf197)
 221 #define CDC_A_RX_HPH_L_PA_DAC_CTL       (0xf19B)
 222 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK     BIT(1)
 223 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET    BIT(1)
 224 #define CDC_A_RX_HPH_R_PA_DAC_CTL       (0xf19D)
 225 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET  BIT(1)
 226 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
 227 
 228 #define CDC_A_RX_EAR_CTL                        (0xf19E)
 229 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK         BIT(0)
 230 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE       BIT(0)
 231 
 232 #define CDC_A_SPKR_DAC_CTL              (0xf1B0)
 233 #define SPKR_DAC_CTL_DAC_RESET_MASK     BIT(4)
 234 #define SPKR_DAC_CTL_DAC_RESET_NORMAL   0
 235 
 236 #define CDC_A_SPKR_DRV_CTL              (0xf1B2)
 237 #define SPKR_DRV_CTL_DEF_MASK           0xEF
 238 #define SPKR_DRV_CLASSD_PA_EN_MASK      BIT(7)
 239 #define SPKR_DRV_CLASSD_PA_EN_ENABLE    BIT(7)
 240 #define SPKR_DRV_CAL_EN                 BIT(6)
 241 #define SPKR_DRV_SETTLE_EN              BIT(5)
 242 #define SPKR_DRV_FW_EN                  BIT(3)
 243 #define SPKR_DRV_BOOST_SET              BIT(2)
 244 #define SPKR_DRV_CMFB_SET               BIT(1)
 245 #define SPKR_DRV_GAIN_SET               BIT(0)
 246 #define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \
 247                 SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \
 248                 SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \
 249                 SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET)
 250 #define CDC_A_SPKR_OCP_CTL              (0xf1B4)
 251 #define CDC_A_SPKR_PWRSTG_CTL           (0xf1B5)
 252 #define SPKR_PWRSTG_CTL_DAC_EN_MASK     BIT(0)
 253 #define SPKR_PWRSTG_CTL_DAC_EN          BIT(0)
 254 #define SPKR_PWRSTG_CTL_MASK            0xE0
 255 #define SPKR_PWRSTG_CTL_BBM_MASK        BIT(7)
 256 #define SPKR_PWRSTG_CTL_BBM_EN          BIT(7)
 257 #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK  BIT(6)
 258 #define SPKR_PWRSTG_CTL_HBRDGE_EN       BIT(6)
 259 #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK   BIT(5)
 260 #define SPKR_PWRSTG_CTL_CLAMP_EN        BIT(5)
 261 
 262 #define CDC_A_SPKR_DRV_DBG              (0xf1B7)
 263 #define CDC_A_CURRENT_LIMIT             (0xf1C0)
 264 #define CDC_A_BOOST_EN_CTL              (0xf1C3)
 265 #define CDC_A_SLOPE_COMP_IP_ZERO        (0xf1C4)
 266 #define CDC_A_SEC_ACCESS                (0xf1D0)
 267 #define CDC_A_PERPH_RESET_CTL3          (0xf1DA)
 268 #define CDC_A_PERPH_RESET_CTL4          (0xf1DB)
 269 
 270 #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
 271                         SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
 272 #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 273                                     SNDRV_PCM_FMTBIT_S32_LE)
 274 
 275 static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
 276                SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4;
 277 static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET;
 278 
 279 static const char * const supply_names[] = {
 280         "vdd-cdc-io",
 281         "vdd-cdc-tx-rx-cx",
 282 };
 283 
 284 #define MBHC_MAX_BUTTONS        (5)
 285 
 286 struct pm8916_wcd_analog_priv {
 287         u16 pmic_rev;
 288         u16 codec_version;
 289         bool    mbhc_btn_enabled;
 290         /* special event to detect accessory type */
 291         int     mbhc_btn0_released;
 292         bool    detect_accessory_type;
 293         struct clk *mclk;
 294         struct snd_soc_component *component;
 295         struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
 296         struct snd_soc_jack *jack;
 297         bool hphl_jack_type_normally_open;
 298         bool gnd_jack_type_normally_open;
 299         /* Voltage threshold when internal current source of 100uA is used */
 300         u32 vref_btn_cs[MBHC_MAX_BUTTONS];
 301         /* Voltage threshold when microphone bias is ON */
 302         u32 vref_btn_micb[MBHC_MAX_BUTTONS];
 303         unsigned int micbias1_cap_mode;
 304         unsigned int micbias2_cap_mode;
 305         unsigned int micbias_mv;
 306 };
 307 
 308 static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" };
 309 static const char *const rdac2_mux_text[] = { "RX1", "RX2" };
 310 static const char *const hph_text[] = { "ZERO", "Switch", };
 311 
 312 static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT(
 313                                         ARRAY_SIZE(hph_text), hph_text);
 314 
 315 static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum);
 316 static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum);
 317 
 318 /* ADC2 MUX */
 319 static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT(
 320                         ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
 321 
 322 /* RDAC2 MUX */
 323 static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE(
 324                         CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text);
 325 
 326 static const struct snd_kcontrol_new spkr_switch[] = {
 327         SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0)
 328 };
 329 
 330 static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM(
 331                                         "RDAC2 MUX Mux", rdac2_mux_enum);
 332 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM(
 333                                         "ADC2 MUX Mux", adc2_enum);
 334 
 335 /* Analog Gain control 0 dB to +24 dB in 6 dB steps */
 336 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);
 337 
 338 static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = {
 339         SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain),
 340         SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain),
 341         SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain),
 342 };
 343 
 344 static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component)
 345 {
 346         struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
 347 
 348         snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
 349                             MICB_1_CTL_EXT_PRECHARG_EN_MASK |
 350                             MICB_1_CTL_INT_PRECHARG_BYP_MASK,
 351                             MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL
 352                             | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE);
 353 
 354         if (wcd->micbias_mv) {
 355                 snd_soc_component_update_bits(component, CDC_A_MICB_1_VAL,
 356                                     MICB_1_VAL_MICB_OUT_VAL_MASK,
 357                                     MICB_VOLTAGE_REGVAL(wcd->micbias_mv));
 358                 /*
 359                  * Special headset needs MICBIAS as 2.7V so wait for
 360                  * 50 msec for the MICBIAS to reach 2.7 volts.
 361                  */
 362                 if (wcd->micbias_mv >= 2700)
 363                         msleep(50);
 364         }
 365 
 366         snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
 367                             MICB_1_CTL_EXT_PRECHARG_EN_MASK |
 368                             MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0);
 369 
 370 }
 371 
 372 static int pm8916_wcd_analog_enable_micbias_ext(struct snd_soc_component
 373                                                  *component, int event,
 374                                                  int reg, unsigned int cap_mode)
 375 {
 376         switch (event) {
 377         case SND_SOC_DAPM_POST_PMU:
 378                 pm8916_wcd_analog_micbias_enable(component);
 379                 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
 380                                     MICB_1_EN_BYP_CAP_MASK, cap_mode);
 381                 break;
 382         }
 383 
 384         return 0;
 385 }
 386 
 387 static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_component
 388                                                  *component, int event,
 389                                                  int reg, u32 cap_mode)
 390 {
 391 
 392         switch (event) {
 393         case SND_SOC_DAPM_PRE_PMU:
 394                 snd_soc_component_update_bits(component, reg, MICB_1_EN_PULL_DOWN_EN_MASK, 0);
 395                 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
 396                                     MICB_1_EN_OPA_STG2_TAIL_CURR_MASK,
 397                                     MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA);
 398 
 399                 break;
 400         case SND_SOC_DAPM_POST_PMU:
 401                 pm8916_wcd_analog_micbias_enable(component);
 402                 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
 403                                     MICB_1_EN_BYP_CAP_MASK, cap_mode);
 404                 break;
 405         }
 406 
 407         return 0;
 408 }
 409 
 410 static int pm8916_wcd_analog_enable_micbias_ext1(struct
 411                                                   snd_soc_dapm_widget
 412                                                   *w, struct snd_kcontrol
 413                                                   *kcontrol, int event)
 414 {
 415         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 416         struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
 417 
 418         return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg,
 419                                                      wcd->micbias1_cap_mode);
 420 }
 421 
 422 static int pm8916_wcd_analog_enable_micbias_ext2(struct
 423                                                   snd_soc_dapm_widget
 424                                                   *w, struct snd_kcontrol
 425                                                   *kcontrol, int event)
 426 {
 427         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 428         struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
 429 
 430         return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg,
 431                                                      wcd->micbias2_cap_mode);
 432 
 433 }
 434 
 435 static int pm8916_wcd_analog_enable_micbias_int1(struct
 436                                                   snd_soc_dapm_widget
 437                                                   *w, struct snd_kcontrol
 438                                                   *kcontrol, int event)
 439 {
 440         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 441         struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
 442 
 443         switch (event) {
 444         case SND_SOC_DAPM_PRE_PMU:
 445                 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS,
 446                                     MICB_1_INT_TX1_INT_RBIAS_EN_MASK,
 447                                     MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE);
 448                 break;
 449         }
 450 
 451         return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg,
 452                                                      wcd->micbias1_cap_mode);
 453 }
 454 
 455 static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv,
 456                                       bool micbias2_enabled)
 457 {
 458         struct snd_soc_component *component = priv->component;
 459         u32 coarse, fine, reg_val, reg_addr;
 460         int *vrefs, i;
 461 
 462         if (!micbias2_enabled) { /* use internal 100uA Current source */
 463                 /* Enable internal 2.2k Internal Rbias Resistor */
 464                 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS,
 465                                     MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
 466                                     MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
 467                 /* Remove pull down on MIC BIAS2 */
 468                 snd_soc_component_update_bits(component, CDC_A_MICB_2_EN,
 469                                    CDC_A_MICB_2_PULL_DOWN_EN_MASK,
 470                                    0);
 471                 /* enable 100uA internal current source */
 472                 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
 473                                     CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK,
 474                                     CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA);
 475         }
 476         snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
 477                         CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK,
 478                         CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN);
 479 
 480         if (micbias2_enabled)
 481                 vrefs = &priv->vref_btn_micb[0];
 482         else
 483                 vrefs = &priv->vref_btn_cs[0];
 484 
 485         /* program vref ranges for all the buttons */
 486         reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0;
 487         for (i = 0; i <  MBHC_MAX_BUTTONS; i++) {
 488                 /* split mv in to coarse parts of 100mv & fine parts of 12mv */
 489                 coarse = (vrefs[i] / 100);
 490                 fine = ((vrefs[i] % 100) / 12);
 491                 reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) |
 492                          (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT);
 493                 snd_soc_component_update_bits(component, reg_addr,
 494                                CDC_A_MBHC_BTN_VREF_MASK,
 495                                reg_val);
 496                 reg_addr++;
 497         }
 498 
 499         return 0;
 500 }
 501 
 502 static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd)
 503 {
 504         struct snd_soc_component *component = wcd->component;
 505         bool micbias_enabled = false;
 506         u32 plug_type = 0;
 507         u32 int_en_mask;
 508 
 509         snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_1,
 510                       CDC_A_MBHC_DET_CTL_L_DET_EN |
 511                       CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION |
 512                       CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO |
 513                       CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN);
 514 
 515         if (wcd->hphl_jack_type_normally_open)
 516                 plug_type |= CDC_A_HPHL_PLUG_TYPE_NO;
 517 
 518         if (wcd->gnd_jack_type_normally_open)
 519                 plug_type |= CDC_A_GND_PLUG_TYPE_NO;
 520 
 521         snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_2,
 522                       CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 |
 523                       CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD |
 524                       plug_type |
 525                       CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN);
 526 
 527 
 528         snd_soc_component_write(component, CDC_A_MBHC_DBNC_TIMER,
 529                       CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS |
 530                       CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS);
 531 
 532         /* enable MBHC clock */
 533         snd_soc_component_update_bits(component, CDC_D_CDC_DIG_CLK_CTL,
 534                             DIG_CLK_CTL_D_MBHC_CLK_EN_MASK,
 535                             DIG_CLK_CTL_D_MBHC_CLK_EN);
 536 
 537         if (snd_soc_component_read32(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE)
 538                 micbias_enabled = true;
 539 
 540         pm8916_mbhc_configure_bias(wcd, micbias_enabled);
 541 
 542         int_en_mask = MBHC_SWITCH_INT;
 543         if (wcd->mbhc_btn_enabled)
 544                 int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET;
 545 
 546         snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0);
 547         snd_soc_component_update_bits(component, CDC_D_INT_EN_SET, int_en_mask, int_en_mask);
 548         wcd->mbhc_btn0_released = false;
 549         wcd->detect_accessory_type = true;
 550 }
 551 
 552 static int pm8916_wcd_analog_enable_micbias_int2(struct
 553                                                   snd_soc_dapm_widget
 554                                                   *w, struct snd_kcontrol
 555                                                   *kcontrol, int event)
 556 {
 557         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 558         struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
 559 
 560         switch (event) {
 561         case SND_SOC_DAPM_PRE_PMU:
 562                 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS,
 563                                     MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
 564                                     MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
 565                 break;
 566         case SND_SOC_DAPM_POST_PMU:
 567                 pm8916_mbhc_configure_bias(wcd, true);
 568                 break;
 569         case SND_SOC_DAPM_POST_PMD:
 570                 pm8916_mbhc_configure_bias(wcd, false);
 571                 break;
 572         }
 573 
 574         return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg,
 575                                                      wcd->micbias2_cap_mode);
 576 }
 577 
 578 static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w,
 579                                          struct snd_kcontrol *kcontrol,
 580                                          int event)
 581 {
 582         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 583         u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2;
 584         u8 init_bit_shift;
 585 
 586         if (w->reg == CDC_A_TX_1_EN)
 587                 init_bit_shift = 5;
 588         else
 589                 init_bit_shift = 4;
 590 
 591         switch (event) {
 592         case SND_SOC_DAPM_PRE_PMU:
 593                 if (w->reg == CDC_A_TX_2_EN)
 594                         snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
 595                                             MICB_1_CTL_CFILT_REF_SEL_MASK,
 596                                             MICB_1_CTL_CFILT_REF_SEL_HPF_REF);
 597                 /*
 598                  * Add delay of 10 ms to give sufficient time for the voltage
 599                  * to shoot up and settle so that the txfe init does not
 600                  * happen when the input voltage is changing too much.
 601                  */
 602                 usleep_range(10000, 10010);
 603                 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift,
 604                                     1 << init_bit_shift);
 605                 switch (w->reg) {
 606                 case CDC_A_TX_1_EN:
 607                         snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
 608                                             CONN_TX1_SERIAL_TX1_MUX,
 609                                             CONN_TX1_SERIAL_TX1_ADC_1);
 610                         break;
 611                 case CDC_A_TX_2_EN:
 612                 case CDC_A_TX_3_EN:
 613                         snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
 614                                             CONN_TX2_SERIAL_TX2_MUX,
 615                                             CONN_TX2_SERIAL_TX2_ADC_2);
 616                         break;
 617                 }
 618                 break;
 619         case SND_SOC_DAPM_POST_PMU:
 620                 /*
 621                  * Add delay of 12 ms before deasserting the init
 622                  * to reduce the tx pop
 623                  */
 624                 usleep_range(12000, 12010);
 625                 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00);
 626                 break;
 627         case SND_SOC_DAPM_POST_PMD:
 628                 switch (w->reg) {
 629                 case CDC_A_TX_1_EN:
 630                         snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
 631                                             CONN_TX1_SERIAL_TX1_MUX,
 632                                             CONN_TX1_SERIAL_TX1_ZERO);
 633                         break;
 634                 case CDC_A_TX_2_EN:
 635                         snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
 636                                             MICB_1_CTL_CFILT_REF_SEL_MASK, 0);
 637                         /* fall through */
 638                 case CDC_A_TX_3_EN:
 639                         snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
 640                                             CONN_TX2_SERIAL_TX2_MUX,
 641                                             CONN_TX2_SERIAL_TX2_ZERO);
 642                         break;
 643                 }
 644 
 645 
 646                 break;
 647         }
 648         return 0;
 649 }
 650 
 651 static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w,
 652                                             struct snd_kcontrol *kcontrol,
 653                                             int event)
 654 {
 655         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 656 
 657         switch (event) {
 658         case SND_SOC_DAPM_PRE_PMU:
 659                 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
 660                                     SPKR_PWRSTG_CTL_DAC_EN_MASK |
 661                                     SPKR_PWRSTG_CTL_BBM_MASK |
 662                                     SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
 663                                     SPKR_PWRSTG_CTL_CLAMP_EN_MASK,
 664                                     SPKR_PWRSTG_CTL_DAC_EN|
 665                                     SPKR_PWRSTG_CTL_BBM_EN |
 666                                     SPKR_PWRSTG_CTL_HBRDGE_EN |
 667                                     SPKR_PWRSTG_CTL_CLAMP_EN);
 668 
 669                 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
 670                                     RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK,
 671                                     RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE);
 672                 break;
 673         case SND_SOC_DAPM_POST_PMU:
 674                 snd_soc_component_update_bits(component, CDC_A_SPKR_DRV_CTL,
 675                                     SPKR_DRV_CTL_DEF_MASK,
 676                                     SPKR_DRV_CTL_DEF_VAL);
 677                 snd_soc_component_update_bits(component, w->reg,
 678                                     SPKR_DRV_CLASSD_PA_EN_MASK,
 679                                     SPKR_DRV_CLASSD_PA_EN_ENABLE);
 680                 break;
 681         case SND_SOC_DAPM_POST_PMD:
 682                 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
 683                                     SPKR_PWRSTG_CTL_DAC_EN_MASK|
 684                                     SPKR_PWRSTG_CTL_BBM_MASK |
 685                                     SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
 686                                     SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0);
 687 
 688                 snd_soc_component_update_bits(component, CDC_A_SPKR_DAC_CTL,
 689                                     SPKR_DAC_CTL_DAC_RESET_MASK,
 690                                     SPKR_DAC_CTL_DAC_RESET_NORMAL);
 691                 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
 692                                     RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0);
 693                 break;
 694         }
 695         return 0;
 696 }
 697 
 698 static const struct reg_default wcd_reg_defaults_2_0[] = {
 699         {CDC_A_RX_COM_OCP_CTL, 0xD1},
 700         {CDC_A_RX_COM_OCP_COUNT, 0xFF},
 701         {CDC_D_SEC_ACCESS, 0xA5},
 702         {CDC_D_PERPH_RESET_CTL3, 0x0F},
 703         {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F},
 704         {CDC_A_NCP_FBCTRL, 0x28},
 705         {CDC_A_SPKR_DRV_CTL, 0x69},
 706         {CDC_A_SPKR_DRV_DBG, 0x01},
 707         {CDC_A_BOOST_EN_CTL, 0x5F},
 708         {CDC_A_SLOPE_COMP_IP_ZERO, 0x88},
 709         {CDC_A_SEC_ACCESS, 0xA5},
 710         {CDC_A_PERPH_RESET_CTL3, 0x0F},
 711         {CDC_A_CURRENT_LIMIT, 0x82},
 712         {CDC_A_SPKR_DAC_CTL, 0x03},
 713         {CDC_A_SPKR_OCP_CTL, 0xE1},
 714         {CDC_A_MASTER_BIAS_CTL, 0x30},
 715 };
 716 
 717 static int pm8916_wcd_analog_probe(struct snd_soc_component *component)
 718 {
 719         struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
 720         int err, reg;
 721 
 722         err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
 723         if (err != 0) {
 724                 dev_err(component->dev, "failed to enable regulators (%d)\n", err);
 725                 return err;
 726         }
 727 
 728         snd_soc_component_init_regmap(component,
 729                                   dev_get_regmap(component->dev->parent, NULL));
 730         snd_soc_component_set_drvdata(component, priv);
 731         priv->pmic_rev = snd_soc_component_read32(component, CDC_D_REVISION1);
 732         priv->codec_version = snd_soc_component_read32(component, CDC_D_PERPH_SUBTYPE);
 733 
 734         dev_info(component->dev, "PMIC REV: %d\t CODEC Version: %d\n",
 735                  priv->pmic_rev, priv->codec_version);
 736 
 737         snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01);
 738         snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01);
 739 
 740         for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)
 741                 snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg,
 742                               wcd_reg_defaults_2_0[reg].def);
 743 
 744         priv->component = component;
 745 
 746         snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
 747                             RST_CTL_DIG_SW_RST_N_MASK,
 748                             RST_CTL_DIG_SW_RST_N_REMOVE_RESET);
 749 
 750         pm8916_wcd_setup_mbhc(priv);
 751 
 752         return 0;
 753 }
 754 
 755 static void pm8916_wcd_analog_remove(struct snd_soc_component *component)
 756 {
 757         struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
 758 
 759         snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
 760                             RST_CTL_DIG_SW_RST_N_MASK, 0);
 761 
 762         regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
 763                                       priv->supplies);
 764 }
 765 
 766 static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = {
 767 
 768         {"PDM_RX1", NULL, "PDM Playback"},
 769         {"PDM_RX2", NULL, "PDM Playback"},
 770         {"PDM_RX3", NULL, "PDM Playback"},
 771         {"PDM Capture", NULL, "PDM_TX"},
 772 
 773         /* ADC Connections */
 774         {"PDM_TX", NULL, "ADC2"},
 775         {"PDM_TX", NULL, "ADC3"},
 776         {"ADC2", NULL, "ADC2 MUX"},
 777         {"ADC3", NULL, "ADC2 MUX"},
 778         {"ADC2 MUX", "INP2", "ADC2_INP2"},
 779         {"ADC2 MUX", "INP3", "ADC2_INP3"},
 780 
 781         {"PDM_TX", NULL, "ADC1"},
 782         {"ADC1", NULL, "AMIC1"},
 783         {"ADC2_INP2", NULL, "AMIC2"},
 784         {"ADC2_INP3", NULL, "AMIC3"},
 785 
 786         /* RDAC Connections */
 787         {"HPHR DAC", NULL, "RDAC2 MUX"},
 788         {"RDAC2 MUX", "RX1", "PDM_RX1"},
 789         {"RDAC2 MUX", "RX2", "PDM_RX2"},
 790         {"HPHL DAC", NULL, "PDM_RX1"},
 791         {"PDM_RX1", NULL, "RXD1_CLK"},
 792         {"PDM_RX2", NULL, "RXD2_CLK"},
 793         {"PDM_RX3", NULL, "RXD3_CLK"},
 794 
 795         {"PDM_RX1", NULL, "RXD_PDM_CLK"},
 796         {"PDM_RX2", NULL, "RXD_PDM_CLK"},
 797         {"PDM_RX3", NULL, "RXD_PDM_CLK"},
 798 
 799         {"ADC1", NULL, "TXD_CLK"},
 800         {"ADC2", NULL, "TXD_CLK"},
 801         {"ADC3", NULL, "TXD_CLK"},
 802 
 803         {"ADC1", NULL, "TXA_CLK25"},
 804         {"ADC2", NULL, "TXA_CLK25"},
 805         {"ADC3", NULL, "TXA_CLK25"},
 806 
 807         {"PDM_RX1", NULL, "A_MCLK2"},
 808         {"PDM_RX2", NULL, "A_MCLK2"},
 809         {"PDM_RX3", NULL, "A_MCLK2"},
 810 
 811         {"PDM_TX", NULL, "A_MCLK2"},
 812         {"A_MCLK2", NULL, "A_MCLK"},
 813 
 814         /* Headset (RX MIX1 and RX MIX2) */
 815         {"HEADPHONE", NULL, "HPHL PA"},
 816         {"HEADPHONE", NULL, "HPHR PA"},
 817 
 818         {"HPHL PA", NULL, "EAR_HPHL_CLK"},
 819         {"HPHR PA", NULL, "EAR_HPHR_CLK"},
 820 
 821         {"CP", NULL, "NCP_CLK"},
 822 
 823         {"HPHL PA", NULL, "HPHL"},
 824         {"HPHR PA", NULL, "HPHR"},
 825         {"HPHL PA", NULL, "CP"},
 826         {"HPHL PA", NULL, "RX_BIAS"},
 827         {"HPHR PA", NULL, "CP"},
 828         {"HPHR PA", NULL, "RX_BIAS"},
 829         {"HPHL", "Switch", "HPHL DAC"},
 830         {"HPHR", "Switch", "HPHR DAC"},
 831 
 832         {"RX_BIAS", NULL, "DAC_REF"},
 833 
 834         {"SPK_OUT", NULL, "SPK PA"},
 835         {"SPK PA", NULL, "RX_BIAS"},
 836         {"SPK PA", NULL, "SPKR_CLK"},
 837         {"SPK PA", NULL, "SPK DAC"},
 838         {"SPK DAC", "Switch", "PDM_RX3"},
 839 
 840         {"MIC BIAS Internal1", NULL, "INT_LDO_H"},
 841         {"MIC BIAS Internal2", NULL, "INT_LDO_H"},
 842         {"MIC BIAS External1", NULL, "INT_LDO_H"},
 843         {"MIC BIAS External2", NULL, "INT_LDO_H"},
 844         {"MIC BIAS Internal1", NULL, "vdd-micbias"},
 845         {"MIC BIAS Internal2", NULL, "vdd-micbias"},
 846         {"MIC BIAS External1", NULL, "vdd-micbias"},
 847         {"MIC BIAS External2", NULL, "vdd-micbias"},
 848 };
 849 
 850 static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = {
 851 
 852         SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
 853         SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
 854         SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
 855         SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
 856 
 857         SND_SOC_DAPM_INPUT("AMIC1"),
 858         SND_SOC_DAPM_INPUT("AMIC3"),
 859         SND_SOC_DAPM_INPUT("AMIC2"),
 860         SND_SOC_DAPM_OUTPUT("HEADPHONE"),
 861 
 862         /* RX stuff */
 863         SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
 864 
 865         SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),
 866         SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux),
 867         SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
 868                            0),
 869         SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),
 870         SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux),
 871         SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
 872                            0),
 873         SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
 874                            spkr_switch, ARRAY_SIZE(spkr_switch)),
 875 
 876         /* Speaker */
 877         SND_SOC_DAPM_OUTPUT("SPK_OUT"),
 878         SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL,
 879                            6, 0, NULL, 0,
 880                            pm8916_wcd_analog_enable_spk_pa,
 881                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 882                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
 883         SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0),
 884         SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0),
 885 
 886         SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),
 887         SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),
 888 
 889         /* TX */
 890         SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_EN, 7, 0,
 891                             pm8916_wcd_analog_enable_micbias_int1,
 892                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 893                             SND_SOC_DAPM_POST_PMD),
 894         SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_2_EN, 7, 0,
 895                             pm8916_wcd_analog_enable_micbias_int2,
 896                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 897                             SND_SOC_DAPM_POST_PMD),
 898 
 899         SND_SOC_DAPM_SUPPLY("MIC BIAS External1", CDC_A_MICB_1_EN, 7, 0,
 900                             pm8916_wcd_analog_enable_micbias_ext1,
 901                             SND_SOC_DAPM_POST_PMU),
 902         SND_SOC_DAPM_SUPPLY("MIC BIAS External2", CDC_A_MICB_2_EN, 7, 0,
 903                             pm8916_wcd_analog_enable_micbias_ext2,
 904                             SND_SOC_DAPM_POST_PMU),
 905 
 906         SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0,
 907                            pm8916_wcd_analog_enable_adc,
 908                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 909                            SND_SOC_DAPM_POST_PMD),
 910         SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0,
 911                            pm8916_wcd_analog_enable_adc,
 912                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 913                            SND_SOC_DAPM_POST_PMD),
 914         SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0,
 915                            pm8916_wcd_analog_enable_adc,
 916                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 917                            SND_SOC_DAPM_POST_PMD),
 918 
 919         SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 920         SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
 921 
 922         SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
 923         SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
 924 
 925         /* Analog path clocks */
 926         SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,
 927                             0),
 928         SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,
 929                             0),
 930         SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),
 931         SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),
 932 
 933         /* Digital path clocks */
 934 
 935         SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),
 936         SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),
 937         SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),
 938 
 939         SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),
 940         SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),
 941         SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,
 942                             0),
 943 
 944         /* System Clock source */
 945         SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),
 946         /* TX ADC and RX DAC Clock source. */
 947         SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),
 948 };
 949 
 950 static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component,
 951                                       struct snd_soc_jack *jack,
 952                                       void *data)
 953 {
 954         struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
 955 
 956         wcd->jack = jack;
 957 
 958         return 0;
 959 }
 960 
 961 static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
 962 {
 963         struct pm8916_wcd_analog_priv *priv = arg;
 964 
 965         if (priv->detect_accessory_type) {
 966                 struct snd_soc_component *component = priv->component;
 967                 u32 val = snd_soc_component_read32(component, CDC_A_MBHC_RESULT_1);
 968 
 969                 /* check if its BTN0 thats released */
 970                 if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK))
 971                         priv->mbhc_btn0_released = true;
 972 
 973         } else {
 974                 snd_soc_jack_report(priv->jack, 0, btn_mask);
 975         }
 976 
 977         return IRQ_HANDLED;
 978 }
 979 
 980 static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg)
 981 {
 982         struct pm8916_wcd_analog_priv *priv = arg;
 983         struct snd_soc_component *component = priv->component;
 984         u32 btn_result;
 985 
 986         btn_result = snd_soc_component_read32(component, CDC_A_MBHC_RESULT_1) &
 987                                   CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK;
 988 
 989         switch (btn_result) {
 990         case 0xf:
 991                 snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask);
 992                 break;
 993         case 0x7:
 994                 snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask);
 995                 break;
 996         case 0x3:
 997                 snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask);
 998                 break;
 999         case 0x1:
1000                 snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask);
1001                 break;
1002         case 0x0:
1003                 /* handle BTN_0 specially for type detection */
1004                 if (!priv->detect_accessory_type)
1005                         snd_soc_jack_report(priv->jack,
1006                                             SND_JACK_BTN_0, btn_mask);
1007                 break;
1008         default:
1009                 dev_err(component->dev,
1010                         "Unexpected button press result (%x)", btn_result);
1011                 break;
1012         }
1013 
1014         return IRQ_HANDLED;
1015 }
1016 
1017 static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg)
1018 {
1019         struct pm8916_wcd_analog_priv *priv = arg;
1020         struct snd_soc_component *component = priv->component;
1021         bool ins = false;
1022 
1023         if (snd_soc_component_read32(component, CDC_A_MBHC_DET_CTL_1) &
1024                                 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK)
1025                 ins = true;
1026 
1027         /* Set the detection type appropriately */
1028         snd_soc_component_update_bits(component, CDC_A_MBHC_DET_CTL_1,
1029                             CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK,
1030                             (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT));
1031 
1032 
1033         if (ins) { /* hs insertion */
1034                 bool micbias_enabled = false;
1035 
1036                 if (snd_soc_component_read32(component, CDC_A_MICB_2_EN) &
1037                                 CDC_A_MICB_2_EN_ENABLE)
1038                         micbias_enabled = true;
1039 
1040                 pm8916_mbhc_configure_bias(priv, micbias_enabled);
1041 
1042                 /*
1043                  * if only a btn0 press event is receive just before
1044                  * insert event then its a 3 pole headphone else if
1045                  * both press and release event received then its
1046                  * a headset.
1047                  */
1048                 if (priv->mbhc_btn0_released)
1049                         snd_soc_jack_report(priv->jack,
1050                                             SND_JACK_HEADSET, hs_jack_mask);
1051                 else
1052                         snd_soc_jack_report(priv->jack,
1053                                             SND_JACK_HEADPHONE, hs_jack_mask);
1054 
1055                 priv->detect_accessory_type = false;
1056 
1057         } else { /* removal */
1058                 snd_soc_jack_report(priv->jack, 0, hs_jack_mask);
1059                 priv->detect_accessory_type = true;
1060                 priv->mbhc_btn0_released = false;
1061         }
1062 
1063         return IRQ_HANDLED;
1064 }
1065 
1066 static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = {
1067         [0] = {
1068                .name = "pm8916_wcd_analog_pdm_rx",
1069                .id = 0,
1070                .playback = {
1071                             .stream_name = "PDM Playback",
1072                             .rates = MSM8916_WCD_ANALOG_RATES,
1073                             .formats = MSM8916_WCD_ANALOG_FORMATS,
1074                             .channels_min = 1,
1075                             .channels_max = 3,
1076                             },
1077                },
1078         [1] = {
1079                .name = "pm8916_wcd_analog_pdm_tx",
1080                .id = 1,
1081                .capture = {
1082                            .stream_name = "PDM Capture",
1083                            .rates = MSM8916_WCD_ANALOG_RATES,
1084                            .formats = MSM8916_WCD_ANALOG_FORMATS,
1085                            .channels_min = 1,
1086                            .channels_max = 4,
1087                            },
1088                },
1089 };
1090 
1091 static const struct snd_soc_component_driver pm8916_wcd_analog = {
1092         .probe                  = pm8916_wcd_analog_probe,
1093         .remove                 = pm8916_wcd_analog_remove,
1094         .set_jack               = pm8916_wcd_analog_set_jack,
1095         .controls               = pm8916_wcd_analog_snd_controls,
1096         .num_controls           = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),
1097         .dapm_widgets           = pm8916_wcd_analog_dapm_widgets,
1098         .num_dapm_widgets       = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets),
1099         .dapm_routes            = pm8916_wcd_analog_audio_map,
1100         .num_dapm_routes        = ARRAY_SIZE(pm8916_wcd_analog_audio_map),
1101         .idle_bias_on           = 1,
1102         .use_pmdown_time        = 1,
1103         .endianness             = 1,
1104         .non_legacy_dai_naming  = 1,
1105 };
1106 
1107 static int pm8916_wcd_analog_parse_dt(struct device *dev,
1108                                        struct pm8916_wcd_analog_priv *priv)
1109 {
1110         int rval;
1111 
1112         if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap"))
1113                 priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP;
1114         else
1115                 priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
1116 
1117         if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap"))
1118                 priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP;
1119         else
1120                 priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
1121 
1122         of_property_read_u32(dev->of_node, "qcom,micbias-lvl",
1123                              &priv->micbias_mv);
1124 
1125         if (of_property_read_bool(dev->of_node,
1126                                   "qcom,hphl-jack-type-normally-open"))
1127                 priv->hphl_jack_type_normally_open = true;
1128         else
1129                 priv->hphl_jack_type_normally_open = false;
1130 
1131         if (of_property_read_bool(dev->of_node,
1132                                   "qcom,gnd-jack-type-normally-open"))
1133                 priv->gnd_jack_type_normally_open = true;
1134         else
1135                 priv->gnd_jack_type_normally_open = false;
1136 
1137         priv->mbhc_btn_enabled = true;
1138         rval = of_property_read_u32_array(dev->of_node,
1139                                           "qcom,mbhc-vthreshold-low",
1140                                           &priv->vref_btn_cs[0],
1141                                           MBHC_MAX_BUTTONS);
1142         if (rval < 0) {
1143                 priv->mbhc_btn_enabled = false;
1144         } else {
1145                 rval = of_property_read_u32_array(dev->of_node,
1146                                                   "qcom,mbhc-vthreshold-high",
1147                                                   &priv->vref_btn_micb[0],
1148                                                   MBHC_MAX_BUTTONS);
1149                 if (rval < 0)
1150                         priv->mbhc_btn_enabled = false;
1151         }
1152 
1153         if (!priv->mbhc_btn_enabled)
1154                 dev_err(dev,
1155                         "DT property missing, MBHC btn detection disabled\n");
1156 
1157 
1158         return 0;
1159 }
1160 
1161 static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev)
1162 {
1163         struct pm8916_wcd_analog_priv *priv;
1164         struct device *dev = &pdev->dev;
1165         int ret, i, irq;
1166 
1167         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1168         if (!priv)
1169                 return -ENOMEM;
1170 
1171         ret = pm8916_wcd_analog_parse_dt(dev, priv);
1172         if (ret < 0)
1173                 return ret;
1174 
1175         priv->mclk = devm_clk_get(dev, "mclk");
1176         if (IS_ERR(priv->mclk)) {
1177                 dev_err(dev, "failed to get mclk\n");
1178                 return PTR_ERR(priv->mclk);
1179         }
1180 
1181         for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1182                 priv->supplies[i].supply = supply_names[i];
1183 
1184         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
1185                                     priv->supplies);
1186         if (ret) {
1187                 dev_err(dev, "Failed to get regulator supplies %d\n", ret);
1188                 return ret;
1189         }
1190 
1191         ret = clk_prepare_enable(priv->mclk);
1192         if (ret < 0) {
1193                 dev_err(dev, "failed to enable mclk %d\n", ret);
1194                 return ret;
1195         }
1196 
1197         irq = platform_get_irq_byname(pdev, "mbhc_switch_int");
1198         if (irq < 0)
1199                 return irq;
1200 
1201         ret = devm_request_threaded_irq(dev, irq, NULL,
1202                                pm8916_mbhc_switch_irq_handler,
1203                                IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
1204                                IRQF_ONESHOT,
1205                                "mbhc switch irq", priv);
1206         if (ret)
1207                 dev_err(dev, "cannot request mbhc switch irq\n");
1208 
1209         if (priv->mbhc_btn_enabled) {
1210                 irq = platform_get_irq_byname(pdev, "mbhc_but_press_det");
1211                 if (irq < 0)
1212                         return irq;
1213 
1214                 ret = devm_request_threaded_irq(dev, irq, NULL,
1215                                        mbhc_btn_press_irq_handler,
1216                                        IRQF_TRIGGER_RISING |
1217                                        IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1218                                        "mbhc btn press irq", priv);
1219                 if (ret)
1220                         dev_err(dev, "cannot request mbhc button press irq\n");
1221 
1222                 irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det");
1223                 if (irq < 0)
1224                         return irq;
1225 
1226                 ret = devm_request_threaded_irq(dev, irq, NULL,
1227                                        mbhc_btn_release_irq_handler,
1228                                        IRQF_TRIGGER_RISING |
1229                                        IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1230                                        "mbhc btn release irq", priv);
1231                 if (ret)
1232                         dev_err(dev, "cannot request mbhc button release irq\n");
1233 
1234         }
1235 
1236         dev_set_drvdata(dev, priv);
1237 
1238         return devm_snd_soc_register_component(dev, &pm8916_wcd_analog,
1239                                       pm8916_wcd_analog_dai,
1240                                       ARRAY_SIZE(pm8916_wcd_analog_dai));
1241 }
1242 
1243 static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev)
1244 {
1245         struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev);
1246 
1247         clk_disable_unprepare(priv->mclk);
1248 
1249         return 0;
1250 }
1251 
1252 static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = {
1253         { .compatible = "qcom,pm8916-wcd-analog-codec", },
1254         { }
1255 };
1256 
1257 MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table);
1258 
1259 static struct platform_driver pm8916_wcd_analog_spmi_driver = {
1260         .driver = {
1261                    .name = "qcom,pm8916-wcd-spmi-codec",
1262                    .of_match_table = pm8916_wcd_analog_spmi_match_table,
1263         },
1264         .probe = pm8916_wcd_analog_spmi_probe,
1265         .remove = pm8916_wcd_analog_spmi_remove,
1266 };
1267 
1268 module_platform_driver(pm8916_wcd_analog_spmi_driver);
1269 
1270 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
1271 MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver");
1272 MODULE_LICENSE("GPL v2");

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