This source file includes following definitions.
- rt5668_volatile_register
- rt5668_readable_register
- rt5668_reset
- rt5668_sel_asrc_clk_src
- rt5668_button_detect
- rt5668_enable_push_button_irq
- rt5668_headset_detect
- rt5668_irq
- rt5668_jd_check_handler
- rt5668_set_jack_detect
- rt5668_jack_detect_handler
- rt5668_div_sel
- set_dmic_clk
- set_filter_clk
- is_sys_clk_from_pll1
- is_using_asrc
- rt5668_hp_event
- set_dmic_power
- rt5655_set_verf
- rt5668_set_tdm_slot
- rt5668_hw_params
- rt5668_set_dai_fmt
- rt5668_set_component_sysclk
- rt5668_set_component_pll
- rt5668_set_bclk_ratio
- rt5668_set_bias_level
- rt5668_probe
- rt5668_remove
- rt5668_suspend
- rt5668_resume
- rt5668_parse_dt
- rt5668_calibrate
- rt5668_i2c_probe
- rt5668_i2c_shutdown
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8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/acpi.h>
18 #include <linux/gpio.h>
19 #include <linux/of_gpio.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/mutex.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/jack.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30 #include <sound/rt5668.h>
31
32 #include "rl6231.h"
33 #include "rt5668.h"
34
35 #define RT5668_NUM_SUPPLIES 3
36
37 static const char *rt5668_supply_names[RT5668_NUM_SUPPLIES] = {
38 "AVDD",
39 "MICVDD",
40 "VBAT",
41 };
42
43 struct rt5668_priv {
44 struct snd_soc_component *component;
45 struct rt5668_platform_data pdata;
46 struct regmap *regmap;
47 struct snd_soc_jack *hs_jack;
48 struct regulator_bulk_data supplies[RT5668_NUM_SUPPLIES];
49 struct delayed_work jack_detect_work;
50 struct delayed_work jd_check_work;
51 struct mutex calibrate_mutex;
52
53 int sysclk;
54 int sysclk_src;
55 int lrck[RT5668_AIFS];
56 int bclk[RT5668_AIFS];
57 int master[RT5668_AIFS];
58
59 int pll_src;
60 int pll_in;
61 int pll_out;
62
63 int jack_type;
64 };
65
66 static const struct reg_default rt5668_reg[] = {
67 {0x0002, 0x8080},
68 {0x0003, 0x8000},
69 {0x0005, 0x0000},
70 {0x0006, 0x0000},
71 {0x0008, 0x800f},
72 {0x000b, 0x0000},
73 {0x0010, 0x4040},
74 {0x0011, 0x0000},
75 {0x0012, 0x1404},
76 {0x0013, 0x1000},
77 {0x0014, 0xa00a},
78 {0x0015, 0x0404},
79 {0x0016, 0x0404},
80 {0x0019, 0xafaf},
81 {0x001c, 0x2f2f},
82 {0x001f, 0x0000},
83 {0x0022, 0x5757},
84 {0x0023, 0x0039},
85 {0x0024, 0x000b},
86 {0x0026, 0xc0c4},
87 {0x0029, 0x8080},
88 {0x002a, 0xa0a0},
89 {0x002b, 0x0300},
90 {0x0030, 0x0000},
91 {0x003c, 0x0080},
92 {0x0044, 0x0c0c},
93 {0x0049, 0x0000},
94 {0x0061, 0x0000},
95 {0x0062, 0x0000},
96 {0x0063, 0x003f},
97 {0x0064, 0x0000},
98 {0x0065, 0x0000},
99 {0x0066, 0x0030},
100 {0x0067, 0x0000},
101 {0x006b, 0x0000},
102 {0x006c, 0x0000},
103 {0x006d, 0x2200},
104 {0x006e, 0x0a10},
105 {0x0070, 0x8000},
106 {0x0071, 0x8000},
107 {0x0073, 0x0000},
108 {0x0074, 0x0000},
109 {0x0075, 0x0002},
110 {0x0076, 0x0001},
111 {0x0079, 0x0000},
112 {0x007a, 0x0000},
113 {0x007b, 0x0000},
114 {0x007c, 0x0100},
115 {0x007e, 0x0000},
116 {0x0080, 0x0000},
117 {0x0081, 0x0000},
118 {0x0082, 0x0000},
119 {0x0083, 0x0000},
120 {0x0084, 0x0000},
121 {0x0085, 0x0000},
122 {0x0086, 0x0005},
123 {0x0087, 0x0000},
124 {0x0088, 0x0000},
125 {0x008c, 0x0003},
126 {0x008d, 0x0000},
127 {0x008e, 0x0060},
128 {0x008f, 0x1000},
129 {0x0091, 0x0c26},
130 {0x0092, 0x0073},
131 {0x0093, 0x0000},
132 {0x0094, 0x0080},
133 {0x0098, 0x0000},
134 {0x009a, 0x0000},
135 {0x009b, 0x0000},
136 {0x009c, 0x0000},
137 {0x009d, 0x0000},
138 {0x009e, 0x100c},
139 {0x009f, 0x0000},
140 {0x00a0, 0x0000},
141 {0x00a3, 0x0002},
142 {0x00a4, 0x0001},
143 {0x00ae, 0x2040},
144 {0x00af, 0x0000},
145 {0x00b6, 0x0000},
146 {0x00b7, 0x0000},
147 {0x00b8, 0x0000},
148 {0x00b9, 0x0002},
149 {0x00be, 0x0000},
150 {0x00c0, 0x0160},
151 {0x00c1, 0x82a0},
152 {0x00c2, 0x0000},
153 {0x00d0, 0x0000},
154 {0x00d1, 0x2244},
155 {0x00d2, 0x3300},
156 {0x00d3, 0x2200},
157 {0x00d4, 0x0000},
158 {0x00d9, 0x0009},
159 {0x00da, 0x0000},
160 {0x00db, 0x0000},
161 {0x00dc, 0x00c0},
162 {0x00dd, 0x2220},
163 {0x00de, 0x3131},
164 {0x00df, 0x3131},
165 {0x00e0, 0x3131},
166 {0x00e2, 0x0000},
167 {0x00e3, 0x4000},
168 {0x00e4, 0x0aa0},
169 {0x00e5, 0x3131},
170 {0x00e6, 0x3131},
171 {0x00e7, 0x3131},
172 {0x00e8, 0x3131},
173 {0x00ea, 0xb320},
174 {0x00eb, 0x0000},
175 {0x00f0, 0x0000},
176 {0x00f1, 0x00d0},
177 {0x00f2, 0x00d0},
178 {0x00f6, 0x0000},
179 {0x00fa, 0x0000},
180 {0x00fb, 0x0000},
181 {0x00fc, 0x0000},
182 {0x00fd, 0x0000},
183 {0x00fe, 0x10ec},
184 {0x00ff, 0x6530},
185 {0x0100, 0xa0a0},
186 {0x010b, 0x0000},
187 {0x010c, 0xae00},
188 {0x010d, 0xaaa0},
189 {0x010e, 0x8aa2},
190 {0x010f, 0x02a2},
191 {0x0110, 0xc000},
192 {0x0111, 0x04a2},
193 {0x0112, 0x2800},
194 {0x0113, 0x0000},
195 {0x0117, 0x0100},
196 {0x0125, 0x0410},
197 {0x0132, 0x6026},
198 {0x0136, 0x5555},
199 {0x0138, 0x3700},
200 {0x013a, 0x2000},
201 {0x013b, 0x2000},
202 {0x013c, 0x2005},
203 {0x013f, 0x0000},
204 {0x0142, 0x0000},
205 {0x0145, 0x0002},
206 {0x0146, 0x0000},
207 {0x0147, 0x0000},
208 {0x0148, 0x0000},
209 {0x0149, 0x0000},
210 {0x0150, 0x79a1},
211 {0x0151, 0x0000},
212 {0x0160, 0x4ec0},
213 {0x0161, 0x0080},
214 {0x0162, 0x0200},
215 {0x0163, 0x0800},
216 {0x0164, 0x0000},
217 {0x0165, 0x0000},
218 {0x0166, 0x0000},
219 {0x0167, 0x000f},
220 {0x0168, 0x000f},
221 {0x0169, 0x0021},
222 {0x0190, 0x413d},
223 {0x0194, 0x0000},
224 {0x0195, 0x0000},
225 {0x0197, 0x0022},
226 {0x0198, 0x0000},
227 {0x0199, 0x0000},
228 {0x01af, 0x0000},
229 {0x01b0, 0x0400},
230 {0x01b1, 0x0000},
231 {0x01b2, 0x0000},
232 {0x01b3, 0x0000},
233 {0x01b4, 0x0000},
234 {0x01b5, 0x0000},
235 {0x01b6, 0x01c3},
236 {0x01b7, 0x02a0},
237 {0x01b8, 0x03e9},
238 {0x01b9, 0x1389},
239 {0x01ba, 0xc351},
240 {0x01bb, 0x0009},
241 {0x01bc, 0x0018},
242 {0x01bd, 0x002a},
243 {0x01be, 0x004c},
244 {0x01bf, 0x0097},
245 {0x01c0, 0x433d},
246 {0x01c1, 0x2800},
247 {0x01c2, 0x0000},
248 {0x01c3, 0x0000},
249 {0x01c4, 0x0000},
250 {0x01c5, 0x0000},
251 {0x01c6, 0x0000},
252 {0x01c7, 0x0000},
253 {0x01c8, 0x40af},
254 {0x01c9, 0x0702},
255 {0x01ca, 0x0000},
256 {0x01cb, 0x0000},
257 {0x01cc, 0x5757},
258 {0x01cd, 0x5757},
259 {0x01ce, 0x5757},
260 {0x01cf, 0x5757},
261 {0x01d0, 0x5757},
262 {0x01d1, 0x5757},
263 {0x01d2, 0x5757},
264 {0x01d3, 0x5757},
265 {0x01d4, 0x5757},
266 {0x01d5, 0x5757},
267 {0x01d6, 0x0000},
268 {0x01d7, 0x0008},
269 {0x01d8, 0x0029},
270 {0x01d9, 0x3333},
271 {0x01da, 0x0000},
272 {0x01db, 0x0004},
273 {0x01dc, 0x0000},
274 {0x01de, 0x7c00},
275 {0x01df, 0x0320},
276 {0x01e0, 0x06a1},
277 {0x01e1, 0x0000},
278 {0x01e2, 0x0000},
279 {0x01e3, 0x0000},
280 {0x01e4, 0x0000},
281 {0x01e6, 0x0001},
282 {0x01e7, 0x0000},
283 {0x01e8, 0x0000},
284 {0x01ea, 0x0000},
285 {0x01eb, 0x0000},
286 {0x01ec, 0x0000},
287 {0x01ed, 0x0000},
288 {0x01ee, 0x0000},
289 {0x01ef, 0x0000},
290 {0x01f0, 0x0000},
291 {0x01f1, 0x0000},
292 {0x01f2, 0x0000},
293 {0x01f3, 0x0000},
294 {0x01f4, 0x0000},
295 {0x0210, 0x6297},
296 {0x0211, 0xa005},
297 {0x0212, 0x824c},
298 {0x0213, 0xf7ff},
299 {0x0214, 0xf24c},
300 {0x0215, 0x0102},
301 {0x0216, 0x00a3},
302 {0x0217, 0x0048},
303 {0x0218, 0xa2c0},
304 {0x0219, 0x0400},
305 {0x021a, 0x00c8},
306 {0x021b, 0x00c0},
307 {0x021c, 0x0000},
308 {0x0250, 0x4500},
309 {0x0251, 0x40b3},
310 {0x0252, 0x0000},
311 {0x0253, 0x0000},
312 {0x0254, 0x0000},
313 {0x0255, 0x0000},
314 {0x0256, 0x0000},
315 {0x0257, 0x0000},
316 {0x0258, 0x0000},
317 {0x0259, 0x0000},
318 {0x025a, 0x0005},
319 {0x0270, 0x0000},
320 {0x02ff, 0x0110},
321 {0x0300, 0x001f},
322 {0x0301, 0x032c},
323 {0x0302, 0x5f21},
324 {0x0303, 0x4000},
325 {0x0304, 0x4000},
326 {0x0305, 0x06d5},
327 {0x0306, 0x8000},
328 {0x0307, 0x0700},
329 {0x0310, 0x4560},
330 {0x0311, 0xa4a8},
331 {0x0312, 0x7418},
332 {0x0313, 0x0000},
333 {0x0314, 0x0006},
334 {0x0315, 0xffff},
335 {0x0316, 0xc400},
336 {0x0317, 0x0000},
337 {0x03c0, 0x7e00},
338 {0x03c1, 0x8000},
339 {0x03c2, 0x8000},
340 {0x03c3, 0x8000},
341 {0x03c4, 0x8000},
342 {0x03c5, 0x8000},
343 {0x03c6, 0x8000},
344 {0x03c7, 0x8000},
345 {0x03c8, 0x8000},
346 {0x03c9, 0x8000},
347 {0x03ca, 0x8000},
348 {0x03cb, 0x8000},
349 {0x03cc, 0x8000},
350 {0x03d0, 0x0000},
351 {0x03d1, 0x0000},
352 {0x03d2, 0x0000},
353 {0x03d3, 0x0000},
354 {0x03d4, 0x2000},
355 {0x03d5, 0x2000},
356 {0x03d6, 0x0000},
357 {0x03d7, 0x0000},
358 {0x03d8, 0x2000},
359 {0x03d9, 0x2000},
360 {0x03da, 0x2000},
361 {0x03db, 0x2000},
362 {0x03dc, 0x0000},
363 {0x03dd, 0x0000},
364 {0x03de, 0x0000},
365 {0x03df, 0x2000},
366 {0x03e0, 0x0000},
367 {0x03e1, 0x0000},
368 {0x03e2, 0x0000},
369 {0x03e3, 0x0000},
370 {0x03e4, 0x0000},
371 {0x03e5, 0x0000},
372 {0x03e6, 0x0000},
373 {0x03e7, 0x0000},
374 {0x03e8, 0x0000},
375 {0x03e9, 0x0000},
376 {0x03ea, 0x0000},
377 {0x03eb, 0x0000},
378 {0x03ec, 0x0000},
379 {0x03ed, 0x0000},
380 {0x03ee, 0x0000},
381 {0x03ef, 0x0000},
382 {0x03f0, 0x0800},
383 {0x03f1, 0x0800},
384 {0x03f2, 0x0800},
385 {0x03f3, 0x0800},
386 };
387
388 static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
389 {
390 switch (reg) {
391 case RT5668_RESET:
392 case RT5668_CBJ_CTRL_2:
393 case RT5668_INT_ST_1:
394 case RT5668_4BTN_IL_CMD_1:
395 case RT5668_AJD1_CTRL:
396 case RT5668_HP_CALIB_CTRL_1:
397 case RT5668_DEVICE_ID:
398 case RT5668_I2C_MODE:
399 case RT5668_HP_CALIB_CTRL_10:
400 case RT5668_EFUSE_CTRL_2:
401 case RT5668_JD_TOP_VC_VTRL:
402 case RT5668_HP_IMP_SENS_CTRL_19:
403 case RT5668_IL_CMD_1:
404 case RT5668_SAR_IL_CMD_2:
405 case RT5668_SAR_IL_CMD_4:
406 case RT5668_SAR_IL_CMD_10:
407 case RT5668_SAR_IL_CMD_11:
408 case RT5668_EFUSE_CTRL_6...RT5668_EFUSE_CTRL_11:
409 case RT5668_HP_CALIB_STA_1...RT5668_HP_CALIB_STA_11:
410 return true;
411 default:
412 return false;
413 }
414 }
415
416 static bool rt5668_readable_register(struct device *dev, unsigned int reg)
417 {
418 switch (reg) {
419 case RT5668_RESET:
420 case RT5668_VERSION_ID:
421 case RT5668_VENDOR_ID:
422 case RT5668_DEVICE_ID:
423 case RT5668_HP_CTRL_1:
424 case RT5668_HP_CTRL_2:
425 case RT5668_HPL_GAIN:
426 case RT5668_HPR_GAIN:
427 case RT5668_I2C_CTRL:
428 case RT5668_CBJ_BST_CTRL:
429 case RT5668_CBJ_CTRL_1:
430 case RT5668_CBJ_CTRL_2:
431 case RT5668_CBJ_CTRL_3:
432 case RT5668_CBJ_CTRL_4:
433 case RT5668_CBJ_CTRL_5:
434 case RT5668_CBJ_CTRL_6:
435 case RT5668_CBJ_CTRL_7:
436 case RT5668_DAC1_DIG_VOL:
437 case RT5668_STO1_ADC_DIG_VOL:
438 case RT5668_STO1_ADC_BOOST:
439 case RT5668_HP_IMP_GAIN_1:
440 case RT5668_HP_IMP_GAIN_2:
441 case RT5668_SIDETONE_CTRL:
442 case RT5668_STO1_ADC_MIXER:
443 case RT5668_AD_DA_MIXER:
444 case RT5668_STO1_DAC_MIXER:
445 case RT5668_A_DAC1_MUX:
446 case RT5668_DIG_INF2_DATA:
447 case RT5668_REC_MIXER:
448 case RT5668_CAL_REC:
449 case RT5668_ALC_BACK_GAIN:
450 case RT5668_PWR_DIG_1:
451 case RT5668_PWR_DIG_2:
452 case RT5668_PWR_ANLG_1:
453 case RT5668_PWR_ANLG_2:
454 case RT5668_PWR_ANLG_3:
455 case RT5668_PWR_MIXER:
456 case RT5668_PWR_VOL:
457 case RT5668_CLK_DET:
458 case RT5668_RESET_LPF_CTRL:
459 case RT5668_RESET_HPF_CTRL:
460 case RT5668_DMIC_CTRL_1:
461 case RT5668_I2S1_SDP:
462 case RT5668_I2S2_SDP:
463 case RT5668_ADDA_CLK_1:
464 case RT5668_ADDA_CLK_2:
465 case RT5668_I2S1_F_DIV_CTRL_1:
466 case RT5668_I2S1_F_DIV_CTRL_2:
467 case RT5668_TDM_CTRL:
468 case RT5668_TDM_ADDA_CTRL_1:
469 case RT5668_TDM_ADDA_CTRL_2:
470 case RT5668_DATA_SEL_CTRL_1:
471 case RT5668_TDM_TCON_CTRL:
472 case RT5668_GLB_CLK:
473 case RT5668_PLL_CTRL_1:
474 case RT5668_PLL_CTRL_2:
475 case RT5668_PLL_TRACK_1:
476 case RT5668_PLL_TRACK_2:
477 case RT5668_PLL_TRACK_3:
478 case RT5668_PLL_TRACK_4:
479 case RT5668_PLL_TRACK_5:
480 case RT5668_PLL_TRACK_6:
481 case RT5668_PLL_TRACK_11:
482 case RT5668_SDW_REF_CLK:
483 case RT5668_DEPOP_1:
484 case RT5668_DEPOP_2:
485 case RT5668_HP_CHARGE_PUMP_1:
486 case RT5668_HP_CHARGE_PUMP_2:
487 case RT5668_MICBIAS_1:
488 case RT5668_MICBIAS_2:
489 case RT5668_PLL_TRACK_12:
490 case RT5668_PLL_TRACK_14:
491 case RT5668_PLL2_CTRL_1:
492 case RT5668_PLL2_CTRL_2:
493 case RT5668_PLL2_CTRL_3:
494 case RT5668_PLL2_CTRL_4:
495 case RT5668_RC_CLK_CTRL:
496 case RT5668_I2S_M_CLK_CTRL_1:
497 case RT5668_I2S2_F_DIV_CTRL_1:
498 case RT5668_I2S2_F_DIV_CTRL_2:
499 case RT5668_EQ_CTRL_1:
500 case RT5668_EQ_CTRL_2:
501 case RT5668_IRQ_CTRL_1:
502 case RT5668_IRQ_CTRL_2:
503 case RT5668_IRQ_CTRL_3:
504 case RT5668_IRQ_CTRL_4:
505 case RT5668_INT_ST_1:
506 case RT5668_GPIO_CTRL_1:
507 case RT5668_GPIO_CTRL_2:
508 case RT5668_GPIO_CTRL_3:
509 case RT5668_HP_AMP_DET_CTRL_1:
510 case RT5668_HP_AMP_DET_CTRL_2:
511 case RT5668_MID_HP_AMP_DET:
512 case RT5668_LOW_HP_AMP_DET:
513 case RT5668_DELAY_BUF_CTRL:
514 case RT5668_SV_ZCD_1:
515 case RT5668_SV_ZCD_2:
516 case RT5668_IL_CMD_1:
517 case RT5668_IL_CMD_2:
518 case RT5668_IL_CMD_3:
519 case RT5668_IL_CMD_4:
520 case RT5668_IL_CMD_5:
521 case RT5668_IL_CMD_6:
522 case RT5668_4BTN_IL_CMD_1:
523 case RT5668_4BTN_IL_CMD_2:
524 case RT5668_4BTN_IL_CMD_3:
525 case RT5668_4BTN_IL_CMD_4:
526 case RT5668_4BTN_IL_CMD_5:
527 case RT5668_4BTN_IL_CMD_6:
528 case RT5668_4BTN_IL_CMD_7:
529 case RT5668_ADC_STO1_HP_CTRL_1:
530 case RT5668_ADC_STO1_HP_CTRL_2:
531 case RT5668_AJD1_CTRL:
532 case RT5668_JD1_THD:
533 case RT5668_JD2_THD:
534 case RT5668_JD_CTRL_1:
535 case RT5668_DUMMY_1:
536 case RT5668_DUMMY_2:
537 case RT5668_DUMMY_3:
538 case RT5668_DAC_ADC_DIG_VOL1:
539 case RT5668_BIAS_CUR_CTRL_2:
540 case RT5668_BIAS_CUR_CTRL_3:
541 case RT5668_BIAS_CUR_CTRL_4:
542 case RT5668_BIAS_CUR_CTRL_5:
543 case RT5668_BIAS_CUR_CTRL_6:
544 case RT5668_BIAS_CUR_CTRL_7:
545 case RT5668_BIAS_CUR_CTRL_8:
546 case RT5668_BIAS_CUR_CTRL_9:
547 case RT5668_BIAS_CUR_CTRL_10:
548 case RT5668_VREF_REC_OP_FB_CAP_CTRL:
549 case RT5668_CHARGE_PUMP_1:
550 case RT5668_DIG_IN_CTRL_1:
551 case RT5668_PAD_DRIVING_CTRL:
552 case RT5668_SOFT_RAMP_DEPOP:
553 case RT5668_CHOP_DAC:
554 case RT5668_CHOP_ADC:
555 case RT5668_CALIB_ADC_CTRL:
556 case RT5668_VOL_TEST:
557 case RT5668_SPKVDD_DET_STA:
558 case RT5668_TEST_MODE_CTRL_1:
559 case RT5668_TEST_MODE_CTRL_2:
560 case RT5668_TEST_MODE_CTRL_3:
561 case RT5668_TEST_MODE_CTRL_4:
562 case RT5668_TEST_MODE_CTRL_5:
563 case RT5668_PLL1_INTERNAL:
564 case RT5668_PLL2_INTERNAL:
565 case RT5668_STO_NG2_CTRL_1:
566 case RT5668_STO_NG2_CTRL_2:
567 case RT5668_STO_NG2_CTRL_3:
568 case RT5668_STO_NG2_CTRL_4:
569 case RT5668_STO_NG2_CTRL_5:
570 case RT5668_STO_NG2_CTRL_6:
571 case RT5668_STO_NG2_CTRL_7:
572 case RT5668_STO_NG2_CTRL_8:
573 case RT5668_STO_NG2_CTRL_9:
574 case RT5668_STO_NG2_CTRL_10:
575 case RT5668_STO1_DAC_SIL_DET:
576 case RT5668_SIL_PSV_CTRL1:
577 case RT5668_SIL_PSV_CTRL2:
578 case RT5668_SIL_PSV_CTRL3:
579 case RT5668_SIL_PSV_CTRL4:
580 case RT5668_SIL_PSV_CTRL5:
581 case RT5668_HP_IMP_SENS_CTRL_01:
582 case RT5668_HP_IMP_SENS_CTRL_02:
583 case RT5668_HP_IMP_SENS_CTRL_03:
584 case RT5668_HP_IMP_SENS_CTRL_04:
585 case RT5668_HP_IMP_SENS_CTRL_05:
586 case RT5668_HP_IMP_SENS_CTRL_06:
587 case RT5668_HP_IMP_SENS_CTRL_07:
588 case RT5668_HP_IMP_SENS_CTRL_08:
589 case RT5668_HP_IMP_SENS_CTRL_09:
590 case RT5668_HP_IMP_SENS_CTRL_10:
591 case RT5668_HP_IMP_SENS_CTRL_11:
592 case RT5668_HP_IMP_SENS_CTRL_12:
593 case RT5668_HP_IMP_SENS_CTRL_13:
594 case RT5668_HP_IMP_SENS_CTRL_14:
595 case RT5668_HP_IMP_SENS_CTRL_15:
596 case RT5668_HP_IMP_SENS_CTRL_16:
597 case RT5668_HP_IMP_SENS_CTRL_17:
598 case RT5668_HP_IMP_SENS_CTRL_18:
599 case RT5668_HP_IMP_SENS_CTRL_19:
600 case RT5668_HP_IMP_SENS_CTRL_20:
601 case RT5668_HP_IMP_SENS_CTRL_21:
602 case RT5668_HP_IMP_SENS_CTRL_22:
603 case RT5668_HP_IMP_SENS_CTRL_23:
604 case RT5668_HP_IMP_SENS_CTRL_24:
605 case RT5668_HP_IMP_SENS_CTRL_25:
606 case RT5668_HP_IMP_SENS_CTRL_26:
607 case RT5668_HP_IMP_SENS_CTRL_27:
608 case RT5668_HP_IMP_SENS_CTRL_28:
609 case RT5668_HP_IMP_SENS_CTRL_29:
610 case RT5668_HP_IMP_SENS_CTRL_30:
611 case RT5668_HP_IMP_SENS_CTRL_31:
612 case RT5668_HP_IMP_SENS_CTRL_32:
613 case RT5668_HP_IMP_SENS_CTRL_33:
614 case RT5668_HP_IMP_SENS_CTRL_34:
615 case RT5668_HP_IMP_SENS_CTRL_35:
616 case RT5668_HP_IMP_SENS_CTRL_36:
617 case RT5668_HP_IMP_SENS_CTRL_37:
618 case RT5668_HP_IMP_SENS_CTRL_38:
619 case RT5668_HP_IMP_SENS_CTRL_39:
620 case RT5668_HP_IMP_SENS_CTRL_40:
621 case RT5668_HP_IMP_SENS_CTRL_41:
622 case RT5668_HP_IMP_SENS_CTRL_42:
623 case RT5668_HP_IMP_SENS_CTRL_43:
624 case RT5668_HP_LOGIC_CTRL_1:
625 case RT5668_HP_LOGIC_CTRL_2:
626 case RT5668_HP_LOGIC_CTRL_3:
627 case RT5668_HP_CALIB_CTRL_1:
628 case RT5668_HP_CALIB_CTRL_2:
629 case RT5668_HP_CALIB_CTRL_3:
630 case RT5668_HP_CALIB_CTRL_4:
631 case RT5668_HP_CALIB_CTRL_5:
632 case RT5668_HP_CALIB_CTRL_6:
633 case RT5668_HP_CALIB_CTRL_7:
634 case RT5668_HP_CALIB_CTRL_9:
635 case RT5668_HP_CALIB_CTRL_10:
636 case RT5668_HP_CALIB_CTRL_11:
637 case RT5668_HP_CALIB_STA_1:
638 case RT5668_HP_CALIB_STA_2:
639 case RT5668_HP_CALIB_STA_3:
640 case RT5668_HP_CALIB_STA_4:
641 case RT5668_HP_CALIB_STA_5:
642 case RT5668_HP_CALIB_STA_6:
643 case RT5668_HP_CALIB_STA_7:
644 case RT5668_HP_CALIB_STA_8:
645 case RT5668_HP_CALIB_STA_9:
646 case RT5668_HP_CALIB_STA_10:
647 case RT5668_HP_CALIB_STA_11:
648 case RT5668_SAR_IL_CMD_1:
649 case RT5668_SAR_IL_CMD_2:
650 case RT5668_SAR_IL_CMD_3:
651 case RT5668_SAR_IL_CMD_4:
652 case RT5668_SAR_IL_CMD_5:
653 case RT5668_SAR_IL_CMD_6:
654 case RT5668_SAR_IL_CMD_7:
655 case RT5668_SAR_IL_CMD_8:
656 case RT5668_SAR_IL_CMD_9:
657 case RT5668_SAR_IL_CMD_10:
658 case RT5668_SAR_IL_CMD_11:
659 case RT5668_SAR_IL_CMD_12:
660 case RT5668_SAR_IL_CMD_13:
661 case RT5668_EFUSE_CTRL_1:
662 case RT5668_EFUSE_CTRL_2:
663 case RT5668_EFUSE_CTRL_3:
664 case RT5668_EFUSE_CTRL_4:
665 case RT5668_EFUSE_CTRL_5:
666 case RT5668_EFUSE_CTRL_6:
667 case RT5668_EFUSE_CTRL_7:
668 case RT5668_EFUSE_CTRL_8:
669 case RT5668_EFUSE_CTRL_9:
670 case RT5668_EFUSE_CTRL_10:
671 case RT5668_EFUSE_CTRL_11:
672 case RT5668_JD_TOP_VC_VTRL:
673 case RT5668_DRC1_CTRL_0:
674 case RT5668_DRC1_CTRL_1:
675 case RT5668_DRC1_CTRL_2:
676 case RT5668_DRC1_CTRL_3:
677 case RT5668_DRC1_CTRL_4:
678 case RT5668_DRC1_CTRL_5:
679 case RT5668_DRC1_CTRL_6:
680 case RT5668_DRC1_HARD_LMT_CTRL_1:
681 case RT5668_DRC1_HARD_LMT_CTRL_2:
682 case RT5668_DRC1_PRIV_1:
683 case RT5668_DRC1_PRIV_2:
684 case RT5668_DRC1_PRIV_3:
685 case RT5668_DRC1_PRIV_4:
686 case RT5668_DRC1_PRIV_5:
687 case RT5668_DRC1_PRIV_6:
688 case RT5668_DRC1_PRIV_7:
689 case RT5668_DRC1_PRIV_8:
690 case RT5668_EQ_AUTO_RCV_CTRL1:
691 case RT5668_EQ_AUTO_RCV_CTRL2:
692 case RT5668_EQ_AUTO_RCV_CTRL3:
693 case RT5668_EQ_AUTO_RCV_CTRL4:
694 case RT5668_EQ_AUTO_RCV_CTRL5:
695 case RT5668_EQ_AUTO_RCV_CTRL6:
696 case RT5668_EQ_AUTO_RCV_CTRL7:
697 case RT5668_EQ_AUTO_RCV_CTRL8:
698 case RT5668_EQ_AUTO_RCV_CTRL9:
699 case RT5668_EQ_AUTO_RCV_CTRL10:
700 case RT5668_EQ_AUTO_RCV_CTRL11:
701 case RT5668_EQ_AUTO_RCV_CTRL12:
702 case RT5668_EQ_AUTO_RCV_CTRL13:
703 case RT5668_ADC_L_EQ_LPF1_A1:
704 case RT5668_R_EQ_LPF1_A1:
705 case RT5668_L_EQ_LPF1_H0:
706 case RT5668_R_EQ_LPF1_H0:
707 case RT5668_L_EQ_BPF1_A1:
708 case RT5668_R_EQ_BPF1_A1:
709 case RT5668_L_EQ_BPF1_A2:
710 case RT5668_R_EQ_BPF1_A2:
711 case RT5668_L_EQ_BPF1_H0:
712 case RT5668_R_EQ_BPF1_H0:
713 case RT5668_L_EQ_BPF2_A1:
714 case RT5668_R_EQ_BPF2_A1:
715 case RT5668_L_EQ_BPF2_A2:
716 case RT5668_R_EQ_BPF2_A2:
717 case RT5668_L_EQ_BPF2_H0:
718 case RT5668_R_EQ_BPF2_H0:
719 case RT5668_L_EQ_BPF3_A1:
720 case RT5668_R_EQ_BPF3_A1:
721 case RT5668_L_EQ_BPF3_A2:
722 case RT5668_R_EQ_BPF3_A2:
723 case RT5668_L_EQ_BPF3_H0:
724 case RT5668_R_EQ_BPF3_H0:
725 case RT5668_L_EQ_BPF4_A1:
726 case RT5668_R_EQ_BPF4_A1:
727 case RT5668_L_EQ_BPF4_A2:
728 case RT5668_R_EQ_BPF4_A2:
729 case RT5668_L_EQ_BPF4_H0:
730 case RT5668_R_EQ_BPF4_H0:
731 case RT5668_L_EQ_HPF1_A1:
732 case RT5668_R_EQ_HPF1_A1:
733 case RT5668_L_EQ_HPF1_H0:
734 case RT5668_R_EQ_HPF1_H0:
735 case RT5668_L_EQ_PRE_VOL:
736 case RT5668_R_EQ_PRE_VOL:
737 case RT5668_L_EQ_POST_VOL:
738 case RT5668_R_EQ_POST_VOL:
739 case RT5668_I2C_MODE:
740 return true;
741 default:
742 return false;
743 }
744 }
745
746 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
747 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
748 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
749 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
750
751
752 static const DECLARE_TLV_DB_RANGE(bst_tlv,
753 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
754 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
755 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
756 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
757 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
758 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
759 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
760 );
761
762
763 static const char * const rt5668_data_select[] = {
764 "L/R", "R/L", "L/L", "R/R"
765 };
766
767 static SOC_ENUM_SINGLE_DECL(rt5668_if2_adc_enum,
768 RT5668_DIG_INF2_DATA, RT5668_IF2_ADC_SEL_SFT, rt5668_data_select);
769
770 static SOC_ENUM_SINGLE_DECL(rt5668_if1_01_adc_enum,
771 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC1_SEL_SFT, rt5668_data_select);
772
773 static SOC_ENUM_SINGLE_DECL(rt5668_if1_23_adc_enum,
774 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC2_SEL_SFT, rt5668_data_select);
775
776 static SOC_ENUM_SINGLE_DECL(rt5668_if1_45_adc_enum,
777 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC3_SEL_SFT, rt5668_data_select);
778
779 static SOC_ENUM_SINGLE_DECL(rt5668_if1_67_adc_enum,
780 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC4_SEL_SFT, rt5668_data_select);
781
782 static const struct snd_kcontrol_new rt5668_if2_adc_swap_mux =
783 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5668_if2_adc_enum);
784
785 static const struct snd_kcontrol_new rt5668_if1_01_adc_swap_mux =
786 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5668_if1_01_adc_enum);
787
788 static const struct snd_kcontrol_new rt5668_if1_23_adc_swap_mux =
789 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5668_if1_23_adc_enum);
790
791 static const struct snd_kcontrol_new rt5668_if1_45_adc_swap_mux =
792 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5668_if1_45_adc_enum);
793
794 static const struct snd_kcontrol_new rt5668_if1_67_adc_swap_mux =
795 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5668_if1_67_adc_enum);
796
797 static void rt5668_reset(struct regmap *regmap)
798 {
799 regmap_write(regmap, RT5668_RESET, 0);
800 regmap_write(regmap, RT5668_I2C_MODE, 1);
801 }
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816 int rt5668_sel_asrc_clk_src(struct snd_soc_component *component,
817 unsigned int filter_mask, unsigned int clk_src)
818 {
819
820 switch (clk_src) {
821 case RT5668_CLK_SEL_SYS:
822 case RT5668_CLK_SEL_I2S1_ASRC:
823 case RT5668_CLK_SEL_I2S2_ASRC:
824 break;
825
826 default:
827 return -EINVAL;
828 }
829
830 if (filter_mask & RT5668_DA_STEREO1_FILTER) {
831 snd_soc_component_update_bits(component, RT5668_PLL_TRACK_2,
832 RT5668_FILTER_CLK_SEL_MASK,
833 clk_src << RT5668_FILTER_CLK_SEL_SFT);
834 }
835
836 if (filter_mask & RT5668_AD_STEREO1_FILTER) {
837 snd_soc_component_update_bits(component, RT5668_PLL_TRACK_3,
838 RT5668_FILTER_CLK_SEL_MASK,
839 clk_src << RT5668_FILTER_CLK_SEL_SFT);
840 }
841
842 return 0;
843 }
844 EXPORT_SYMBOL_GPL(rt5668_sel_asrc_clk_src);
845
846 static int rt5668_button_detect(struct snd_soc_component *component)
847 {
848 int btn_type, val;
849
850 val = snd_soc_component_read32(component, RT5668_4BTN_IL_CMD_1);
851 btn_type = val & 0xfff0;
852 snd_soc_component_write(component, RT5668_4BTN_IL_CMD_1, val);
853 pr_debug("%s btn_type=%x\n", __func__, btn_type);
854
855 return btn_type;
856 }
857
858 static void rt5668_enable_push_button_irq(struct snd_soc_component *component,
859 bool enable)
860 {
861 if (enable) {
862 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
863 RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_EN);
864 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13,
865 RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_BTN);
866 snd_soc_component_write(component, RT5668_IL_CMD_1, 0x0040);
867 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
868 RT5668_4BTN_IL_MASK | RT5668_4BTN_IL_RST_MASK,
869 RT5668_4BTN_IL_EN | RT5668_4BTN_IL_NOR);
870 snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3,
871 RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_EN);
872 } else {
873 snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3,
874 RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_DIS);
875 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
876 RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_DIS);
877 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
878 RT5668_4BTN_IL_MASK, RT5668_4BTN_IL_DIS);
879 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
880 RT5668_4BTN_IL_RST_MASK, RT5668_4BTN_IL_RST);
881 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13,
882 RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_TYPE);
883 }
884 }
885
886
887
888
889
890
891
892
893
894
895 static int rt5668_headset_detect(struct snd_soc_component *component,
896 int jack_insert)
897 {
898 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
899 struct snd_soc_dapm_context *dapm =
900 snd_soc_component_get_dapm(component);
901 unsigned int val, count;
902
903 if (jack_insert) {
904 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
905 snd_soc_dapm_sync(dapm);
906 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1,
907 RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_HIGH);
908
909 count = 0;
910 val = snd_soc_component_read32(component, RT5668_CBJ_CTRL_2)
911 & RT5668_JACK_TYPE_MASK;
912 while (val == 0 && count < 50) {
913 usleep_range(10000, 15000);
914 val = snd_soc_component_read32(component,
915 RT5668_CBJ_CTRL_2) & RT5668_JACK_TYPE_MASK;
916 count++;
917 }
918
919 switch (val) {
920 case 0x1:
921 case 0x2:
922 rt5668->jack_type = SND_JACK_HEADSET;
923 rt5668_enable_push_button_irq(component, true);
924 break;
925 default:
926 rt5668->jack_type = SND_JACK_HEADPHONE;
927 }
928
929 } else {
930 rt5668_enable_push_button_irq(component, false);
931 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1,
932 RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_LOW);
933 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
934 snd_soc_dapm_sync(dapm);
935
936 rt5668->jack_type = 0;
937 }
938
939 dev_dbg(component->dev, "jack_type = %d\n", rt5668->jack_type);
940 return rt5668->jack_type;
941 }
942
943 static irqreturn_t rt5668_irq(int irq, void *data)
944 {
945 struct rt5668_priv *rt5668 = data;
946
947 mod_delayed_work(system_power_efficient_wq,
948 &rt5668->jack_detect_work, msecs_to_jiffies(250));
949
950 return IRQ_HANDLED;
951 }
952
953 static void rt5668_jd_check_handler(struct work_struct *work)
954 {
955 struct rt5668_priv *rt5668 = container_of(work, struct rt5668_priv,
956 jd_check_work.work);
957
958 if (snd_soc_component_read32(rt5668->component, RT5668_AJD1_CTRL)
959 & RT5668_JDH_RS_MASK) {
960
961 rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0);
962
963 snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type,
964 SND_JACK_HEADSET |
965 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
966 SND_JACK_BTN_2 | SND_JACK_BTN_3);
967 } else {
968 schedule_delayed_work(&rt5668->jd_check_work, 500);
969 }
970 }
971
972 static int rt5668_set_jack_detect(struct snd_soc_component *component,
973 struct snd_soc_jack *hs_jack, void *data)
974 {
975 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
976
977 switch (rt5668->pdata.jd_src) {
978 case RT5668_JD1:
979 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_2,
980 RT5668_EXT_JD_SRC, RT5668_EXT_JD_SRC_MANUAL);
981 snd_soc_component_write(component, RT5668_CBJ_CTRL_1, 0xd002);
982 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_3,
983 RT5668_CBJ_IN_BUF_EN, RT5668_CBJ_IN_BUF_EN);
984 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
985 RT5668_SAR_POW_MASK, RT5668_SAR_POW_EN);
986 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
987 RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_IRQ);
988 regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL,
989 RT5668_POW_IRQ | RT5668_POW_JDH |
990 RT5668_POW_ANA, RT5668_POW_IRQ |
991 RT5668_POW_JDH | RT5668_POW_ANA);
992 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_2,
993 RT5668_PWR_JDH | RT5668_PWR_JDL,
994 RT5668_PWR_JDH | RT5668_PWR_JDL);
995 regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2,
996 RT5668_JD1_EN_MASK | RT5668_JD1_POL_MASK,
997 RT5668_JD1_EN | RT5668_JD1_POL_NOR);
998 mod_delayed_work(system_power_efficient_wq,
999 &rt5668->jack_detect_work, msecs_to_jiffies(250));
1000 break;
1001
1002 case RT5668_JD_NULL:
1003 regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2,
1004 RT5668_JD1_EN_MASK, RT5668_JD1_DIS);
1005 regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL,
1006 RT5668_POW_JDH | RT5668_POW_JDL, 0);
1007 break;
1008
1009 default:
1010 dev_warn(component->dev, "Wrong JD source\n");
1011 break;
1012 }
1013
1014 rt5668->hs_jack = hs_jack;
1015
1016 return 0;
1017 }
1018
1019 static void rt5668_jack_detect_handler(struct work_struct *work)
1020 {
1021 struct rt5668_priv *rt5668 =
1022 container_of(work, struct rt5668_priv, jack_detect_work.work);
1023 int val, btn_type;
1024
1025 while (!rt5668->component)
1026 usleep_range(10000, 15000);
1027
1028 while (!rt5668->component->card->instantiated)
1029 usleep_range(10000, 15000);
1030
1031 mutex_lock(&rt5668->calibrate_mutex);
1032
1033 val = snd_soc_component_read32(rt5668->component, RT5668_AJD1_CTRL)
1034 & RT5668_JDH_RS_MASK;
1035 if (!val) {
1036
1037 if (rt5668->jack_type == 0) {
1038
1039 rt5668->jack_type =
1040 rt5668_headset_detect(rt5668->component, 1);
1041 } else {
1042
1043 rt5668->jack_type = SND_JACK_HEADSET;
1044 btn_type = rt5668_button_detect(rt5668->component);
1045
1046
1047
1048
1049
1050
1051
1052 switch (btn_type) {
1053 case 0x8000:
1054 case 0x4000:
1055 case 0x2000:
1056 rt5668->jack_type |= SND_JACK_BTN_0;
1057 break;
1058 case 0x1000:
1059 case 0x0800:
1060 case 0x0400:
1061 rt5668->jack_type |= SND_JACK_BTN_1;
1062 break;
1063 case 0x0200:
1064 case 0x0100:
1065 case 0x0080:
1066 rt5668->jack_type |= SND_JACK_BTN_2;
1067 break;
1068 case 0x0040:
1069 case 0x0020:
1070 case 0x0010:
1071 rt5668->jack_type |= SND_JACK_BTN_3;
1072 break;
1073 case 0x0000:
1074 break;
1075 default:
1076 btn_type = 0;
1077 dev_err(rt5668->component->dev,
1078 "Unexpected button code 0x%04x\n",
1079 btn_type);
1080 break;
1081 }
1082 }
1083 } else {
1084
1085 rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0);
1086 }
1087
1088 snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type,
1089 SND_JACK_HEADSET |
1090 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1091 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1092
1093 if (rt5668->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1094 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1095 schedule_delayed_work(&rt5668->jd_check_work, 0);
1096 else
1097 cancel_delayed_work_sync(&rt5668->jd_check_work);
1098
1099 mutex_unlock(&rt5668->calibrate_mutex);
1100 }
1101
1102 static const struct snd_kcontrol_new rt5668_snd_controls[] = {
1103
1104 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5668_HPL_GAIN,
1105 RT5668_HPR_GAIN, RT5668_G_HP_SFT, 15, 1, hp_vol_tlv),
1106
1107
1108 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5668_DAC1_DIG_VOL,
1109 RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 175, 0, dac_vol_tlv),
1110
1111
1112 SOC_SINGLE_TLV("CBJ Boost Volume", RT5668_CBJ_BST_CTRL,
1113 RT5668_BST_CBJ_SFT, 8, 0, bst_tlv),
1114
1115
1116 SOC_DOUBLE("STO1 ADC Capture Switch", RT5668_STO1_ADC_DIG_VOL,
1117 RT5668_L_MUTE_SFT, RT5668_R_MUTE_SFT, 1, 1),
1118 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5668_STO1_ADC_DIG_VOL,
1119 RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 127, 0, adc_vol_tlv),
1120
1121
1122 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5668_STO1_ADC_BOOST,
1123 RT5668_STO1_ADC_L_BST_SFT, RT5668_STO1_ADC_R_BST_SFT,
1124 3, 0, adc_bst_tlv),
1125 };
1126
1127
1128 static int rt5668_div_sel(struct rt5668_priv *rt5668,
1129 int target, const int div[], int size)
1130 {
1131 int i;
1132
1133 if (rt5668->sysclk < target) {
1134 pr_err("sysclk rate %d is too low\n",
1135 rt5668->sysclk);
1136 return 0;
1137 }
1138
1139 for (i = 0; i < size - 1; i++) {
1140 pr_info("div[%d]=%d\n", i, div[i]);
1141 if (target * div[i] == rt5668->sysclk)
1142 return i;
1143 if (target * div[i + 1] > rt5668->sysclk) {
1144 pr_err("can't find div for sysclk %d\n",
1145 rt5668->sysclk);
1146 return i;
1147 }
1148 }
1149
1150 if (target * div[i] < rt5668->sysclk)
1151 pr_err("sysclk rate %d is too high\n",
1152 rt5668->sysclk);
1153
1154 return size - 1;
1155
1156 }
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1169 struct snd_kcontrol *kcontrol, int event)
1170 {
1171 struct snd_soc_component *component =
1172 snd_soc_dapm_to_component(w->dapm);
1173 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
1174 int idx = -EINVAL;
1175 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1176
1177 idx = rt5668_div_sel(rt5668, 1500000, div, ARRAY_SIZE(div));
1178
1179 snd_soc_component_update_bits(component, RT5668_DMIC_CTRL_1,
1180 RT5668_DMIC_CLK_MASK, idx << RT5668_DMIC_CLK_SFT);
1181
1182 return 0;
1183 }
1184
1185 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1186 struct snd_kcontrol *kcontrol, int event)
1187 {
1188 struct snd_soc_component *component =
1189 snd_soc_dapm_to_component(w->dapm);
1190 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
1191 int ref, val, reg, idx = -EINVAL;
1192 static const int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1193
1194 val = snd_soc_component_read32(component, RT5668_GPIO_CTRL_1) &
1195 RT5668_GP4_PIN_MASK;
1196 if (w->shift == RT5668_PWR_ADC_S1F_BIT &&
1197 val == RT5668_GP4_PIN_ADCDAT2)
1198 ref = 256 * rt5668->lrck[RT5668_AIF2];
1199 else
1200 ref = 256 * rt5668->lrck[RT5668_AIF1];
1201
1202 idx = rt5668_div_sel(rt5668, ref, div, ARRAY_SIZE(div));
1203
1204 if (w->shift == RT5668_PWR_ADC_S1F_BIT)
1205 reg = RT5668_PLL_TRACK_3;
1206 else
1207 reg = RT5668_PLL_TRACK_2;
1208
1209 snd_soc_component_update_bits(component, reg,
1210 RT5668_FILTER_CLK_SEL_MASK, idx << RT5668_FILTER_CLK_SEL_SFT);
1211
1212 return 0;
1213 }
1214
1215 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1216 struct snd_soc_dapm_widget *sink)
1217 {
1218 unsigned int val;
1219 struct snd_soc_component *component =
1220 snd_soc_dapm_to_component(w->dapm);
1221
1222 val = snd_soc_component_read32(component, RT5668_GLB_CLK);
1223 val &= RT5668_SCLK_SRC_MASK;
1224 if (val == RT5668_SCLK_SRC_PLL1)
1225 return 1;
1226 else
1227 return 0;
1228 }
1229
1230 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1231 struct snd_soc_dapm_widget *sink)
1232 {
1233 unsigned int reg, shift, val;
1234 struct snd_soc_component *component =
1235 snd_soc_dapm_to_component(w->dapm);
1236
1237 switch (w->shift) {
1238 case RT5668_ADC_STO1_ASRC_SFT:
1239 reg = RT5668_PLL_TRACK_3;
1240 shift = RT5668_FILTER_CLK_SEL_SFT;
1241 break;
1242 case RT5668_DAC_STO1_ASRC_SFT:
1243 reg = RT5668_PLL_TRACK_2;
1244 shift = RT5668_FILTER_CLK_SEL_SFT;
1245 break;
1246 default:
1247 return 0;
1248 }
1249
1250 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1251 switch (val) {
1252 case RT5668_CLK_SEL_I2S1_ASRC:
1253 case RT5668_CLK_SEL_I2S2_ASRC:
1254 return 1;
1255 default:
1256 return 0;
1257 }
1258
1259 }
1260
1261
1262 static const struct snd_kcontrol_new rt5668_sto1_adc_l_mix[] = {
1263 SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER,
1264 RT5668_M_STO1_ADC_L1_SFT, 1, 1),
1265 SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER,
1266 RT5668_M_STO1_ADC_L2_SFT, 1, 1),
1267 };
1268
1269 static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = {
1270 SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER,
1271 RT5668_M_STO1_ADC_R1_SFT, 1, 1),
1272 SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER,
1273 RT5668_M_STO1_ADC_R2_SFT, 1, 1),
1274 };
1275
1276 static const struct snd_kcontrol_new rt5668_dac_l_mix[] = {
1277 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER,
1278 RT5668_M_ADCMIX_L_SFT, 1, 1),
1279 SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER,
1280 RT5668_M_DAC1_L_SFT, 1, 1),
1281 };
1282
1283 static const struct snd_kcontrol_new rt5668_dac_r_mix[] = {
1284 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER,
1285 RT5668_M_ADCMIX_R_SFT, 1, 1),
1286 SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER,
1287 RT5668_M_DAC1_R_SFT, 1, 1),
1288 };
1289
1290 static const struct snd_kcontrol_new rt5668_sto1_dac_l_mix[] = {
1291 SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER,
1292 RT5668_M_DAC_L1_STO_L_SFT, 1, 1),
1293 SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER,
1294 RT5668_M_DAC_R1_STO_L_SFT, 1, 1),
1295 };
1296
1297 static const struct snd_kcontrol_new rt5668_sto1_dac_r_mix[] = {
1298 SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER,
1299 RT5668_M_DAC_L1_STO_R_SFT, 1, 1),
1300 SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER,
1301 RT5668_M_DAC_R1_STO_R_SFT, 1, 1),
1302 };
1303
1304
1305 static const struct snd_kcontrol_new rt5668_rec1_l_mix[] = {
1306 SOC_DAPM_SINGLE("CBJ Switch", RT5668_REC_MIXER,
1307 RT5668_M_CBJ_RM1_L_SFT, 1, 1),
1308 };
1309
1310
1311
1312 static const char * const rt5668_sto1_adc1_src[] = {
1313 "DAC MIX", "ADC"
1314 };
1315
1316 static SOC_ENUM_SINGLE_DECL(
1317 rt5668_sto1_adc1l_enum, RT5668_STO1_ADC_MIXER,
1318 RT5668_STO1_ADC1L_SRC_SFT, rt5668_sto1_adc1_src);
1319
1320 static const struct snd_kcontrol_new rt5668_sto1_adc1l_mux =
1321 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1l_enum);
1322
1323 static SOC_ENUM_SINGLE_DECL(
1324 rt5668_sto1_adc1r_enum, RT5668_STO1_ADC_MIXER,
1325 RT5668_STO1_ADC1R_SRC_SFT, rt5668_sto1_adc1_src);
1326
1327 static const struct snd_kcontrol_new rt5668_sto1_adc1r_mux =
1328 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1r_enum);
1329
1330
1331
1332 static const char * const rt5668_sto1_adc_src[] = {
1333 "ADC1 L", "ADC1 R"
1334 };
1335
1336 static SOC_ENUM_SINGLE_DECL(
1337 rt5668_sto1_adcl_enum, RT5668_STO1_ADC_MIXER,
1338 RT5668_STO1_ADCL_SRC_SFT, rt5668_sto1_adc_src);
1339
1340 static const struct snd_kcontrol_new rt5668_sto1_adcl_mux =
1341 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5668_sto1_adcl_enum);
1342
1343 static SOC_ENUM_SINGLE_DECL(
1344 rt5668_sto1_adcr_enum, RT5668_STO1_ADC_MIXER,
1345 RT5668_STO1_ADCR_SRC_SFT, rt5668_sto1_adc_src);
1346
1347 static const struct snd_kcontrol_new rt5668_sto1_adcr_mux =
1348 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5668_sto1_adcr_enum);
1349
1350
1351
1352 static const char * const rt5668_sto1_adc2_src[] = {
1353 "DAC MIX", "DMIC"
1354 };
1355
1356 static SOC_ENUM_SINGLE_DECL(
1357 rt5668_sto1_adc2l_enum, RT5668_STO1_ADC_MIXER,
1358 RT5668_STO1_ADC2L_SRC_SFT, rt5668_sto1_adc2_src);
1359
1360 static const struct snd_kcontrol_new rt5668_sto1_adc2l_mux =
1361 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5668_sto1_adc2l_enum);
1362
1363 static SOC_ENUM_SINGLE_DECL(
1364 rt5668_sto1_adc2r_enum, RT5668_STO1_ADC_MIXER,
1365 RT5668_STO1_ADC2R_SRC_SFT, rt5668_sto1_adc2_src);
1366
1367 static const struct snd_kcontrol_new rt5668_sto1_adc2r_mux =
1368 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5668_sto1_adc2r_enum);
1369
1370
1371 static const unsigned int rt5668_if1_adc_slot_values[] = {
1372 0,
1373 2,
1374 4,
1375 6,
1376 };
1377
1378 static const char * const rt5668_if1_adc_slot_src[] = {
1379 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1380 };
1381
1382 static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_if1_adc_slot_enum,
1383 RT5668_TDM_CTRL, RT5668_TDM_ADC_LCA_SFT, RT5668_TDM_ADC_LCA_MASK,
1384 rt5668_if1_adc_slot_src, rt5668_if1_adc_slot_values);
1385
1386 static const struct snd_kcontrol_new rt5668_if1_adc_slot_mux =
1387 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5668_if1_adc_slot_enum);
1388
1389
1390
1391 static const char * const rt5668_alg_dac1_src[] = {
1392 "Stereo1 DAC Mixer", "DAC1"
1393 };
1394
1395 static SOC_ENUM_SINGLE_DECL(
1396 rt5668_alg_dac_l1_enum, RT5668_A_DAC1_MUX,
1397 RT5668_A_DACL1_SFT, rt5668_alg_dac1_src);
1398
1399 static const struct snd_kcontrol_new rt5668_alg_dac_l1_mux =
1400 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5668_alg_dac_l1_enum);
1401
1402 static SOC_ENUM_SINGLE_DECL(
1403 rt5668_alg_dac_r1_enum, RT5668_A_DAC1_MUX,
1404 RT5668_A_DACR1_SFT, rt5668_alg_dac1_src);
1405
1406 static const struct snd_kcontrol_new rt5668_alg_dac_r1_mux =
1407 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5668_alg_dac_r1_enum);
1408
1409
1410 static const struct snd_kcontrol_new hpol_switch =
1411 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1,
1412 RT5668_L_MUTE_SFT, 1, 1);
1413 static const struct snd_kcontrol_new hpor_switch =
1414 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1,
1415 RT5668_R_MUTE_SFT, 1, 1);
1416
1417 static int rt5668_hp_event(struct snd_soc_dapm_widget *w,
1418 struct snd_kcontrol *kcontrol, int event)
1419 {
1420 struct snd_soc_component *component =
1421 snd_soc_dapm_to_component(w->dapm);
1422
1423 switch (event) {
1424 case SND_SOC_DAPM_PRE_PMU:
1425 snd_soc_component_write(component,
1426 RT5668_HP_LOGIC_CTRL_2, 0x0012);
1427 snd_soc_component_write(component,
1428 RT5668_HP_CTRL_2, 0x6000);
1429 snd_soc_component_update_bits(component, RT5668_STO_NG2_CTRL_1,
1430 RT5668_NG2_EN_MASK, RT5668_NG2_EN);
1431 snd_soc_component_update_bits(component,
1432 RT5668_DEPOP_1, 0x60, 0x60);
1433 break;
1434
1435 case SND_SOC_DAPM_POST_PMD:
1436 snd_soc_component_update_bits(component,
1437 RT5668_DEPOP_1, 0x60, 0x0);
1438 snd_soc_component_write(component,
1439 RT5668_HP_CTRL_2, 0x0000);
1440 break;
1441
1442 default:
1443 return 0;
1444 }
1445
1446 return 0;
1447
1448 }
1449
1450 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1451 struct snd_kcontrol *kcontrol, int event)
1452 {
1453 switch (event) {
1454 case SND_SOC_DAPM_POST_PMU:
1455
1456 msleep(150);
1457 break;
1458
1459 default:
1460 return 0;
1461 }
1462
1463 return 0;
1464 }
1465
1466 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
1467 struct snd_kcontrol *kcontrol, int event)
1468 {
1469 struct snd_soc_component *component =
1470 snd_soc_dapm_to_component(w->dapm);
1471
1472 switch (event) {
1473 case SND_SOC_DAPM_PRE_PMU:
1474 switch (w->shift) {
1475 case RT5668_PWR_VREF1_BIT:
1476 snd_soc_component_update_bits(component,
1477 RT5668_PWR_ANLG_1, RT5668_PWR_FV1, 0);
1478 break;
1479
1480 case RT5668_PWR_VREF2_BIT:
1481 snd_soc_component_update_bits(component,
1482 RT5668_PWR_ANLG_1, RT5668_PWR_FV2, 0);
1483 break;
1484
1485 default:
1486 break;
1487 }
1488 break;
1489
1490 case SND_SOC_DAPM_POST_PMU:
1491 usleep_range(15000, 20000);
1492 switch (w->shift) {
1493 case RT5668_PWR_VREF1_BIT:
1494 snd_soc_component_update_bits(component,
1495 RT5668_PWR_ANLG_1, RT5668_PWR_FV1,
1496 RT5668_PWR_FV1);
1497 break;
1498
1499 case RT5668_PWR_VREF2_BIT:
1500 snd_soc_component_update_bits(component,
1501 RT5668_PWR_ANLG_1, RT5668_PWR_FV2,
1502 RT5668_PWR_FV2);
1503 break;
1504
1505 default:
1506 break;
1507 }
1508 break;
1509
1510 default:
1511 return 0;
1512 }
1513
1514 return 0;
1515 }
1516
1517 static const unsigned int rt5668_adcdat_pin_values[] = {
1518 1,
1519 3,
1520 };
1521
1522 static const char * const rt5668_adcdat_pin_select[] = {
1523 "ADCDAT1",
1524 "ADCDAT2",
1525 };
1526
1527 static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_adcdat_pin_enum,
1528 RT5668_GPIO_CTRL_1, RT5668_GP4_PIN_SFT, RT5668_GP4_PIN_MASK,
1529 rt5668_adcdat_pin_select, rt5668_adcdat_pin_values);
1530
1531 static const struct snd_kcontrol_new rt5668_adcdat_pin_ctrl =
1532 SOC_DAPM_ENUM("ADCDAT", rt5668_adcdat_pin_enum);
1533
1534 static const struct snd_soc_dapm_widget rt5668_dapm_widgets[] = {
1535 SND_SOC_DAPM_SUPPLY("LDO2", RT5668_PWR_ANLG_3, RT5668_PWR_LDO2_BIT,
1536 0, NULL, 0),
1537 SND_SOC_DAPM_SUPPLY("PLL1", RT5668_PWR_ANLG_3, RT5668_PWR_PLL_BIT,
1538 0, NULL, 0),
1539 SND_SOC_DAPM_SUPPLY("PLL2B", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2B_BIT,
1540 0, NULL, 0),
1541 SND_SOC_DAPM_SUPPLY("PLL2F", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2F_BIT,
1542 0, NULL, 0),
1543 SND_SOC_DAPM_SUPPLY("Vref1", RT5668_PWR_ANLG_1, RT5668_PWR_VREF1_BIT, 0,
1544 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1545 SND_SOC_DAPM_SUPPLY("Vref2", RT5668_PWR_ANLG_1, RT5668_PWR_VREF2_BIT, 0,
1546 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1547
1548
1549 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5668_PLL_TRACK_1,
1550 RT5668_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1551 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5668_PLL_TRACK_1,
1552 RT5668_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1553 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5668_PLL_TRACK_1,
1554 RT5668_AD_ASRC_SFT, 0, NULL, 0),
1555 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5668_PLL_TRACK_1,
1556 RT5668_DA_ASRC_SFT, 0, NULL, 0),
1557 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5668_PLL_TRACK_1,
1558 RT5668_DMIC_ASRC_SFT, 0, NULL, 0),
1559
1560
1561 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5668_PWR_ANLG_2, RT5668_PWR_MB1_BIT,
1562 0, NULL, 0),
1563 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5668_PWR_ANLG_2, RT5668_PWR_MB2_BIT,
1564 0, NULL, 0),
1565
1566
1567 SND_SOC_DAPM_INPUT("DMIC L1"),
1568 SND_SOC_DAPM_INPUT("DMIC R1"),
1569
1570 SND_SOC_DAPM_INPUT("IN1P"),
1571
1572 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1573 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1574 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5668_DMIC_CTRL_1,
1575 RT5668_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1576
1577
1578 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1579 0, 0, NULL, 0),
1580
1581 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5668_PWR_ANLG_3,
1582 RT5668_PWR_CBJ_BIT, 0, NULL, 0),
1583
1584
1585 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_rec1_l_mix,
1586 ARRAY_SIZE(rt5668_rec1_l_mix)),
1587 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5668_PWR_ANLG_2,
1588 RT5668_PWR_RM1_L_BIT, 0, NULL, 0),
1589
1590
1591 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1592 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1593
1594 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5668_PWR_DIG_1,
1595 RT5668_PWR_ADC_L1_BIT, 0, NULL, 0),
1596 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5668_PWR_DIG_1,
1597 RT5668_PWR_ADC_R1_BIT, 0, NULL, 0),
1598 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5668_CHOP_ADC,
1599 RT5668_CKGEN_ADC1_SFT, 0, NULL, 0),
1600
1601
1602 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1603 &rt5668_sto1_adc1l_mux),
1604 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1605 &rt5668_sto1_adc1r_mux),
1606 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1607 &rt5668_sto1_adc2l_mux),
1608 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1609 &rt5668_sto1_adc2r_mux),
1610 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1611 &rt5668_sto1_adcl_mux),
1612 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1613 &rt5668_sto1_adcr_mux),
1614 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1615 &rt5668_if1_adc_slot_mux),
1616
1617
1618 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5668_PWR_DIG_2,
1619 RT5668_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1620 SND_SOC_DAPM_PRE_PMU),
1621 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5668_STO1_ADC_DIG_VOL,
1622 RT5668_L_MUTE_SFT, 1, rt5668_sto1_adc_l_mix,
1623 ARRAY_SIZE(rt5668_sto1_adc_l_mix)),
1624 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5668_STO1_ADC_DIG_VOL,
1625 RT5668_R_MUTE_SFT, 1, rt5668_sto1_adc_r_mix,
1626 ARRAY_SIZE(rt5668_sto1_adc_r_mix)),
1627
1628
1629 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1630
1631
1632 SND_SOC_DAPM_SUPPLY("I2S1", RT5668_PWR_DIG_1, RT5668_PWR_I2S1_BIT,
1633 0, NULL, 0),
1634 SND_SOC_DAPM_SUPPLY("I2S2", RT5668_PWR_DIG_1, RT5668_PWR_I2S2_BIT,
1635 0, NULL, 0),
1636 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1637 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1638 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1639
1640
1641 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1642 &rt5668_if1_01_adc_swap_mux),
1643 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1644 &rt5668_if1_23_adc_swap_mux),
1645 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1646 &rt5668_if1_45_adc_swap_mux),
1647 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1648 &rt5668_if1_67_adc_swap_mux),
1649 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1650 &rt5668_if2_adc_swap_mux),
1651
1652 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1653 &rt5668_adcdat_pin_ctrl),
1654
1655
1656 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1657 RT5668_I2S1_SDP, RT5668_SEL_ADCDAT_SFT, 1),
1658 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1659 RT5668_I2S2_SDP, RT5668_I2S2_PIN_CFG_SFT, 1),
1660 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1661
1662
1663
1664 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1665 rt5668_dac_l_mix, ARRAY_SIZE(rt5668_dac_l_mix)),
1666 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1667 rt5668_dac_r_mix, ARRAY_SIZE(rt5668_dac_r_mix)),
1668
1669
1670 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1671 &rt5668_alg_dac_l1_mux),
1672 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1673 &rt5668_alg_dac_r1_mux),
1674
1675
1676 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5668_PWR_DIG_2,
1677 RT5668_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1678 SND_SOC_DAPM_PRE_PMU),
1679 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1680 rt5668_sto1_dac_l_mix, ARRAY_SIZE(rt5668_sto1_dac_l_mix)),
1681 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1682 rt5668_sto1_dac_r_mix, ARRAY_SIZE(rt5668_sto1_dac_r_mix)),
1683
1684
1685 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5668_PWR_DIG_1,
1686 RT5668_PWR_DAC_L1_BIT, 0),
1687 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5668_PWR_DIG_1,
1688 RT5668_PWR_DAC_R1_BIT, 0),
1689 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5668_CHOP_DAC,
1690 RT5668_CKGEN_DAC1_SFT, 0, NULL, 0),
1691
1692
1693 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5668_hp_event,
1694 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1695
1696 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5668_PWR_ANLG_1,
1697 RT5668_PWR_HA_L_BIT, 0, NULL, 0),
1698 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5668_PWR_ANLG_1,
1699 RT5668_PWR_HA_R_BIT, 0, NULL, 0),
1700 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5668_DEPOP_1,
1701 RT5668_PUMP_EN_SFT, 0, NULL, 0),
1702 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5668_DEPOP_1,
1703 RT5668_CAPLESS_EN_SFT, 0, NULL, 0),
1704
1705 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1706 &hpol_switch),
1707 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1708 &hpor_switch),
1709
1710
1711 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5668_CLK_DET,
1712 RT5668_SYS_CLK_DET_SFT, 0, NULL, 0),
1713 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5668_CLK_DET,
1714 RT5668_PLL1_CLK_DET_SFT, 0, NULL, 0),
1715 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5668_CLK_DET,
1716 RT5668_PLL2_CLK_DET_SFT, 0, NULL, 0),
1717 SND_SOC_DAPM_SUPPLY("CLKDET", RT5668_CLK_DET,
1718 RT5668_POW_CLK_DET_SFT, 0, NULL, 0),
1719
1720
1721 SND_SOC_DAPM_OUTPUT("HPOL"),
1722 SND_SOC_DAPM_OUTPUT("HPOR"),
1723
1724 };
1725
1726 static const struct snd_soc_dapm_route rt5668_dapm_routes[] = {
1727
1728 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1729 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1730
1731
1732 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1733 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1734 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1735 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1736
1737
1738 {"MICBIAS1", NULL, "Vref1"},
1739 {"MICBIAS1", NULL, "Vref2"},
1740 {"MICBIAS2", NULL, "Vref1"},
1741 {"MICBIAS2", NULL, "Vref2"},
1742
1743 {"CLKDET SYS", NULL, "CLKDET"},
1744
1745 {"IN1P", NULL, "LDO2"},
1746
1747 {"BST1 CBJ", NULL, "IN1P"},
1748 {"BST1 CBJ", NULL, "CBJ Power"},
1749 {"CBJ Power", NULL, "Vref2"},
1750
1751 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1752 {"RECMIX1L", NULL, "RECMIX1L Power"},
1753
1754 {"ADC1 L", NULL, "RECMIX1L"},
1755 {"ADC1 L", NULL, "ADC1 L Power"},
1756 {"ADC1 L", NULL, "ADC1 clock"},
1757
1758 {"DMIC L1", NULL, "DMIC CLK"},
1759 {"DMIC L1", NULL, "DMIC1 Power"},
1760 {"DMIC R1", NULL, "DMIC CLK"},
1761 {"DMIC R1", NULL, "DMIC1 Power"},
1762 {"DMIC CLK", NULL, "DMIC ASRC"},
1763
1764 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1765 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1766 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1767 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1768
1769 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1770 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1771 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1772 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1773
1774 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1775 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1776 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1777 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1778
1779 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1780 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1781 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1782
1783 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1784 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1785 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1786
1787 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1788 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1789
1790 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1791 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1792 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1793 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1794 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1795 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1796 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1797 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1798 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1799 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1800 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1801 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1802 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1803 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1804 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1805 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1806
1807 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1808 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1809 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1810 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1811 {"IF1_ADC Mux", NULL, "I2S1"},
1812 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1813 {"AIF1TX", NULL, "ADCDAT Mux"},
1814 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1815 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1816 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1817 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1818 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1819 {"AIF2TX", NULL, "ADCDAT Mux"},
1820
1821 {"IF1 DAC1 L", NULL, "AIF1RX"},
1822 {"IF1 DAC1 L", NULL, "I2S1"},
1823 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1824 {"IF1 DAC1 R", NULL, "AIF1RX"},
1825 {"IF1 DAC1 R", NULL, "I2S1"},
1826 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1827
1828 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1829 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1830 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1831 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1832
1833 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1834 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1835
1836 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1837 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1838
1839 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1840 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1841 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1842 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1843
1844 {"DAC L1", NULL, "DAC L1 Source"},
1845 {"DAC R1", NULL, "DAC R1 Source"},
1846
1847 {"DAC L1", NULL, "DAC 1 Clock"},
1848 {"DAC R1", NULL, "DAC 1 Clock"},
1849
1850 {"HP Amp", NULL, "DAC L1"},
1851 {"HP Amp", NULL, "DAC R1"},
1852 {"HP Amp", NULL, "HP Amp L"},
1853 {"HP Amp", NULL, "HP Amp R"},
1854 {"HP Amp", NULL, "Capless"},
1855 {"HP Amp", NULL, "Charge Pump"},
1856 {"HP Amp", NULL, "CLKDET SYS"},
1857 {"HP Amp", NULL, "CBJ Power"},
1858 {"HP Amp", NULL, "Vref2"},
1859 {"HPOL Playback", "Switch", "HP Amp"},
1860 {"HPOR Playback", "Switch", "HP Amp"},
1861 {"HPOL", NULL, "HPOL Playback"},
1862 {"HPOR", NULL, "HPOR Playback"},
1863 };
1864
1865 static int rt5668_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1866 unsigned int rx_mask, int slots, int slot_width)
1867 {
1868 struct snd_soc_component *component = dai->component;
1869 unsigned int val = 0;
1870
1871 switch (slots) {
1872 case 4:
1873 val |= RT5668_TDM_TX_CH_4;
1874 val |= RT5668_TDM_RX_CH_4;
1875 break;
1876 case 6:
1877 val |= RT5668_TDM_TX_CH_6;
1878 val |= RT5668_TDM_RX_CH_6;
1879 break;
1880 case 8:
1881 val |= RT5668_TDM_TX_CH_8;
1882 val |= RT5668_TDM_RX_CH_8;
1883 break;
1884 case 2:
1885 break;
1886 default:
1887 return -EINVAL;
1888 }
1889
1890 snd_soc_component_update_bits(component, RT5668_TDM_CTRL,
1891 RT5668_TDM_TX_CH_MASK | RT5668_TDM_RX_CH_MASK, val);
1892
1893 switch (slot_width) {
1894 case 16:
1895 val = RT5668_TDM_CL_16;
1896 break;
1897 case 20:
1898 val = RT5668_TDM_CL_20;
1899 break;
1900 case 24:
1901 val = RT5668_TDM_CL_24;
1902 break;
1903 case 32:
1904 val = RT5668_TDM_CL_32;
1905 break;
1906 default:
1907 return -EINVAL;
1908 }
1909
1910 snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL,
1911 RT5668_TDM_CL_MASK, val);
1912
1913 return 0;
1914 }
1915
1916
1917 static int rt5668_hw_params(struct snd_pcm_substream *substream,
1918 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1919 {
1920 struct snd_soc_component *component = dai->component;
1921 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
1922 unsigned int len_1 = 0, len_2 = 0;
1923 int pre_div, frame_size;
1924
1925 rt5668->lrck[dai->id] = params_rate(params);
1926 pre_div = rl6231_get_clk_info(rt5668->sysclk, rt5668->lrck[dai->id]);
1927
1928 frame_size = snd_soc_params_to_frame_size(params);
1929 if (frame_size < 0) {
1930 dev_err(component->dev, "Unsupported frame size: %d\n",
1931 frame_size);
1932 return -EINVAL;
1933 }
1934
1935 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
1936 rt5668->lrck[dai->id], pre_div, dai->id);
1937
1938 switch (params_width(params)) {
1939 case 16:
1940 break;
1941 case 20:
1942 len_1 |= RT5668_I2S1_DL_20;
1943 len_2 |= RT5668_I2S2_DL_20;
1944 break;
1945 case 24:
1946 len_1 |= RT5668_I2S1_DL_24;
1947 len_2 |= RT5668_I2S2_DL_24;
1948 break;
1949 case 32:
1950 len_1 |= RT5668_I2S1_DL_32;
1951 len_2 |= RT5668_I2S2_DL_24;
1952 break;
1953 case 8:
1954 len_1 |= RT5668_I2S2_DL_8;
1955 len_2 |= RT5668_I2S2_DL_8;
1956 break;
1957 default:
1958 return -EINVAL;
1959 }
1960
1961 switch (dai->id) {
1962 case RT5668_AIF1:
1963 snd_soc_component_update_bits(component, RT5668_I2S1_SDP,
1964 RT5668_I2S1_DL_MASK, len_1);
1965 if (rt5668->master[RT5668_AIF1]) {
1966 snd_soc_component_update_bits(component,
1967 RT5668_ADDA_CLK_1, RT5668_I2S_M_DIV_MASK,
1968 pre_div << RT5668_I2S_M_DIV_SFT);
1969 }
1970 if (params_channels(params) == 1)
1971 snd_soc_component_update_bits(component,
1972 RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK,
1973 RT5668_I2S1_MONO_EN);
1974 else
1975 snd_soc_component_update_bits(component,
1976 RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK,
1977 RT5668_I2S1_MONO_DIS);
1978 break;
1979 case RT5668_AIF2:
1980 snd_soc_component_update_bits(component, RT5668_I2S2_SDP,
1981 RT5668_I2S2_DL_MASK, len_2);
1982 if (rt5668->master[RT5668_AIF2]) {
1983 snd_soc_component_update_bits(component,
1984 RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_M_PD_MASK,
1985 pre_div << RT5668_I2S2_M_PD_SFT);
1986 }
1987 if (params_channels(params) == 1)
1988 snd_soc_component_update_bits(component,
1989 RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK,
1990 RT5668_I2S2_MONO_EN);
1991 else
1992 snd_soc_component_update_bits(component,
1993 RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK,
1994 RT5668_I2S2_MONO_DIS);
1995 break;
1996 default:
1997 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1998 return -EINVAL;
1999 }
2000
2001 return 0;
2002 }
2003
2004 static int rt5668_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2005 {
2006 struct snd_soc_component *component = dai->component;
2007 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2008 unsigned int reg_val = 0, tdm_ctrl = 0;
2009
2010 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2011 case SND_SOC_DAIFMT_CBM_CFM:
2012 rt5668->master[dai->id] = 1;
2013 break;
2014 case SND_SOC_DAIFMT_CBS_CFS:
2015 rt5668->master[dai->id] = 0;
2016 break;
2017 default:
2018 return -EINVAL;
2019 }
2020
2021 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2022 case SND_SOC_DAIFMT_NB_NF:
2023 break;
2024 case SND_SOC_DAIFMT_IB_NF:
2025 reg_val |= RT5668_I2S_BP_INV;
2026 tdm_ctrl |= RT5668_TDM_S_BP_INV;
2027 break;
2028 case SND_SOC_DAIFMT_NB_IF:
2029 if (dai->id == RT5668_AIF1)
2030 tdm_ctrl |= RT5668_TDM_S_LP_INV | RT5668_TDM_M_BP_INV;
2031 else
2032 return -EINVAL;
2033 break;
2034 case SND_SOC_DAIFMT_IB_IF:
2035 if (dai->id == RT5668_AIF1)
2036 tdm_ctrl |= RT5668_TDM_S_BP_INV | RT5668_TDM_S_LP_INV |
2037 RT5668_TDM_M_BP_INV | RT5668_TDM_M_LP_INV;
2038 else
2039 return -EINVAL;
2040 break;
2041 default:
2042 return -EINVAL;
2043 }
2044
2045 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2046 case SND_SOC_DAIFMT_I2S:
2047 break;
2048 case SND_SOC_DAIFMT_LEFT_J:
2049 reg_val |= RT5668_I2S_DF_LEFT;
2050 tdm_ctrl |= RT5668_TDM_DF_LEFT;
2051 break;
2052 case SND_SOC_DAIFMT_DSP_A:
2053 reg_val |= RT5668_I2S_DF_PCM_A;
2054 tdm_ctrl |= RT5668_TDM_DF_PCM_A;
2055 break;
2056 case SND_SOC_DAIFMT_DSP_B:
2057 reg_val |= RT5668_I2S_DF_PCM_B;
2058 tdm_ctrl |= RT5668_TDM_DF_PCM_B;
2059 break;
2060 default:
2061 return -EINVAL;
2062 }
2063
2064 switch (dai->id) {
2065 case RT5668_AIF1:
2066 snd_soc_component_update_bits(component, RT5668_I2S1_SDP,
2067 RT5668_I2S_DF_MASK, reg_val);
2068 snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL,
2069 RT5668_TDM_MS_MASK | RT5668_TDM_S_BP_MASK |
2070 RT5668_TDM_DF_MASK | RT5668_TDM_M_BP_MASK |
2071 RT5668_TDM_M_LP_MASK | RT5668_TDM_S_LP_MASK,
2072 tdm_ctrl | rt5668->master[dai->id]);
2073 break;
2074 case RT5668_AIF2:
2075 if (rt5668->master[dai->id] == 0)
2076 reg_val |= RT5668_I2S2_MS_S;
2077 snd_soc_component_update_bits(component, RT5668_I2S2_SDP,
2078 RT5668_I2S2_MS_MASK | RT5668_I2S_BP_MASK |
2079 RT5668_I2S_DF_MASK, reg_val);
2080 break;
2081 default:
2082 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2083 return -EINVAL;
2084 }
2085 return 0;
2086 }
2087
2088 static int rt5668_set_component_sysclk(struct snd_soc_component *component,
2089 int clk_id, int source, unsigned int freq, int dir)
2090 {
2091 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2092 unsigned int reg_val = 0, src = 0;
2093
2094 if (freq == rt5668->sysclk && clk_id == rt5668->sysclk_src)
2095 return 0;
2096
2097 switch (clk_id) {
2098 case RT5668_SCLK_S_MCLK:
2099 reg_val |= RT5668_SCLK_SRC_MCLK;
2100 src = RT5668_CLK_SRC_MCLK;
2101 break;
2102 case RT5668_SCLK_S_PLL1:
2103 reg_val |= RT5668_SCLK_SRC_PLL1;
2104 src = RT5668_CLK_SRC_PLL1;
2105 break;
2106 case RT5668_SCLK_S_PLL2:
2107 reg_val |= RT5668_SCLK_SRC_PLL2;
2108 src = RT5668_CLK_SRC_PLL2;
2109 break;
2110 case RT5668_SCLK_S_RCCLK:
2111 reg_val |= RT5668_SCLK_SRC_RCCLK;
2112 src = RT5668_CLK_SRC_RCCLK;
2113 break;
2114 default:
2115 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2116 return -EINVAL;
2117 }
2118 snd_soc_component_update_bits(component, RT5668_GLB_CLK,
2119 RT5668_SCLK_SRC_MASK, reg_val);
2120
2121 if (rt5668->master[RT5668_AIF2]) {
2122 snd_soc_component_update_bits(component,
2123 RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_SRC_MASK,
2124 src << RT5668_I2S2_SRC_SFT);
2125 }
2126
2127 rt5668->sysclk = freq;
2128 rt5668->sysclk_src = clk_id;
2129
2130 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2131 freq, clk_id);
2132
2133 return 0;
2134 }
2135
2136 static int rt5668_set_component_pll(struct snd_soc_component *component,
2137 int pll_id, int source, unsigned int freq_in,
2138 unsigned int freq_out)
2139 {
2140 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2141 struct rl6231_pll_code pll_code;
2142 int ret;
2143
2144 if (source == rt5668->pll_src && freq_in == rt5668->pll_in &&
2145 freq_out == rt5668->pll_out)
2146 return 0;
2147
2148 if (!freq_in || !freq_out) {
2149 dev_dbg(component->dev, "PLL disabled\n");
2150
2151 rt5668->pll_in = 0;
2152 rt5668->pll_out = 0;
2153 snd_soc_component_update_bits(component, RT5668_GLB_CLK,
2154 RT5668_SCLK_SRC_MASK, RT5668_SCLK_SRC_MCLK);
2155 return 0;
2156 }
2157
2158 switch (source) {
2159 case RT5668_PLL1_S_MCLK:
2160 snd_soc_component_update_bits(component, RT5668_GLB_CLK,
2161 RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_MCLK);
2162 break;
2163 case RT5668_PLL1_S_BCLK1:
2164 snd_soc_component_update_bits(component, RT5668_GLB_CLK,
2165 RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_BCLK1);
2166 break;
2167 default:
2168 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2169 return -EINVAL;
2170 }
2171
2172 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2173 if (ret < 0) {
2174 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2175 return ret;
2176 }
2177
2178 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2179 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2180 pll_code.n_code, pll_code.k_code);
2181
2182 snd_soc_component_write(component, RT5668_PLL_CTRL_1,
2183 pll_code.n_code << RT5668_PLL_N_SFT | pll_code.k_code);
2184 snd_soc_component_write(component, RT5668_PLL_CTRL_2,
2185 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SFT |
2186 pll_code.m_bp << RT5668_PLL_M_BP_SFT);
2187
2188 rt5668->pll_in = freq_in;
2189 rt5668->pll_out = freq_out;
2190 rt5668->pll_src = source;
2191
2192 return 0;
2193 }
2194
2195 static int rt5668_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2196 {
2197 struct snd_soc_component *component = dai->component;
2198 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2199
2200 rt5668->bclk[dai->id] = ratio;
2201
2202 switch (ratio) {
2203 case 64:
2204 snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2,
2205 RT5668_I2S2_BCLK_MS2_MASK,
2206 RT5668_I2S2_BCLK_MS2_64);
2207 break;
2208 case 32:
2209 snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2,
2210 RT5668_I2S2_BCLK_MS2_MASK,
2211 RT5668_I2S2_BCLK_MS2_32);
2212 break;
2213 default:
2214 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
2215 return -EINVAL;
2216 }
2217
2218 return 0;
2219 }
2220
2221 static int rt5668_set_bias_level(struct snd_soc_component *component,
2222 enum snd_soc_bias_level level)
2223 {
2224 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2225
2226 switch (level) {
2227 case SND_SOC_BIAS_PREPARE:
2228 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
2229 RT5668_PWR_MB | RT5668_PWR_BG,
2230 RT5668_PWR_MB | RT5668_PWR_BG);
2231 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
2232 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO,
2233 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO);
2234 break;
2235
2236 case SND_SOC_BIAS_STANDBY:
2237 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
2238 RT5668_PWR_MB, RT5668_PWR_MB);
2239 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
2240 RT5668_DIG_GATE_CTRL, RT5668_DIG_GATE_CTRL);
2241 break;
2242 case SND_SOC_BIAS_OFF:
2243 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
2244 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO, 0);
2245 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
2246 RT5668_PWR_MB | RT5668_PWR_BG, 0);
2247 break;
2248
2249 default:
2250 break;
2251 }
2252
2253 return 0;
2254 }
2255
2256 static int rt5668_probe(struct snd_soc_component *component)
2257 {
2258 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2259
2260 rt5668->component = component;
2261
2262 return 0;
2263 }
2264
2265 static void rt5668_remove(struct snd_soc_component *component)
2266 {
2267 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2268
2269 rt5668_reset(rt5668->regmap);
2270 }
2271
2272 #ifdef CONFIG_PM
2273 static int rt5668_suspend(struct snd_soc_component *component)
2274 {
2275 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2276
2277 regcache_cache_only(rt5668->regmap, true);
2278 regcache_mark_dirty(rt5668->regmap);
2279 return 0;
2280 }
2281
2282 static int rt5668_resume(struct snd_soc_component *component)
2283 {
2284 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2285
2286 regcache_cache_only(rt5668->regmap, false);
2287 regcache_sync(rt5668->regmap);
2288
2289 return 0;
2290 }
2291 #else
2292 #define rt5668_suspend NULL
2293 #define rt5668_resume NULL
2294 #endif
2295
2296 #define RT5668_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2297 #define RT5668_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2298 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2299
2300 static const struct snd_soc_dai_ops rt5668_aif1_dai_ops = {
2301 .hw_params = rt5668_hw_params,
2302 .set_fmt = rt5668_set_dai_fmt,
2303 .set_tdm_slot = rt5668_set_tdm_slot,
2304 };
2305
2306 static const struct snd_soc_dai_ops rt5668_aif2_dai_ops = {
2307 .hw_params = rt5668_hw_params,
2308 .set_fmt = rt5668_set_dai_fmt,
2309 .set_bclk_ratio = rt5668_set_bclk_ratio,
2310 };
2311
2312 static struct snd_soc_dai_driver rt5668_dai[] = {
2313 {
2314 .name = "rt5668-aif1",
2315 .id = RT5668_AIF1,
2316 .playback = {
2317 .stream_name = "AIF1 Playback",
2318 .channels_min = 1,
2319 .channels_max = 2,
2320 .rates = RT5668_STEREO_RATES,
2321 .formats = RT5668_FORMATS,
2322 },
2323 .capture = {
2324 .stream_name = "AIF1 Capture",
2325 .channels_min = 1,
2326 .channels_max = 2,
2327 .rates = RT5668_STEREO_RATES,
2328 .formats = RT5668_FORMATS,
2329 },
2330 .ops = &rt5668_aif1_dai_ops,
2331 },
2332 {
2333 .name = "rt5668-aif2",
2334 .id = RT5668_AIF2,
2335 .capture = {
2336 .stream_name = "AIF2 Capture",
2337 .channels_min = 1,
2338 .channels_max = 2,
2339 .rates = RT5668_STEREO_RATES,
2340 .formats = RT5668_FORMATS,
2341 },
2342 .ops = &rt5668_aif2_dai_ops,
2343 },
2344 };
2345
2346 static const struct snd_soc_component_driver soc_component_dev_rt5668 = {
2347 .probe = rt5668_probe,
2348 .remove = rt5668_remove,
2349 .suspend = rt5668_suspend,
2350 .resume = rt5668_resume,
2351 .set_bias_level = rt5668_set_bias_level,
2352 .controls = rt5668_snd_controls,
2353 .num_controls = ARRAY_SIZE(rt5668_snd_controls),
2354 .dapm_widgets = rt5668_dapm_widgets,
2355 .num_dapm_widgets = ARRAY_SIZE(rt5668_dapm_widgets),
2356 .dapm_routes = rt5668_dapm_routes,
2357 .num_dapm_routes = ARRAY_SIZE(rt5668_dapm_routes),
2358 .set_sysclk = rt5668_set_component_sysclk,
2359 .set_pll = rt5668_set_component_pll,
2360 .set_jack = rt5668_set_jack_detect,
2361 .use_pmdown_time = 1,
2362 .endianness = 1,
2363 .non_legacy_dai_naming = 1,
2364 };
2365
2366 static const struct regmap_config rt5668_regmap = {
2367 .reg_bits = 16,
2368 .val_bits = 16,
2369 .max_register = RT5668_I2C_MODE,
2370 .volatile_reg = rt5668_volatile_register,
2371 .readable_reg = rt5668_readable_register,
2372 .cache_type = REGCACHE_RBTREE,
2373 .reg_defaults = rt5668_reg,
2374 .num_reg_defaults = ARRAY_SIZE(rt5668_reg),
2375 .use_single_read = true,
2376 .use_single_write = true,
2377 };
2378
2379 static const struct i2c_device_id rt5668_i2c_id[] = {
2380 {"rt5668b", 0},
2381 {}
2382 };
2383 MODULE_DEVICE_TABLE(i2c, rt5668_i2c_id);
2384
2385 static int rt5668_parse_dt(struct rt5668_priv *rt5668, struct device *dev)
2386 {
2387
2388 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
2389 &rt5668->pdata.dmic1_data_pin);
2390 of_property_read_u32(dev->of_node, "realtek,dmic1-clk-pin",
2391 &rt5668->pdata.dmic1_clk_pin);
2392 of_property_read_u32(dev->of_node, "realtek,jd-src",
2393 &rt5668->pdata.jd_src);
2394
2395 rt5668->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2396 "realtek,ldo1-en-gpios", 0);
2397
2398 return 0;
2399 }
2400
2401 static void rt5668_calibrate(struct rt5668_priv *rt5668)
2402 {
2403 int value, count;
2404
2405 mutex_lock(&rt5668->calibrate_mutex);
2406
2407 rt5668_reset(rt5668->regmap);
2408 regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xa2bf);
2409 usleep_range(15000, 20000);
2410 regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xf2bf);
2411 regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380);
2412 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8001);
2413 regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000);
2414 regmap_write(rt5668->regmap, RT5668_STO1_DAC_MIXER, 0x2080);
2415 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x4040);
2416 regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0069);
2417 regmap_write(rt5668->regmap, RT5668_CHOP_DAC, 0x3000);
2418 regmap_write(rt5668->regmap, RT5668_HP_CTRL_2, 0x6000);
2419 regmap_write(rt5668->regmap, RT5668_HP_CHARGE_PUMP_1, 0x0f26);
2420 regmap_write(rt5668->regmap, RT5668_CALIB_ADC_CTRL, 0x7f05);
2421 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x686c);
2422 regmap_write(rt5668->regmap, RT5668_CAL_REC, 0x0d0d);
2423 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_9, 0x000f);
2424 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8d01);
2425 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_2, 0x0321);
2426 regmap_write(rt5668->regmap, RT5668_HP_LOGIC_CTRL_2, 0x0004);
2427 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0x7c00);
2428 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_3, 0x06a1);
2429 regmap_write(rt5668->regmap, RT5668_A_DAC1_MUX, 0x0311);
2430 regmap_write(rt5668->regmap, RT5668_RESET_HPF_CTRL, 0x0000);
2431 regmap_write(rt5668->regmap, RT5668_ADC_STO1_HP_CTRL_1, 0x3320);
2432
2433 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0xfc00);
2434
2435 for (count = 0; count < 60; count++) {
2436 regmap_read(rt5668->regmap, RT5668_HP_CALIB_STA_1, &value);
2437 if (!(value & 0x8000))
2438 break;
2439
2440 usleep_range(10000, 10005);
2441 }
2442
2443 if (count >= 60)
2444 pr_err("HP Calibration Failure\n");
2445
2446
2447 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0xc0c4);
2448 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x0000);
2449
2450 mutex_unlock(&rt5668->calibrate_mutex);
2451
2452 }
2453
2454 static int rt5668_i2c_probe(struct i2c_client *i2c,
2455 const struct i2c_device_id *id)
2456 {
2457 struct rt5668_platform_data *pdata = dev_get_platdata(&i2c->dev);
2458 struct rt5668_priv *rt5668;
2459 int i, ret;
2460 unsigned int val;
2461
2462 rt5668 = devm_kzalloc(&i2c->dev, sizeof(struct rt5668_priv),
2463 GFP_KERNEL);
2464
2465 if (rt5668 == NULL)
2466 return -ENOMEM;
2467
2468 i2c_set_clientdata(i2c, rt5668);
2469
2470 if (pdata)
2471 rt5668->pdata = *pdata;
2472 else
2473 rt5668_parse_dt(rt5668, &i2c->dev);
2474
2475 rt5668->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap);
2476 if (IS_ERR(rt5668->regmap)) {
2477 ret = PTR_ERR(rt5668->regmap);
2478 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2479 ret);
2480 return ret;
2481 }
2482
2483 for (i = 0; i < ARRAY_SIZE(rt5668->supplies); i++)
2484 rt5668->supplies[i].supply = rt5668_supply_names[i];
2485
2486 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5668->supplies),
2487 rt5668->supplies);
2488 if (ret != 0) {
2489 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2490 return ret;
2491 }
2492
2493 ret = regulator_bulk_enable(ARRAY_SIZE(rt5668->supplies),
2494 rt5668->supplies);
2495 if (ret != 0) {
2496 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2497 return ret;
2498 }
2499
2500 if (gpio_is_valid(rt5668->pdata.ldo1_en)) {
2501 if (devm_gpio_request_one(&i2c->dev, rt5668->pdata.ldo1_en,
2502 GPIOF_OUT_INIT_HIGH, "rt5668"))
2503 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
2504 }
2505
2506
2507 usleep_range(300000, 350000);
2508
2509 regmap_write(rt5668->regmap, RT5668_I2C_MODE, 0x1);
2510 usleep_range(10000, 15000);
2511
2512 regmap_read(rt5668->regmap, RT5668_DEVICE_ID, &val);
2513 if (val != DEVICE_ID) {
2514 pr_err("Device with ID register %x is not rt5668\n", val);
2515 return -ENODEV;
2516 }
2517
2518 rt5668_reset(rt5668->regmap);
2519
2520 rt5668_calibrate(rt5668);
2521
2522 regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0000);
2523
2524
2525 if (rt5668->pdata.dmic1_data_pin != RT5668_DMIC1_NULL) {
2526 switch (rt5668->pdata.dmic1_data_pin) {
2527 case RT5668_DMIC1_DATA_GPIO2:
2528 regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1,
2529 RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO2);
2530 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2531 RT5668_GP2_PIN_MASK, RT5668_GP2_PIN_DMIC_SDA);
2532 break;
2533
2534 case RT5668_DMIC1_DATA_GPIO5:
2535 regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1,
2536 RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO5);
2537 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2538 RT5668_GP5_PIN_MASK, RT5668_GP5_PIN_DMIC_SDA);
2539 break;
2540
2541 default:
2542 dev_dbg(&i2c->dev, "invalid DMIC_DAT pin\n");
2543 break;
2544 }
2545
2546 switch (rt5668->pdata.dmic1_clk_pin) {
2547 case RT5668_DMIC1_CLK_GPIO1:
2548 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2549 RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_DMIC_CLK);
2550 break;
2551
2552 case RT5668_DMIC1_CLK_GPIO3:
2553 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2554 RT5668_GP3_PIN_MASK, RT5668_GP3_PIN_DMIC_CLK);
2555 break;
2556
2557 default:
2558 dev_dbg(&i2c->dev, "invalid DMIC_CLK pin\n");
2559 break;
2560 }
2561 }
2562
2563 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
2564 RT5668_LDO1_DVO_MASK | RT5668_HP_DRIVER_MASK,
2565 RT5668_LDO1_DVO_14 | RT5668_HP_DRIVER_5X);
2566 regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380);
2567 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2568 RT5668_GP4_PIN_MASK | RT5668_GP5_PIN_MASK,
2569 RT5668_GP4_PIN_ADCDAT1 | RT5668_GP5_PIN_DACDAT1);
2570 regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000);
2571
2572 INIT_DELAYED_WORK(&rt5668->jack_detect_work,
2573 rt5668_jack_detect_handler);
2574 INIT_DELAYED_WORK(&rt5668->jd_check_work,
2575 rt5668_jd_check_handler);
2576
2577 mutex_init(&rt5668->calibrate_mutex);
2578
2579 if (i2c->irq) {
2580 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2581 rt5668_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2582 | IRQF_ONESHOT, "rt5668", rt5668);
2583 if (ret)
2584 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2585
2586 }
2587
2588 return devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5668,
2589 rt5668_dai, ARRAY_SIZE(rt5668_dai));
2590 }
2591
2592 static void rt5668_i2c_shutdown(struct i2c_client *client)
2593 {
2594 struct rt5668_priv *rt5668 = i2c_get_clientdata(client);
2595
2596 rt5668_reset(rt5668->regmap);
2597 }
2598
2599 #ifdef CONFIG_OF
2600 static const struct of_device_id rt5668_of_match[] = {
2601 {.compatible = "realtek,rt5668b"},
2602 {},
2603 };
2604 MODULE_DEVICE_TABLE(of, rt5668_of_match);
2605 #endif
2606
2607 #ifdef CONFIG_ACPI
2608 static const struct acpi_device_id rt5668_acpi_match[] = {
2609 {"10EC5668", 0,},
2610 {},
2611 };
2612 MODULE_DEVICE_TABLE(acpi, rt5668_acpi_match);
2613 #endif
2614
2615 static struct i2c_driver rt5668_i2c_driver = {
2616 .driver = {
2617 .name = "rt5668b",
2618 .of_match_table = of_match_ptr(rt5668_of_match),
2619 .acpi_match_table = ACPI_PTR(rt5668_acpi_match),
2620 },
2621 .probe = rt5668_i2c_probe,
2622 .shutdown = rt5668_i2c_shutdown,
2623 .id_table = rt5668_i2c_id,
2624 };
2625 module_i2c_driver(rt5668_i2c_driver);
2626
2627 MODULE_DESCRIPTION("ASoC RT5668B driver");
2628 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2629 MODULE_LICENSE("GPL v2");