root/sound/soc/codecs/ml26124.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   4  */
   5 
   6 #ifndef ML26124_H
   7 #define ML26124_H
   8 
   9 /* Clock Control Register */
  10 #define ML26124_SMPLING_RATE            0x00
  11 #define ML26124_PLLNL                   0x02
  12 #define ML26124_PLLNH                   0x04
  13 #define ML26124_PLLML                   0x06
  14 #define ML26124_PLLMH                   0x08
  15 #define ML26124_PLLDIV                  0x0a
  16 #define ML26124_CLK_EN                  0x0c
  17 #define ML26124_CLK_CTL                 0x0e
  18 
  19 /* System Control Register */
  20 #define ML26124_SW_RST                  0x10
  21 #define ML26124_REC_PLYBAK_RUN          0x12
  22 #define ML26124_MIC_TIM                 0x14
  23 
  24 /* Power Mnagement Register */
  25 #define ML26124_PW_REF_PW_MNG           0x20
  26 #define ML26124_PW_IN_PW_MNG            0x22
  27 #define ML26124_PW_DAC_PW_MNG           0x24
  28 #define ML26124_PW_SPAMP_PW_MNG         0x26
  29 #define ML26124_PW_LOUT_PW_MNG          0x28
  30 #define ML26124_PW_VOUT_PW_MNG          0x2a
  31 #define ML26124_PW_ZCCMP_PW_MNG         0x2e
  32 
  33 /* Analog Reference Control Register */
  34 #define ML26124_PW_MICBIAS_VOL          0x30
  35 
  36 /* Input/Output Amplifier Control Register */
  37 #define ML26124_PW_MIC_IN_VOL           0x32
  38 #define ML26124_PW_MIC_BOST_VOL         0x38
  39 #define ML26124_PW_SPK_AMP_VOL          0x3a
  40 #define ML26124_PW_AMP_VOL_FUNC         0x48
  41 #define ML26124_PW_AMP_VOL_FADE         0x4a
  42 
  43 /* Analog Path Control Register */
  44 #define ML26124_SPK_AMP_OUT             0x54
  45 #define ML26124_MIC_IF_CTL              0x5a
  46 #define ML26124_MIC_SELECT              0xe8
  47 
  48 /* Audio Interface Control Register */
  49 #define ML26124_SAI_TRANS_CTL           0x60
  50 #define ML26124_SAI_RCV_CTL             0x62
  51 #define ML26124_SAI_MODE_SEL            0x64
  52 
  53 /* DSP Control Register */
  54 #define ML26124_FILTER_EN               0x66
  55 #define ML26124_DVOL_CTL                0x68
  56 #define ML26124_MIXER_VOL_CTL           0x6a
  57 #define ML26124_RECORD_DIG_VOL          0x6c
  58 #define ML26124_PLBAK_DIG_VOL           0x70
  59 #define ML26124_DIGI_BOOST_VOL          0x72
  60 #define ML26124_EQ_GAIN_BRAND0          0x74
  61 #define ML26124_EQ_GAIN_BRAND1          0x76
  62 #define ML26124_EQ_GAIN_BRAND2          0x78
  63 #define ML26124_EQ_GAIN_BRAND3          0x7a
  64 #define ML26124_EQ_GAIN_BRAND4          0x7c
  65 #define ML26124_HPF2_CUTOFF             0x7e
  66 #define ML26124_EQBRAND0_F0L            0x80
  67 #define ML26124_EQBRAND0_F0H            0x82
  68 #define ML26124_EQBRAND0_F1L            0x84
  69 #define ML26124_EQBRAND0_F1H            0x86
  70 #define ML26124_EQBRAND1_F0L            0x88
  71 #define ML26124_EQBRAND1_F0H            0x8a
  72 #define ML26124_EQBRAND1_F1L            0x8c
  73 #define ML26124_EQBRAND1_F1H            0x8e
  74 #define ML26124_EQBRAND2_F0L            0x90
  75 #define ML26124_EQBRAND2_F0H            0x92
  76 #define ML26124_EQBRAND2_F1L            0x94
  77 #define ML26124_EQBRAND2_F1H            0x96
  78 #define ML26124_EQBRAND3_F0L            0x98
  79 #define ML26124_EQBRAND3_F0H            0x9a
  80 #define ML26124_EQBRAND3_F1L            0x9c
  81 #define ML26124_EQBRAND3_F1H            0x9e
  82 #define ML26124_EQBRAND4_F0L            0xa0
  83 #define ML26124_EQBRAND4_F0H            0xa2
  84 #define ML26124_EQBRAND4_F1L            0xa4
  85 #define ML26124_EQBRAND4_F1H            0xa6
  86 
  87 /* ALC Control Register */
  88 #define ML26124_ALC_MODE                0xb0
  89 #define ML26124_ALC_ATTACK_TIM          0xb2
  90 #define ML26124_ALC_DECAY_TIM           0xb4
  91 #define ML26124_ALC_HOLD_TIM            0xb6
  92 #define ML26124_ALC_TARGET_LEV          0xb8
  93 #define ML26124_ALC_MAXMIN_GAIN         0xba
  94 #define ML26124_NOIS_GATE_THRSH         0xbc
  95 #define ML26124_ALC_ZERO_TIMOUT         0xbe
  96 
  97 /* Playback Limiter Control Register */
  98 #define ML26124_PL_ATTACKTIME           0xc0
  99 #define ML26124_PL_DECAYTIME            0xc2
 100 #define ML26124_PL_TARGETTIME           0xc4
 101 #define ML26124_PL_MAXMIN_GAIN          0xc6
 102 #define ML26124_PLYBAK_BOST_VOL         0xc8
 103 #define ML26124_PL_0CROSS_TIMOUT        0xca
 104 
 105 /* Video Amplifer Control Register */
 106 #define ML26124_VIDEO_AMP_GAIN_CTL      0xd0
 107 #define ML26124_VIDEO_AMP_SETUP1        0xd2
 108 #define ML26124_VIDEO_AMP_CTL2          0xd4
 109 
 110 /* Clock select for machine driver */
 111 #define ML26124_USE_PLL                 0
 112 #define ML26124_USE_MCLKI_256FS         1
 113 #define ML26124_USE_MCLKI_512FS         2
 114 #define ML26124_USE_MCLKI_1024FS        3
 115 
 116 /* Register Mask */
 117 #define ML26124_R0_MASK 0xf
 118 #define ML26124_R2_MASK 0xff
 119 #define ML26124_R4_MASK 0x1
 120 #define ML26124_R6_MASK 0xf
 121 #define ML26124_R8_MASK 0x3f
 122 #define ML26124_Ra_MASK 0x1f
 123 #define ML26124_Rc_MASK 0x1f
 124 #define ML26124_Re_MASK 0x7
 125 #define ML26124_R10_MASK        0x1
 126 #define ML26124_R12_MASK        0x17
 127 #define ML26124_R14_MASK        0x3f
 128 #define ML26124_R20_MASK        0x47
 129 #define ML26124_R22_MASK        0xa
 130 #define ML26124_R24_MASK        0x2
 131 #define ML26124_R26_MASK        0x1f
 132 #define ML26124_R28_MASK        0x2
 133 #define ML26124_R2a_MASK        0x2
 134 #define ML26124_R2e_MASK        0x2
 135 #define ML26124_R30_MASK        0x7
 136 #define ML26124_R32_MASK        0x3f
 137 #define ML26124_R38_MASK        0x38
 138 #define ML26124_R3a_MASK        0x3f
 139 #define ML26124_R48_MASK        0x3
 140 #define ML26124_R4a_MASK        0x7
 141 #define ML26124_R54_MASK        0x2a
 142 #define ML26124_R5a_MASK        0x3
 143 #define ML26124_Re8_MASK        0x3
 144 #define ML26124_R60_MASK        0xff
 145 #define ML26124_R62_MASK        0xff
 146 #define ML26124_R64_MASK        0x1
 147 #define ML26124_R66_MASK        0xff
 148 #define ML26124_R68_MASK        0x3b
 149 #define ML26124_R6a_MASK        0xf3
 150 #define ML26124_R6c_MASK        0xff
 151 #define ML26124_R70_MASK        0xff
 152 
 153 #define ML26124_MCLKEN          BIT(0)
 154 #define ML26124_PLLEN           BIT(1)
 155 #define ML26124_PLLOE           BIT(2)
 156 #define ML26124_MCLKOE          BIT(3)
 157 
 158 #define ML26124_BLT_ALL_ON      0x1f
 159 #define ML26124_BLT_PREAMP_ON   0x13
 160 
 161 #define ML26124_MICBEN_ON       BIT(2)
 162 
 163 enum ml26124_regs {
 164         ML26124_MCLK = 0,
 165 };
 166 
 167 enum ml26124_clk_in {
 168         ML26124_USE_PLLOUT = 0,
 169         ML26124_USE_MCLKI,
 170 };
 171 
 172 #endif