This source file includes following definitions.
- rt5682_volatile_register
- rt5682_readable_register
- rt5682_reset
- rt5682_sel_asrc_clk_src
- rt5682_button_detect
- rt5682_enable_push_button_irq
- rt5682_headset_detect
- rt5682_irq
- rt5682_jd_check_handler
- rt5682_set_jack_detect
- rt5682_jack_detect_handler
- rt5682_div_sel
- set_dmic_clk
- set_filter_clk
- is_sys_clk_from_pll1
- is_using_asrc
- rt5682_charge_pump_event
- rt5682_hp_event
- set_dmic_power
- rt5655_set_verf
- rt5682_set_tdm_slot
- rt5682_hw_params
- rt5682_set_dai_fmt
- rt5682_set_component_sysclk
- rt5682_set_component_pll
- rt5682_set_bclk_ratio
- rt5682_set_bias_level
- rt5682_probe
- rt5682_remove
- rt5682_suspend
- rt5682_resume
- rt5682_parse_dt
- rt5682_calibrate
- rt5682_i2c_probe
- rt5682_i2c_shutdown
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8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/acpi.h>
18 #include <linux/gpio.h>
19 #include <linux/of_gpio.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/mutex.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/jack.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30 #include <sound/rt5682.h>
31
32 #include "rl6231.h"
33 #include "rt5682.h"
34
35 #define RT5682_NUM_SUPPLIES 3
36
37 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
38 "AVDD",
39 "MICVDD",
40 "VBAT",
41 };
42
43 static const struct rt5682_platform_data i2s_default_platform_data = {
44 .dmic1_data_pin = RT5682_DMIC1_DATA_GPIO2,
45 .dmic1_clk_pin = RT5682_DMIC1_CLK_GPIO3,
46 .jd_src = RT5682_JD1,
47 };
48
49 struct rt5682_priv {
50 struct snd_soc_component *component;
51 struct rt5682_platform_data pdata;
52 struct regmap *regmap;
53 struct snd_soc_jack *hs_jack;
54 struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES];
55 struct delayed_work jack_detect_work;
56 struct delayed_work jd_check_work;
57 struct mutex calibrate_mutex;
58
59 int sysclk;
60 int sysclk_src;
61 int lrck[RT5682_AIFS];
62 int bclk[RT5682_AIFS];
63 int master[RT5682_AIFS];
64
65 int pll_src;
66 int pll_in;
67 int pll_out;
68
69 int jack_type;
70 };
71
72 static const struct reg_sequence patch_list[] = {
73 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
74 {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
75 {RT5682_I2C_CTRL, 0x000f},
76 };
77
78 static const struct reg_default rt5682_reg[] = {
79 {0x0002, 0x8080},
80 {0x0003, 0x8000},
81 {0x0005, 0x0000},
82 {0x0006, 0x0000},
83 {0x0008, 0x800f},
84 {0x000b, 0x0000},
85 {0x0010, 0x4040},
86 {0x0011, 0x0000},
87 {0x0012, 0x1404},
88 {0x0013, 0x1000},
89 {0x0014, 0xa00a},
90 {0x0015, 0x0404},
91 {0x0016, 0x0404},
92 {0x0019, 0xafaf},
93 {0x001c, 0x2f2f},
94 {0x001f, 0x0000},
95 {0x0022, 0x5757},
96 {0x0023, 0x0039},
97 {0x0024, 0x000b},
98 {0x0026, 0xc0c4},
99 {0x0029, 0x8080},
100 {0x002a, 0xa0a0},
101 {0x002b, 0x0300},
102 {0x0030, 0x0000},
103 {0x003c, 0x0080},
104 {0x0044, 0x0c0c},
105 {0x0049, 0x0000},
106 {0x0061, 0x0000},
107 {0x0062, 0x0000},
108 {0x0063, 0x003f},
109 {0x0064, 0x0000},
110 {0x0065, 0x0000},
111 {0x0066, 0x0030},
112 {0x0067, 0x0000},
113 {0x006b, 0x0000},
114 {0x006c, 0x0000},
115 {0x006d, 0x2200},
116 {0x006e, 0x0a10},
117 {0x0070, 0x8000},
118 {0x0071, 0x8000},
119 {0x0073, 0x0000},
120 {0x0074, 0x0000},
121 {0x0075, 0x0002},
122 {0x0076, 0x0001},
123 {0x0079, 0x0000},
124 {0x007a, 0x0000},
125 {0x007b, 0x0000},
126 {0x007c, 0x0100},
127 {0x007e, 0x0000},
128 {0x0080, 0x0000},
129 {0x0081, 0x0000},
130 {0x0082, 0x0000},
131 {0x0083, 0x0000},
132 {0x0084, 0x0000},
133 {0x0085, 0x0000},
134 {0x0086, 0x0005},
135 {0x0087, 0x0000},
136 {0x0088, 0x0000},
137 {0x008c, 0x0003},
138 {0x008d, 0x0000},
139 {0x008e, 0x0060},
140 {0x008f, 0x1000},
141 {0x0091, 0x0c26},
142 {0x0092, 0x0073},
143 {0x0093, 0x0000},
144 {0x0094, 0x0080},
145 {0x0098, 0x0000},
146 {0x009a, 0x0000},
147 {0x009b, 0x0000},
148 {0x009c, 0x0000},
149 {0x009d, 0x0000},
150 {0x009e, 0x100c},
151 {0x009f, 0x0000},
152 {0x00a0, 0x0000},
153 {0x00a3, 0x0002},
154 {0x00a4, 0x0001},
155 {0x00ae, 0x2040},
156 {0x00af, 0x0000},
157 {0x00b6, 0x0000},
158 {0x00b7, 0x0000},
159 {0x00b8, 0x0000},
160 {0x00b9, 0x0002},
161 {0x00be, 0x0000},
162 {0x00c0, 0x0160},
163 {0x00c1, 0x82a0},
164 {0x00c2, 0x0000},
165 {0x00d0, 0x0000},
166 {0x00d1, 0x2244},
167 {0x00d2, 0x3300},
168 {0x00d3, 0x2200},
169 {0x00d4, 0x0000},
170 {0x00d9, 0x0009},
171 {0x00da, 0x0000},
172 {0x00db, 0x0000},
173 {0x00dc, 0x00c0},
174 {0x00dd, 0x2220},
175 {0x00de, 0x3131},
176 {0x00df, 0x3131},
177 {0x00e0, 0x3131},
178 {0x00e2, 0x0000},
179 {0x00e3, 0x4000},
180 {0x00e4, 0x0aa0},
181 {0x00e5, 0x3131},
182 {0x00e6, 0x3131},
183 {0x00e7, 0x3131},
184 {0x00e8, 0x3131},
185 {0x00ea, 0xb320},
186 {0x00eb, 0x0000},
187 {0x00f0, 0x0000},
188 {0x00f1, 0x00d0},
189 {0x00f2, 0x00d0},
190 {0x00f6, 0x0000},
191 {0x00fa, 0x0000},
192 {0x00fb, 0x0000},
193 {0x00fc, 0x0000},
194 {0x00fd, 0x0000},
195 {0x00fe, 0x10ec},
196 {0x00ff, 0x6530},
197 {0x0100, 0xa0a0},
198 {0x010b, 0x0000},
199 {0x010c, 0xae00},
200 {0x010d, 0xaaa0},
201 {0x010e, 0x8aa2},
202 {0x010f, 0x02a2},
203 {0x0110, 0xc000},
204 {0x0111, 0x04a2},
205 {0x0112, 0x2800},
206 {0x0113, 0x0000},
207 {0x0117, 0x0100},
208 {0x0125, 0x0410},
209 {0x0132, 0x6026},
210 {0x0136, 0x5555},
211 {0x0138, 0x3700},
212 {0x013a, 0x2000},
213 {0x013b, 0x2000},
214 {0x013c, 0x2005},
215 {0x013f, 0x0000},
216 {0x0142, 0x0000},
217 {0x0145, 0x0002},
218 {0x0146, 0x0000},
219 {0x0147, 0x0000},
220 {0x0148, 0x0000},
221 {0x0149, 0x0000},
222 {0x0150, 0x79a1},
223 {0x0151, 0x0000},
224 {0x0160, 0x4ec0},
225 {0x0161, 0x0080},
226 {0x0162, 0x0200},
227 {0x0163, 0x0800},
228 {0x0164, 0x0000},
229 {0x0165, 0x0000},
230 {0x0166, 0x0000},
231 {0x0167, 0x000f},
232 {0x0168, 0x000f},
233 {0x0169, 0x0021},
234 {0x0190, 0x413d},
235 {0x0194, 0x0000},
236 {0x0195, 0x0000},
237 {0x0197, 0x0022},
238 {0x0198, 0x0000},
239 {0x0199, 0x0000},
240 {0x01af, 0x0000},
241 {0x01b0, 0x0400},
242 {0x01b1, 0x0000},
243 {0x01b2, 0x0000},
244 {0x01b3, 0x0000},
245 {0x01b4, 0x0000},
246 {0x01b5, 0x0000},
247 {0x01b6, 0x01c3},
248 {0x01b7, 0x02a0},
249 {0x01b8, 0x03e9},
250 {0x01b9, 0x1389},
251 {0x01ba, 0xc351},
252 {0x01bb, 0x0009},
253 {0x01bc, 0x0018},
254 {0x01bd, 0x002a},
255 {0x01be, 0x004c},
256 {0x01bf, 0x0097},
257 {0x01c0, 0x433d},
258 {0x01c2, 0x0000},
259 {0x01c3, 0x0000},
260 {0x01c4, 0x0000},
261 {0x01c5, 0x0000},
262 {0x01c6, 0x0000},
263 {0x01c7, 0x0000},
264 {0x01c8, 0x40af},
265 {0x01c9, 0x0702},
266 {0x01ca, 0x0000},
267 {0x01cb, 0x0000},
268 {0x01cc, 0x5757},
269 {0x01cd, 0x5757},
270 {0x01ce, 0x5757},
271 {0x01cf, 0x5757},
272 {0x01d0, 0x5757},
273 {0x01d1, 0x5757},
274 {0x01d2, 0x5757},
275 {0x01d3, 0x5757},
276 {0x01d4, 0x5757},
277 {0x01d5, 0x5757},
278 {0x01d6, 0x0000},
279 {0x01d7, 0x0008},
280 {0x01d8, 0x0029},
281 {0x01d9, 0x3333},
282 {0x01da, 0x0000},
283 {0x01db, 0x0004},
284 {0x01dc, 0x0000},
285 {0x01de, 0x7c00},
286 {0x01df, 0x0320},
287 {0x01e0, 0x06a1},
288 {0x01e1, 0x0000},
289 {0x01e2, 0x0000},
290 {0x01e3, 0x0000},
291 {0x01e4, 0x0000},
292 {0x01e6, 0x0001},
293 {0x01e7, 0x0000},
294 {0x01e8, 0x0000},
295 {0x01ea, 0x0000},
296 {0x01eb, 0x0000},
297 {0x01ec, 0x0000},
298 {0x01ed, 0x0000},
299 {0x01ee, 0x0000},
300 {0x01ef, 0x0000},
301 {0x01f0, 0x0000},
302 {0x01f1, 0x0000},
303 {0x01f2, 0x0000},
304 {0x01f3, 0x0000},
305 {0x01f4, 0x0000},
306 {0x0210, 0x6297},
307 {0x0211, 0xa005},
308 {0x0212, 0x824c},
309 {0x0213, 0xf7ff},
310 {0x0214, 0xf24c},
311 {0x0215, 0x0102},
312 {0x0216, 0x00a3},
313 {0x0217, 0x0048},
314 {0x0218, 0xa2c0},
315 {0x0219, 0x0400},
316 {0x021a, 0x00c8},
317 {0x021b, 0x00c0},
318 {0x021c, 0x0000},
319 {0x0250, 0x4500},
320 {0x0251, 0x40b3},
321 {0x0252, 0x0000},
322 {0x0253, 0x0000},
323 {0x0254, 0x0000},
324 {0x0255, 0x0000},
325 {0x0256, 0x0000},
326 {0x0257, 0x0000},
327 {0x0258, 0x0000},
328 {0x0259, 0x0000},
329 {0x025a, 0x0005},
330 {0x0270, 0x0000},
331 {0x02ff, 0x0110},
332 {0x0300, 0x001f},
333 {0x0301, 0x032c},
334 {0x0302, 0x5f21},
335 {0x0303, 0x4000},
336 {0x0304, 0x4000},
337 {0x0305, 0x06d5},
338 {0x0306, 0x8000},
339 {0x0307, 0x0700},
340 {0x0310, 0x4560},
341 {0x0311, 0xa4a8},
342 {0x0312, 0x7418},
343 {0x0313, 0x0000},
344 {0x0314, 0x0006},
345 {0x0315, 0xffff},
346 {0x0316, 0xc400},
347 {0x0317, 0x0000},
348 {0x03c0, 0x7e00},
349 {0x03c1, 0x8000},
350 {0x03c2, 0x8000},
351 {0x03c3, 0x8000},
352 {0x03c4, 0x8000},
353 {0x03c5, 0x8000},
354 {0x03c6, 0x8000},
355 {0x03c7, 0x8000},
356 {0x03c8, 0x8000},
357 {0x03c9, 0x8000},
358 {0x03ca, 0x8000},
359 {0x03cb, 0x8000},
360 {0x03cc, 0x8000},
361 {0x03d0, 0x0000},
362 {0x03d1, 0x0000},
363 {0x03d2, 0x0000},
364 {0x03d3, 0x0000},
365 {0x03d4, 0x2000},
366 {0x03d5, 0x2000},
367 {0x03d6, 0x0000},
368 {0x03d7, 0x0000},
369 {0x03d8, 0x2000},
370 {0x03d9, 0x2000},
371 {0x03da, 0x2000},
372 {0x03db, 0x2000},
373 {0x03dc, 0x0000},
374 {0x03dd, 0x0000},
375 {0x03de, 0x0000},
376 {0x03df, 0x2000},
377 {0x03e0, 0x0000},
378 {0x03e1, 0x0000},
379 {0x03e2, 0x0000},
380 {0x03e3, 0x0000},
381 {0x03e4, 0x0000},
382 {0x03e5, 0x0000},
383 {0x03e6, 0x0000},
384 {0x03e7, 0x0000},
385 {0x03e8, 0x0000},
386 {0x03e9, 0x0000},
387 {0x03ea, 0x0000},
388 {0x03eb, 0x0000},
389 {0x03ec, 0x0000},
390 {0x03ed, 0x0000},
391 {0x03ee, 0x0000},
392 {0x03ef, 0x0000},
393 {0x03f0, 0x0800},
394 {0x03f1, 0x0800},
395 {0x03f2, 0x0800},
396 {0x03f3, 0x0800},
397 };
398
399 static bool rt5682_volatile_register(struct device *dev, unsigned int reg)
400 {
401 switch (reg) {
402 case RT5682_RESET:
403 case RT5682_CBJ_CTRL_2:
404 case RT5682_INT_ST_1:
405 case RT5682_4BTN_IL_CMD_1:
406 case RT5682_AJD1_CTRL:
407 case RT5682_HP_CALIB_CTRL_1:
408 case RT5682_DEVICE_ID:
409 case RT5682_I2C_MODE:
410 case RT5682_HP_CALIB_CTRL_10:
411 case RT5682_EFUSE_CTRL_2:
412 case RT5682_JD_TOP_VC_VTRL:
413 case RT5682_HP_IMP_SENS_CTRL_19:
414 case RT5682_IL_CMD_1:
415 case RT5682_SAR_IL_CMD_2:
416 case RT5682_SAR_IL_CMD_4:
417 case RT5682_SAR_IL_CMD_10:
418 case RT5682_SAR_IL_CMD_11:
419 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
420 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
421 return true;
422 default:
423 return false;
424 }
425 }
426
427 static bool rt5682_readable_register(struct device *dev, unsigned int reg)
428 {
429 switch (reg) {
430 case RT5682_RESET:
431 case RT5682_VERSION_ID:
432 case RT5682_VENDOR_ID:
433 case RT5682_DEVICE_ID:
434 case RT5682_HP_CTRL_1:
435 case RT5682_HP_CTRL_2:
436 case RT5682_HPL_GAIN:
437 case RT5682_HPR_GAIN:
438 case RT5682_I2C_CTRL:
439 case RT5682_CBJ_BST_CTRL:
440 case RT5682_CBJ_CTRL_1:
441 case RT5682_CBJ_CTRL_2:
442 case RT5682_CBJ_CTRL_3:
443 case RT5682_CBJ_CTRL_4:
444 case RT5682_CBJ_CTRL_5:
445 case RT5682_CBJ_CTRL_6:
446 case RT5682_CBJ_CTRL_7:
447 case RT5682_DAC1_DIG_VOL:
448 case RT5682_STO1_ADC_DIG_VOL:
449 case RT5682_STO1_ADC_BOOST:
450 case RT5682_HP_IMP_GAIN_1:
451 case RT5682_HP_IMP_GAIN_2:
452 case RT5682_SIDETONE_CTRL:
453 case RT5682_STO1_ADC_MIXER:
454 case RT5682_AD_DA_MIXER:
455 case RT5682_STO1_DAC_MIXER:
456 case RT5682_A_DAC1_MUX:
457 case RT5682_DIG_INF2_DATA:
458 case RT5682_REC_MIXER:
459 case RT5682_CAL_REC:
460 case RT5682_ALC_BACK_GAIN:
461 case RT5682_PWR_DIG_1:
462 case RT5682_PWR_DIG_2:
463 case RT5682_PWR_ANLG_1:
464 case RT5682_PWR_ANLG_2:
465 case RT5682_PWR_ANLG_3:
466 case RT5682_PWR_MIXER:
467 case RT5682_PWR_VOL:
468 case RT5682_CLK_DET:
469 case RT5682_RESET_LPF_CTRL:
470 case RT5682_RESET_HPF_CTRL:
471 case RT5682_DMIC_CTRL_1:
472 case RT5682_I2S1_SDP:
473 case RT5682_I2S2_SDP:
474 case RT5682_ADDA_CLK_1:
475 case RT5682_ADDA_CLK_2:
476 case RT5682_I2S1_F_DIV_CTRL_1:
477 case RT5682_I2S1_F_DIV_CTRL_2:
478 case RT5682_TDM_CTRL:
479 case RT5682_TDM_ADDA_CTRL_1:
480 case RT5682_TDM_ADDA_CTRL_2:
481 case RT5682_DATA_SEL_CTRL_1:
482 case RT5682_TDM_TCON_CTRL:
483 case RT5682_GLB_CLK:
484 case RT5682_PLL_CTRL_1:
485 case RT5682_PLL_CTRL_2:
486 case RT5682_PLL_TRACK_1:
487 case RT5682_PLL_TRACK_2:
488 case RT5682_PLL_TRACK_3:
489 case RT5682_PLL_TRACK_4:
490 case RT5682_PLL_TRACK_5:
491 case RT5682_PLL_TRACK_6:
492 case RT5682_PLL_TRACK_11:
493 case RT5682_SDW_REF_CLK:
494 case RT5682_DEPOP_1:
495 case RT5682_DEPOP_2:
496 case RT5682_HP_CHARGE_PUMP_1:
497 case RT5682_HP_CHARGE_PUMP_2:
498 case RT5682_MICBIAS_1:
499 case RT5682_MICBIAS_2:
500 case RT5682_PLL_TRACK_12:
501 case RT5682_PLL_TRACK_14:
502 case RT5682_PLL2_CTRL_1:
503 case RT5682_PLL2_CTRL_2:
504 case RT5682_PLL2_CTRL_3:
505 case RT5682_PLL2_CTRL_4:
506 case RT5682_RC_CLK_CTRL:
507 case RT5682_I2S_M_CLK_CTRL_1:
508 case RT5682_I2S2_F_DIV_CTRL_1:
509 case RT5682_I2S2_F_DIV_CTRL_2:
510 case RT5682_EQ_CTRL_1:
511 case RT5682_EQ_CTRL_2:
512 case RT5682_IRQ_CTRL_1:
513 case RT5682_IRQ_CTRL_2:
514 case RT5682_IRQ_CTRL_3:
515 case RT5682_IRQ_CTRL_4:
516 case RT5682_INT_ST_1:
517 case RT5682_GPIO_CTRL_1:
518 case RT5682_GPIO_CTRL_2:
519 case RT5682_GPIO_CTRL_3:
520 case RT5682_HP_AMP_DET_CTRL_1:
521 case RT5682_HP_AMP_DET_CTRL_2:
522 case RT5682_MID_HP_AMP_DET:
523 case RT5682_LOW_HP_AMP_DET:
524 case RT5682_DELAY_BUF_CTRL:
525 case RT5682_SV_ZCD_1:
526 case RT5682_SV_ZCD_2:
527 case RT5682_IL_CMD_1:
528 case RT5682_IL_CMD_2:
529 case RT5682_IL_CMD_3:
530 case RT5682_IL_CMD_4:
531 case RT5682_IL_CMD_5:
532 case RT5682_IL_CMD_6:
533 case RT5682_4BTN_IL_CMD_1:
534 case RT5682_4BTN_IL_CMD_2:
535 case RT5682_4BTN_IL_CMD_3:
536 case RT5682_4BTN_IL_CMD_4:
537 case RT5682_4BTN_IL_CMD_5:
538 case RT5682_4BTN_IL_CMD_6:
539 case RT5682_4BTN_IL_CMD_7:
540 case RT5682_ADC_STO1_HP_CTRL_1:
541 case RT5682_ADC_STO1_HP_CTRL_2:
542 case RT5682_AJD1_CTRL:
543 case RT5682_JD1_THD:
544 case RT5682_JD2_THD:
545 case RT5682_JD_CTRL_1:
546 case RT5682_DUMMY_1:
547 case RT5682_DUMMY_2:
548 case RT5682_DUMMY_3:
549 case RT5682_DAC_ADC_DIG_VOL1:
550 case RT5682_BIAS_CUR_CTRL_2:
551 case RT5682_BIAS_CUR_CTRL_3:
552 case RT5682_BIAS_CUR_CTRL_4:
553 case RT5682_BIAS_CUR_CTRL_5:
554 case RT5682_BIAS_CUR_CTRL_6:
555 case RT5682_BIAS_CUR_CTRL_7:
556 case RT5682_BIAS_CUR_CTRL_8:
557 case RT5682_BIAS_CUR_CTRL_9:
558 case RT5682_BIAS_CUR_CTRL_10:
559 case RT5682_VREF_REC_OP_FB_CAP_CTRL:
560 case RT5682_CHARGE_PUMP_1:
561 case RT5682_DIG_IN_CTRL_1:
562 case RT5682_PAD_DRIVING_CTRL:
563 case RT5682_SOFT_RAMP_DEPOP:
564 case RT5682_CHOP_DAC:
565 case RT5682_CHOP_ADC:
566 case RT5682_CALIB_ADC_CTRL:
567 case RT5682_VOL_TEST:
568 case RT5682_SPKVDD_DET_STA:
569 case RT5682_TEST_MODE_CTRL_1:
570 case RT5682_TEST_MODE_CTRL_2:
571 case RT5682_TEST_MODE_CTRL_3:
572 case RT5682_TEST_MODE_CTRL_4:
573 case RT5682_TEST_MODE_CTRL_5:
574 case RT5682_PLL1_INTERNAL:
575 case RT5682_PLL2_INTERNAL:
576 case RT5682_STO_NG2_CTRL_1:
577 case RT5682_STO_NG2_CTRL_2:
578 case RT5682_STO_NG2_CTRL_3:
579 case RT5682_STO_NG2_CTRL_4:
580 case RT5682_STO_NG2_CTRL_5:
581 case RT5682_STO_NG2_CTRL_6:
582 case RT5682_STO_NG2_CTRL_7:
583 case RT5682_STO_NG2_CTRL_8:
584 case RT5682_STO_NG2_CTRL_9:
585 case RT5682_STO_NG2_CTRL_10:
586 case RT5682_STO1_DAC_SIL_DET:
587 case RT5682_SIL_PSV_CTRL1:
588 case RT5682_SIL_PSV_CTRL2:
589 case RT5682_SIL_PSV_CTRL3:
590 case RT5682_SIL_PSV_CTRL4:
591 case RT5682_SIL_PSV_CTRL5:
592 case RT5682_HP_IMP_SENS_CTRL_01:
593 case RT5682_HP_IMP_SENS_CTRL_02:
594 case RT5682_HP_IMP_SENS_CTRL_03:
595 case RT5682_HP_IMP_SENS_CTRL_04:
596 case RT5682_HP_IMP_SENS_CTRL_05:
597 case RT5682_HP_IMP_SENS_CTRL_06:
598 case RT5682_HP_IMP_SENS_CTRL_07:
599 case RT5682_HP_IMP_SENS_CTRL_08:
600 case RT5682_HP_IMP_SENS_CTRL_09:
601 case RT5682_HP_IMP_SENS_CTRL_10:
602 case RT5682_HP_IMP_SENS_CTRL_11:
603 case RT5682_HP_IMP_SENS_CTRL_12:
604 case RT5682_HP_IMP_SENS_CTRL_13:
605 case RT5682_HP_IMP_SENS_CTRL_14:
606 case RT5682_HP_IMP_SENS_CTRL_15:
607 case RT5682_HP_IMP_SENS_CTRL_16:
608 case RT5682_HP_IMP_SENS_CTRL_17:
609 case RT5682_HP_IMP_SENS_CTRL_18:
610 case RT5682_HP_IMP_SENS_CTRL_19:
611 case RT5682_HP_IMP_SENS_CTRL_20:
612 case RT5682_HP_IMP_SENS_CTRL_21:
613 case RT5682_HP_IMP_SENS_CTRL_22:
614 case RT5682_HP_IMP_SENS_CTRL_23:
615 case RT5682_HP_IMP_SENS_CTRL_24:
616 case RT5682_HP_IMP_SENS_CTRL_25:
617 case RT5682_HP_IMP_SENS_CTRL_26:
618 case RT5682_HP_IMP_SENS_CTRL_27:
619 case RT5682_HP_IMP_SENS_CTRL_28:
620 case RT5682_HP_IMP_SENS_CTRL_29:
621 case RT5682_HP_IMP_SENS_CTRL_30:
622 case RT5682_HP_IMP_SENS_CTRL_31:
623 case RT5682_HP_IMP_SENS_CTRL_32:
624 case RT5682_HP_IMP_SENS_CTRL_33:
625 case RT5682_HP_IMP_SENS_CTRL_34:
626 case RT5682_HP_IMP_SENS_CTRL_35:
627 case RT5682_HP_IMP_SENS_CTRL_36:
628 case RT5682_HP_IMP_SENS_CTRL_37:
629 case RT5682_HP_IMP_SENS_CTRL_38:
630 case RT5682_HP_IMP_SENS_CTRL_39:
631 case RT5682_HP_IMP_SENS_CTRL_40:
632 case RT5682_HP_IMP_SENS_CTRL_41:
633 case RT5682_HP_IMP_SENS_CTRL_42:
634 case RT5682_HP_IMP_SENS_CTRL_43:
635 case RT5682_HP_LOGIC_CTRL_1:
636 case RT5682_HP_LOGIC_CTRL_2:
637 case RT5682_HP_LOGIC_CTRL_3:
638 case RT5682_HP_CALIB_CTRL_1:
639 case RT5682_HP_CALIB_CTRL_2:
640 case RT5682_HP_CALIB_CTRL_3:
641 case RT5682_HP_CALIB_CTRL_4:
642 case RT5682_HP_CALIB_CTRL_5:
643 case RT5682_HP_CALIB_CTRL_6:
644 case RT5682_HP_CALIB_CTRL_7:
645 case RT5682_HP_CALIB_CTRL_9:
646 case RT5682_HP_CALIB_CTRL_10:
647 case RT5682_HP_CALIB_CTRL_11:
648 case RT5682_HP_CALIB_STA_1:
649 case RT5682_HP_CALIB_STA_2:
650 case RT5682_HP_CALIB_STA_3:
651 case RT5682_HP_CALIB_STA_4:
652 case RT5682_HP_CALIB_STA_5:
653 case RT5682_HP_CALIB_STA_6:
654 case RT5682_HP_CALIB_STA_7:
655 case RT5682_HP_CALIB_STA_8:
656 case RT5682_HP_CALIB_STA_9:
657 case RT5682_HP_CALIB_STA_10:
658 case RT5682_HP_CALIB_STA_11:
659 case RT5682_SAR_IL_CMD_1:
660 case RT5682_SAR_IL_CMD_2:
661 case RT5682_SAR_IL_CMD_3:
662 case RT5682_SAR_IL_CMD_4:
663 case RT5682_SAR_IL_CMD_5:
664 case RT5682_SAR_IL_CMD_6:
665 case RT5682_SAR_IL_CMD_7:
666 case RT5682_SAR_IL_CMD_8:
667 case RT5682_SAR_IL_CMD_9:
668 case RT5682_SAR_IL_CMD_10:
669 case RT5682_SAR_IL_CMD_11:
670 case RT5682_SAR_IL_CMD_12:
671 case RT5682_SAR_IL_CMD_13:
672 case RT5682_EFUSE_CTRL_1:
673 case RT5682_EFUSE_CTRL_2:
674 case RT5682_EFUSE_CTRL_3:
675 case RT5682_EFUSE_CTRL_4:
676 case RT5682_EFUSE_CTRL_5:
677 case RT5682_EFUSE_CTRL_6:
678 case RT5682_EFUSE_CTRL_7:
679 case RT5682_EFUSE_CTRL_8:
680 case RT5682_EFUSE_CTRL_9:
681 case RT5682_EFUSE_CTRL_10:
682 case RT5682_EFUSE_CTRL_11:
683 case RT5682_JD_TOP_VC_VTRL:
684 case RT5682_DRC1_CTRL_0:
685 case RT5682_DRC1_CTRL_1:
686 case RT5682_DRC1_CTRL_2:
687 case RT5682_DRC1_CTRL_3:
688 case RT5682_DRC1_CTRL_4:
689 case RT5682_DRC1_CTRL_5:
690 case RT5682_DRC1_CTRL_6:
691 case RT5682_DRC1_HARD_LMT_CTRL_1:
692 case RT5682_DRC1_HARD_LMT_CTRL_2:
693 case RT5682_DRC1_PRIV_1:
694 case RT5682_DRC1_PRIV_2:
695 case RT5682_DRC1_PRIV_3:
696 case RT5682_DRC1_PRIV_4:
697 case RT5682_DRC1_PRIV_5:
698 case RT5682_DRC1_PRIV_6:
699 case RT5682_DRC1_PRIV_7:
700 case RT5682_DRC1_PRIV_8:
701 case RT5682_EQ_AUTO_RCV_CTRL1:
702 case RT5682_EQ_AUTO_RCV_CTRL2:
703 case RT5682_EQ_AUTO_RCV_CTRL3:
704 case RT5682_EQ_AUTO_RCV_CTRL4:
705 case RT5682_EQ_AUTO_RCV_CTRL5:
706 case RT5682_EQ_AUTO_RCV_CTRL6:
707 case RT5682_EQ_AUTO_RCV_CTRL7:
708 case RT5682_EQ_AUTO_RCV_CTRL8:
709 case RT5682_EQ_AUTO_RCV_CTRL9:
710 case RT5682_EQ_AUTO_RCV_CTRL10:
711 case RT5682_EQ_AUTO_RCV_CTRL11:
712 case RT5682_EQ_AUTO_RCV_CTRL12:
713 case RT5682_EQ_AUTO_RCV_CTRL13:
714 case RT5682_ADC_L_EQ_LPF1_A1:
715 case RT5682_R_EQ_LPF1_A1:
716 case RT5682_L_EQ_LPF1_H0:
717 case RT5682_R_EQ_LPF1_H0:
718 case RT5682_L_EQ_BPF1_A1:
719 case RT5682_R_EQ_BPF1_A1:
720 case RT5682_L_EQ_BPF1_A2:
721 case RT5682_R_EQ_BPF1_A2:
722 case RT5682_L_EQ_BPF1_H0:
723 case RT5682_R_EQ_BPF1_H0:
724 case RT5682_L_EQ_BPF2_A1:
725 case RT5682_R_EQ_BPF2_A1:
726 case RT5682_L_EQ_BPF2_A2:
727 case RT5682_R_EQ_BPF2_A2:
728 case RT5682_L_EQ_BPF2_H0:
729 case RT5682_R_EQ_BPF2_H0:
730 case RT5682_L_EQ_BPF3_A1:
731 case RT5682_R_EQ_BPF3_A1:
732 case RT5682_L_EQ_BPF3_A2:
733 case RT5682_R_EQ_BPF3_A2:
734 case RT5682_L_EQ_BPF3_H0:
735 case RT5682_R_EQ_BPF3_H0:
736 case RT5682_L_EQ_BPF4_A1:
737 case RT5682_R_EQ_BPF4_A1:
738 case RT5682_L_EQ_BPF4_A2:
739 case RT5682_R_EQ_BPF4_A2:
740 case RT5682_L_EQ_BPF4_H0:
741 case RT5682_R_EQ_BPF4_H0:
742 case RT5682_L_EQ_HPF1_A1:
743 case RT5682_R_EQ_HPF1_A1:
744 case RT5682_L_EQ_HPF1_H0:
745 case RT5682_R_EQ_HPF1_H0:
746 case RT5682_L_EQ_PRE_VOL:
747 case RT5682_R_EQ_PRE_VOL:
748 case RT5682_L_EQ_POST_VOL:
749 case RT5682_R_EQ_POST_VOL:
750 case RT5682_I2C_MODE:
751 return true;
752 default:
753 return false;
754 }
755 }
756
757 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
758 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
759 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
760
761
762 static const DECLARE_TLV_DB_RANGE(bst_tlv,
763 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
764 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
765 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
766 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
767 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
768 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
769 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
770 );
771
772
773 static const char * const rt5682_data_select[] = {
774 "L/R", "R/L", "L/L", "R/R"
775 };
776
777 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
778 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
779
780 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
781 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
782
783 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
784 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
785
786 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
787 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
788
789 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
790 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
791
792 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
793 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
794
795 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
796 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
797
798 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
799 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
800
801 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
802 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
803
804 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
805 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
806
807 static void rt5682_reset(struct regmap *regmap)
808 {
809 regmap_write(regmap, RT5682_RESET, 0);
810 regmap_write(regmap, RT5682_I2C_MODE, 1);
811 }
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
827 unsigned int filter_mask, unsigned int clk_src)
828 {
829
830 switch (clk_src) {
831 case RT5682_CLK_SEL_SYS:
832 case RT5682_CLK_SEL_I2S1_ASRC:
833 case RT5682_CLK_SEL_I2S2_ASRC:
834 break;
835
836 default:
837 return -EINVAL;
838 }
839
840 if (filter_mask & RT5682_DA_STEREO1_FILTER) {
841 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
842 RT5682_FILTER_CLK_SEL_MASK,
843 clk_src << RT5682_FILTER_CLK_SEL_SFT);
844 }
845
846 if (filter_mask & RT5682_AD_STEREO1_FILTER) {
847 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
848 RT5682_FILTER_CLK_SEL_MASK,
849 clk_src << RT5682_FILTER_CLK_SEL_SFT);
850 }
851
852 return 0;
853 }
854 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
855
856 static int rt5682_button_detect(struct snd_soc_component *component)
857 {
858 int btn_type, val;
859
860 val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1);
861 btn_type = val & 0xfff0;
862 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
863 pr_debug("%s btn_type=%x\n", __func__, btn_type);
864 snd_soc_component_update_bits(component,
865 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
866
867 return btn_type;
868 }
869
870 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
871 bool enable)
872 {
873 if (enable) {
874 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
875 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
876 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
877 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
878 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
879 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
880 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
881 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
882 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
883 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN);
884 } else {
885 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
886 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
887 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
888 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
889 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
890 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
891 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
892 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
893 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
894 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
895 }
896 }
897
898
899
900
901
902
903
904
905
906
907 static int rt5682_headset_detect(struct snd_soc_component *component,
908 int jack_insert)
909 {
910 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
911 unsigned int val, count;
912
913 if (jack_insert) {
914
915 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
916 RT5682_PWR_VREF2 | RT5682_PWR_MB,
917 RT5682_PWR_VREF2 | RT5682_PWR_MB);
918 snd_soc_component_update_bits(component,
919 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
920 usleep_range(15000, 20000);
921 snd_soc_component_update_bits(component,
922 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
923 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
924 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
925
926 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
927 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
928
929 count = 0;
930 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2)
931 & RT5682_JACK_TYPE_MASK;
932 while (val == 0 && count < 50) {
933 usleep_range(10000, 15000);
934 val = snd_soc_component_read32(component,
935 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
936 count++;
937 }
938
939 switch (val) {
940 case 0x1:
941 case 0x2:
942 rt5682->jack_type = SND_JACK_HEADSET;
943 rt5682_enable_push_button_irq(component, true);
944 break;
945 default:
946 rt5682->jack_type = SND_JACK_HEADPHONE;
947 }
948
949 } else {
950 rt5682_enable_push_button_irq(component, false);
951 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
952 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
953 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
954 RT5682_PWR_VREF2 | RT5682_PWR_MB, 0);
955 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
956 RT5682_PWR_CBJ, 0);
957
958 rt5682->jack_type = 0;
959 }
960
961 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
962 return rt5682->jack_type;
963 }
964
965 static irqreturn_t rt5682_irq(int irq, void *data)
966 {
967 struct rt5682_priv *rt5682 = data;
968
969 mod_delayed_work(system_power_efficient_wq,
970 &rt5682->jack_detect_work, msecs_to_jiffies(250));
971
972 return IRQ_HANDLED;
973 }
974
975 static void rt5682_jd_check_handler(struct work_struct *work)
976 {
977 struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv,
978 jd_check_work.work);
979
980 if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
981 & RT5682_JDH_RS_MASK) {
982
983 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
984
985 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
986 SND_JACK_HEADSET |
987 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
988 SND_JACK_BTN_2 | SND_JACK_BTN_3);
989 } else {
990 schedule_delayed_work(&rt5682->jd_check_work, 500);
991 }
992 }
993
994 static int rt5682_set_jack_detect(struct snd_soc_component *component,
995 struct snd_soc_jack *hs_jack, void *data)
996 {
997 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
998
999 rt5682->hs_jack = hs_jack;
1000
1001 if (!hs_jack) {
1002 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1003 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1004 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1005 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1006 return 0;
1007 }
1008
1009 switch (rt5682->pdata.jd_src) {
1010 case RT5682_JD1:
1011 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2,
1012 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
1013 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042);
1014 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3,
1015 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
1016 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
1017 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
1018 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1019 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1020 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1021 RT5682_POW_IRQ | RT5682_POW_JDH |
1022 RT5682_POW_ANA, RT5682_POW_IRQ |
1023 RT5682_POW_JDH | RT5682_POW_ANA);
1024 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1025 RT5682_PWR_JDH | RT5682_PWR_JDL,
1026 RT5682_PWR_JDH | RT5682_PWR_JDL);
1027 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1028 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1029 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1030 mod_delayed_work(system_power_efficient_wq,
1031 &rt5682->jack_detect_work, msecs_to_jiffies(250));
1032 break;
1033
1034 case RT5682_JD_NULL:
1035 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1036 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1037 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1038 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1039 break;
1040
1041 default:
1042 dev_warn(component->dev, "Wrong JD source\n");
1043 break;
1044 }
1045
1046 return 0;
1047 }
1048
1049 static void rt5682_jack_detect_handler(struct work_struct *work)
1050 {
1051 struct rt5682_priv *rt5682 =
1052 container_of(work, struct rt5682_priv, jack_detect_work.work);
1053 int val, btn_type;
1054
1055 while (!rt5682->component)
1056 usleep_range(10000, 15000);
1057
1058 while (!rt5682->component->card->instantiated)
1059 usleep_range(10000, 15000);
1060
1061 mutex_lock(&rt5682->calibrate_mutex);
1062
1063 val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
1064 & RT5682_JDH_RS_MASK;
1065 if (!val) {
1066
1067 if (rt5682->jack_type == 0) {
1068
1069 rt5682->jack_type =
1070 rt5682_headset_detect(rt5682->component, 1);
1071 } else {
1072
1073 rt5682->jack_type = SND_JACK_HEADSET;
1074 btn_type = rt5682_button_detect(rt5682->component);
1075
1076
1077
1078
1079
1080
1081
1082 switch (btn_type) {
1083 case 0x8000:
1084 case 0x4000:
1085 case 0x2000:
1086 rt5682->jack_type |= SND_JACK_BTN_0;
1087 break;
1088 case 0x1000:
1089 case 0x0800:
1090 case 0x0400:
1091 rt5682->jack_type |= SND_JACK_BTN_1;
1092 break;
1093 case 0x0200:
1094 case 0x0100:
1095 case 0x0080:
1096 rt5682->jack_type |= SND_JACK_BTN_2;
1097 break;
1098 case 0x0040:
1099 case 0x0020:
1100 case 0x0010:
1101 rt5682->jack_type |= SND_JACK_BTN_3;
1102 break;
1103 case 0x0000:
1104 break;
1105 default:
1106 btn_type = 0;
1107 dev_err(rt5682->component->dev,
1108 "Unexpected button code 0x%04x\n",
1109 btn_type);
1110 break;
1111 }
1112 }
1113 } else {
1114
1115 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1116 }
1117
1118 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1119 SND_JACK_HEADSET |
1120 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1121 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1122
1123 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1124 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1125 schedule_delayed_work(&rt5682->jd_check_work, 0);
1126 else
1127 cancel_delayed_work_sync(&rt5682->jd_check_work);
1128
1129 mutex_unlock(&rt5682->calibrate_mutex);
1130 }
1131
1132 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1133
1134 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1135 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 86, 0, dac_vol_tlv),
1136
1137
1138 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1139 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1140
1141
1142 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1143 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1144 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1145 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1146
1147
1148 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1149 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1150 3, 0, adc_bst_tlv),
1151 };
1152
1153
1154 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1155 int target, const int div[], int size)
1156 {
1157 int i;
1158
1159 if (rt5682->sysclk < target) {
1160 pr_err("sysclk rate %d is too low\n",
1161 rt5682->sysclk);
1162 return 0;
1163 }
1164
1165 for (i = 0; i < size - 1; i++) {
1166 pr_info("div[%d]=%d\n", i, div[i]);
1167 if (target * div[i] == rt5682->sysclk)
1168 return i;
1169 if (target * div[i + 1] > rt5682->sysclk) {
1170 pr_err("can't find div for sysclk %d\n",
1171 rt5682->sysclk);
1172 return i;
1173 }
1174 }
1175
1176 if (target * div[i] < rt5682->sysclk)
1177 pr_err("sysclk rate %d is too high\n",
1178 rt5682->sysclk);
1179
1180 return size - 1;
1181
1182 }
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1195 struct snd_kcontrol *kcontrol, int event)
1196 {
1197 struct snd_soc_component *component =
1198 snd_soc_dapm_to_component(w->dapm);
1199 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1200 int idx = -EINVAL;
1201 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1202
1203 idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div));
1204
1205 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1206 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1207
1208 return 0;
1209 }
1210
1211 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1212 struct snd_kcontrol *kcontrol, int event)
1213 {
1214 struct snd_soc_component *component =
1215 snd_soc_dapm_to_component(w->dapm);
1216 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1217 int ref, val, reg, idx = -EINVAL;
1218 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1219 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1220
1221 val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) &
1222 RT5682_GP4_PIN_MASK;
1223 if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1224 val == RT5682_GP4_PIN_ADCDAT2)
1225 ref = 256 * rt5682->lrck[RT5682_AIF2];
1226 else
1227 ref = 256 * rt5682->lrck[RT5682_AIF1];
1228
1229 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1230
1231 if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1232 reg = RT5682_PLL_TRACK_3;
1233 else
1234 reg = RT5682_PLL_TRACK_2;
1235
1236 snd_soc_component_update_bits(component, reg,
1237 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1238
1239
1240 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1241 if (rt5682->sysclk <= 12288000 * div_o[idx])
1242 break;
1243 }
1244
1245 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1246 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1247 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1248
1249 return 0;
1250 }
1251
1252 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1253 struct snd_soc_dapm_widget *sink)
1254 {
1255 unsigned int val;
1256 struct snd_soc_component *component =
1257 snd_soc_dapm_to_component(w->dapm);
1258
1259 val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1260 val &= RT5682_SCLK_SRC_MASK;
1261 if (val == RT5682_SCLK_SRC_PLL1)
1262 return 1;
1263 else
1264 return 0;
1265 }
1266
1267 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1268 struct snd_soc_dapm_widget *sink)
1269 {
1270 unsigned int reg, shift, val;
1271 struct snd_soc_component *component =
1272 snd_soc_dapm_to_component(w->dapm);
1273
1274 switch (w->shift) {
1275 case RT5682_ADC_STO1_ASRC_SFT:
1276 reg = RT5682_PLL_TRACK_3;
1277 shift = RT5682_FILTER_CLK_SEL_SFT;
1278 break;
1279 case RT5682_DAC_STO1_ASRC_SFT:
1280 reg = RT5682_PLL_TRACK_2;
1281 shift = RT5682_FILTER_CLK_SEL_SFT;
1282 break;
1283 default:
1284 return 0;
1285 }
1286
1287 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1288 switch (val) {
1289 case RT5682_CLK_SEL_I2S1_ASRC:
1290 case RT5682_CLK_SEL_I2S2_ASRC:
1291 return 1;
1292 default:
1293 return 0;
1294 }
1295
1296 }
1297
1298
1299 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1300 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1301 RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1302 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1303 RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1304 };
1305
1306 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1307 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1308 RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1309 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1310 RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1311 };
1312
1313 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1314 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1315 RT5682_M_ADCMIX_L_SFT, 1, 1),
1316 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1317 RT5682_M_DAC1_L_SFT, 1, 1),
1318 };
1319
1320 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1321 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1322 RT5682_M_ADCMIX_R_SFT, 1, 1),
1323 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1324 RT5682_M_DAC1_R_SFT, 1, 1),
1325 };
1326
1327 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1328 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1329 RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1330 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1331 RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1332 };
1333
1334 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1335 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1336 RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1337 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1338 RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1339 };
1340
1341
1342 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1343 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1344 RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1345 };
1346
1347
1348
1349 static const char * const rt5682_sto1_adc1_src[] = {
1350 "DAC MIX", "ADC"
1351 };
1352
1353 static SOC_ENUM_SINGLE_DECL(
1354 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1355 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1356
1357 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1358 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1359
1360 static SOC_ENUM_SINGLE_DECL(
1361 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1362 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1363
1364 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1365 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1366
1367
1368
1369 static const char * const rt5682_sto1_adc_src[] = {
1370 "ADC1 L", "ADC1 R"
1371 };
1372
1373 static SOC_ENUM_SINGLE_DECL(
1374 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1375 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1376
1377 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1378 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1379
1380 static SOC_ENUM_SINGLE_DECL(
1381 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1382 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1383
1384 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1385 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1386
1387
1388
1389 static const char * const rt5682_sto1_adc2_src[] = {
1390 "DAC MIX", "DMIC"
1391 };
1392
1393 static SOC_ENUM_SINGLE_DECL(
1394 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1395 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1396
1397 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1398 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1399
1400 static SOC_ENUM_SINGLE_DECL(
1401 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1402 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1403
1404 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1405 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1406
1407
1408 static const unsigned int rt5682_if1_adc_slot_values[] = {
1409 0,
1410 2,
1411 4,
1412 6,
1413 };
1414
1415 static const char * const rt5682_if1_adc_slot_src[] = {
1416 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1417 };
1418
1419 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1420 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1421 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1422
1423 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1424 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1425
1426
1427
1428 static const char * const rt5682_alg_dac1_src[] = {
1429 "Stereo1 DAC Mixer", "DAC1"
1430 };
1431
1432 static SOC_ENUM_SINGLE_DECL(
1433 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1434 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1435
1436 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1437 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1438
1439 static SOC_ENUM_SINGLE_DECL(
1440 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1441 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1442
1443 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1444 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1445
1446
1447 static const struct snd_kcontrol_new hpol_switch =
1448 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1449 RT5682_L_MUTE_SFT, 1, 1);
1450 static const struct snd_kcontrol_new hpor_switch =
1451 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1452 RT5682_R_MUTE_SFT, 1, 1);
1453
1454 static int rt5682_charge_pump_event(struct snd_soc_dapm_widget *w,
1455 struct snd_kcontrol *kcontrol, int event)
1456 {
1457 struct snd_soc_component *component =
1458 snd_soc_dapm_to_component(w->dapm);
1459
1460 switch (event) {
1461 case SND_SOC_DAPM_PRE_PMU:
1462 snd_soc_component_update_bits(component,
1463 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
1464 break;
1465 case SND_SOC_DAPM_POST_PMD:
1466 snd_soc_component_update_bits(component,
1467 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_LV);
1468 break;
1469 default:
1470 return 0;
1471 }
1472
1473 return 0;
1474 }
1475
1476 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1477 struct snd_kcontrol *kcontrol, int event)
1478 {
1479 struct snd_soc_component *component =
1480 snd_soc_dapm_to_component(w->dapm);
1481
1482 switch (event) {
1483 case SND_SOC_DAPM_PRE_PMU:
1484 snd_soc_component_write(component,
1485 RT5682_HP_LOGIC_CTRL_2, 0x0012);
1486 snd_soc_component_write(component,
1487 RT5682_HP_CTRL_2, 0x6000);
1488 snd_soc_component_update_bits(component,
1489 RT5682_DEPOP_1, 0x60, 0x60);
1490 snd_soc_component_update_bits(component,
1491 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1492 break;
1493
1494 case SND_SOC_DAPM_POST_PMD:
1495 snd_soc_component_update_bits(component,
1496 RT5682_DEPOP_1, 0x60, 0x0);
1497 snd_soc_component_write(component,
1498 RT5682_HP_CTRL_2, 0x0000);
1499 snd_soc_component_update_bits(component,
1500 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1501 break;
1502
1503 default:
1504 return 0;
1505 }
1506
1507 return 0;
1508
1509 }
1510
1511 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1512 struct snd_kcontrol *kcontrol, int event)
1513 {
1514 switch (event) {
1515 case SND_SOC_DAPM_POST_PMU:
1516
1517 msleep(150);
1518 break;
1519
1520 default:
1521 return 0;
1522 }
1523
1524 return 0;
1525 }
1526
1527 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
1528 struct snd_kcontrol *kcontrol, int event)
1529 {
1530 struct snd_soc_component *component =
1531 snd_soc_dapm_to_component(w->dapm);
1532
1533 switch (event) {
1534 case SND_SOC_DAPM_PRE_PMU:
1535 switch (w->shift) {
1536 case RT5682_PWR_VREF1_BIT:
1537 snd_soc_component_update_bits(component,
1538 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1539 break;
1540
1541 case RT5682_PWR_VREF2_BIT:
1542 snd_soc_component_update_bits(component,
1543 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1544 break;
1545
1546 default:
1547 break;
1548 }
1549 break;
1550
1551 case SND_SOC_DAPM_POST_PMU:
1552 usleep_range(15000, 20000);
1553 switch (w->shift) {
1554 case RT5682_PWR_VREF1_BIT:
1555 snd_soc_component_update_bits(component,
1556 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1557 RT5682_PWR_FV1);
1558 break;
1559
1560 case RT5682_PWR_VREF2_BIT:
1561 snd_soc_component_update_bits(component,
1562 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1563 RT5682_PWR_FV2);
1564 break;
1565
1566 default:
1567 break;
1568 }
1569 break;
1570
1571 default:
1572 return 0;
1573 }
1574
1575 return 0;
1576 }
1577
1578 static const unsigned int rt5682_adcdat_pin_values[] = {
1579 1,
1580 3,
1581 };
1582
1583 static const char * const rt5682_adcdat_pin_select[] = {
1584 "ADCDAT1",
1585 "ADCDAT2",
1586 };
1587
1588 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1589 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1590 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1591
1592 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1593 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1594
1595 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1596 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1597 0, NULL, 0),
1598 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1599 0, NULL, 0),
1600 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1601 0, NULL, 0),
1602 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1603 0, NULL, 0),
1604 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1605 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1606
1607
1608 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1609 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1610 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1611 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1612 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1613 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1614 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1615 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1616 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1617 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1618
1619
1620 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1621 0, NULL, 0),
1622 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1623 0, NULL, 0),
1624
1625
1626 SND_SOC_DAPM_INPUT("DMIC L1"),
1627 SND_SOC_DAPM_INPUT("DMIC R1"),
1628
1629 SND_SOC_DAPM_INPUT("IN1P"),
1630
1631 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1632 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1633 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1634 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1635
1636
1637 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1638 0, 0, NULL, 0),
1639
1640
1641 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1642 ARRAY_SIZE(rt5682_rec1_l_mix)),
1643 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1644 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1645
1646
1647 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1648 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1649
1650 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1651 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1652 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1653 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1654 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1655 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1656
1657
1658 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1659 &rt5682_sto1_adc1l_mux),
1660 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1661 &rt5682_sto1_adc1r_mux),
1662 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1663 &rt5682_sto1_adc2l_mux),
1664 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1665 &rt5682_sto1_adc2r_mux),
1666 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1667 &rt5682_sto1_adcl_mux),
1668 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1669 &rt5682_sto1_adcr_mux),
1670 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1671 &rt5682_if1_adc_slot_mux),
1672
1673
1674 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1675 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1676 SND_SOC_DAPM_PRE_PMU),
1677 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1678 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1679 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1680 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1681 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1682 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1683 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1684 14, 1, NULL, 0),
1685
1686
1687 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1688
1689
1690 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1691 0, NULL, 0),
1692 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1693 0, NULL, 0),
1694 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1695 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1696 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1697
1698
1699 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1700 &rt5682_if1_01_adc_swap_mux),
1701 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1702 &rt5682_if1_23_adc_swap_mux),
1703 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1704 &rt5682_if1_45_adc_swap_mux),
1705 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1706 &rt5682_if1_67_adc_swap_mux),
1707 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1708 &rt5682_if2_adc_swap_mux),
1709
1710 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1711 &rt5682_adcdat_pin_ctrl),
1712
1713
1714 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1715 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1716 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1717 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1718 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1719
1720
1721
1722 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1723 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1724 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1725 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1726
1727
1728 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1729 &rt5682_alg_dac_l1_mux),
1730 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1731 &rt5682_alg_dac_r1_mux),
1732
1733
1734 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1735 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1736 SND_SOC_DAPM_PRE_PMU),
1737 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1738 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1739 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1740 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1741
1742
1743 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1744 RT5682_PWR_DAC_L1_BIT, 0),
1745 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1746 RT5682_PWR_DAC_R1_BIT, 0),
1747 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1748 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1749
1750
1751 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1752 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1753
1754 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1755 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1756 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1757 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1758 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1759 RT5682_PUMP_EN_SFT, 0, rt5682_charge_pump_event,
1760 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1761 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1762 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1763
1764 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1765 &hpol_switch),
1766 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1767 &hpor_switch),
1768
1769
1770 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1771 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1772 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1773 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1774 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1775 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1776 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1777 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1778
1779
1780 SND_SOC_DAPM_OUTPUT("HPOL"),
1781 SND_SOC_DAPM_OUTPUT("HPOR"),
1782
1783 };
1784
1785 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1786
1787 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1788 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1789
1790
1791 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1792 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1793 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1794 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1795 {"ADC STO1 ASRC", NULL, "CLKDET"},
1796 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1797 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1798 {"DAC STO1 ASRC", NULL, "CLKDET"},
1799
1800
1801 {"MICBIAS1", NULL, "Vref1"},
1802 {"MICBIAS2", NULL, "Vref1"},
1803
1804 {"CLKDET SYS", NULL, "CLKDET"},
1805
1806 {"IN1P", NULL, "LDO2"},
1807
1808 {"BST1 CBJ", NULL, "IN1P"},
1809
1810 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1811 {"RECMIX1L", NULL, "RECMIX1L Power"},
1812
1813 {"ADC1 L", NULL, "RECMIX1L"},
1814 {"ADC1 L", NULL, "ADC1 L Power"},
1815 {"ADC1 L", NULL, "ADC1 clock"},
1816
1817 {"DMIC L1", NULL, "DMIC CLK"},
1818 {"DMIC L1", NULL, "DMIC1 Power"},
1819 {"DMIC R1", NULL, "DMIC CLK"},
1820 {"DMIC R1", NULL, "DMIC1 Power"},
1821 {"DMIC CLK", NULL, "DMIC ASRC"},
1822
1823 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1824 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1825 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1826 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1827
1828 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1829 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1830 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1831 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1832
1833 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1834 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1835 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1836 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1837
1838 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1839 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1840 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1841
1842 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1843 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1844 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1845
1846 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1847
1848 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1849 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1850
1851 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1852 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1853 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1854 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1855 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1856 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1857 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1858 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1859 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1860 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1861 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1862 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1863 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1864 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1865 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1866 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1867
1868 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1869 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1870 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1871 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1872 {"IF1_ADC Mux", NULL, "I2S1"},
1873 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1874 {"AIF1TX", NULL, "ADCDAT Mux"},
1875 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1876 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1877 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1878 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1879 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1880 {"AIF2TX", NULL, "ADCDAT Mux"},
1881
1882 {"IF1 DAC1 L", NULL, "AIF1RX"},
1883 {"IF1 DAC1 L", NULL, "I2S1"},
1884 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1885 {"IF1 DAC1 R", NULL, "AIF1RX"},
1886 {"IF1 DAC1 R", NULL, "I2S1"},
1887 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1888
1889 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1890 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1891 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1892 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1893
1894 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1895 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1896
1897 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1898 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1899
1900 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1901 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1902 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1903 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1904
1905 {"DAC L1", NULL, "DAC L1 Source"},
1906 {"DAC R1", NULL, "DAC R1 Source"},
1907
1908 {"DAC L1", NULL, "DAC 1 Clock"},
1909 {"DAC R1", NULL, "DAC 1 Clock"},
1910
1911 {"HP Amp", NULL, "DAC L1"},
1912 {"HP Amp", NULL, "DAC R1"},
1913 {"HP Amp", NULL, "HP Amp L"},
1914 {"HP Amp", NULL, "HP Amp R"},
1915 {"HP Amp", NULL, "Capless"},
1916 {"HP Amp", NULL, "Charge Pump"},
1917 {"HP Amp", NULL, "CLKDET SYS"},
1918 {"HP Amp", NULL, "Vref1"},
1919 {"HPOL Playback", "Switch", "HP Amp"},
1920 {"HPOR Playback", "Switch", "HP Amp"},
1921 {"HPOL", NULL, "HPOL Playback"},
1922 {"HPOR", NULL, "HPOR Playback"},
1923 };
1924
1925 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1926 unsigned int rx_mask, int slots, int slot_width)
1927 {
1928 struct snd_soc_component *component = dai->component;
1929 unsigned int cl, val = 0;
1930
1931 if (tx_mask || rx_mask)
1932 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1933 RT5682_TDM_EN, RT5682_TDM_EN);
1934 else
1935 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1936 RT5682_TDM_EN, 0);
1937
1938 switch (slots) {
1939 case 4:
1940 val |= RT5682_TDM_TX_CH_4;
1941 val |= RT5682_TDM_RX_CH_4;
1942 break;
1943 case 6:
1944 val |= RT5682_TDM_TX_CH_6;
1945 val |= RT5682_TDM_RX_CH_6;
1946 break;
1947 case 8:
1948 val |= RT5682_TDM_TX_CH_8;
1949 val |= RT5682_TDM_RX_CH_8;
1950 break;
1951 case 2:
1952 break;
1953 default:
1954 return -EINVAL;
1955 }
1956
1957 snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
1958 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
1959
1960 switch (slot_width) {
1961 case 8:
1962 if (tx_mask || rx_mask)
1963 return -EINVAL;
1964 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
1965 break;
1966 case 16:
1967 val = RT5682_TDM_CL_16;
1968 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
1969 break;
1970 case 20:
1971 val = RT5682_TDM_CL_20;
1972 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
1973 break;
1974 case 24:
1975 val = RT5682_TDM_CL_24;
1976 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
1977 break;
1978 case 32:
1979 val = RT5682_TDM_CL_32;
1980 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
1981 break;
1982 default:
1983 return -EINVAL;
1984 }
1985
1986 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
1987 RT5682_TDM_CL_MASK, val);
1988 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
1989 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
1990
1991 return 0;
1992 }
1993
1994
1995 static int rt5682_hw_params(struct snd_pcm_substream *substream,
1996 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1997 {
1998 struct snd_soc_component *component = dai->component;
1999 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2000 unsigned int len_1 = 0, len_2 = 0;
2001 int pre_div, frame_size;
2002
2003 rt5682->lrck[dai->id] = params_rate(params);
2004 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2005
2006 frame_size = snd_soc_params_to_frame_size(params);
2007 if (frame_size < 0) {
2008 dev_err(component->dev, "Unsupported frame size: %d\n",
2009 frame_size);
2010 return -EINVAL;
2011 }
2012
2013 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2014 rt5682->lrck[dai->id], pre_div, dai->id);
2015
2016 switch (params_width(params)) {
2017 case 16:
2018 break;
2019 case 20:
2020 len_1 |= RT5682_I2S1_DL_20;
2021 len_2 |= RT5682_I2S2_DL_20;
2022 break;
2023 case 24:
2024 len_1 |= RT5682_I2S1_DL_24;
2025 len_2 |= RT5682_I2S2_DL_24;
2026 break;
2027 case 32:
2028 len_1 |= RT5682_I2S1_DL_32;
2029 len_2 |= RT5682_I2S2_DL_24;
2030 break;
2031 case 8:
2032 len_1 |= RT5682_I2S2_DL_8;
2033 len_2 |= RT5682_I2S2_DL_8;
2034 break;
2035 default:
2036 return -EINVAL;
2037 }
2038
2039 switch (dai->id) {
2040 case RT5682_AIF1:
2041 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2042 RT5682_I2S1_DL_MASK, len_1);
2043 if (rt5682->master[RT5682_AIF1]) {
2044 snd_soc_component_update_bits(component,
2045 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK,
2046 pre_div << RT5682_I2S_M_DIV_SFT);
2047 }
2048 if (params_channels(params) == 1)
2049 snd_soc_component_update_bits(component,
2050 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2051 RT5682_I2S1_MONO_EN);
2052 else
2053 snd_soc_component_update_bits(component,
2054 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2055 RT5682_I2S1_MONO_DIS);
2056 break;
2057 case RT5682_AIF2:
2058 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2059 RT5682_I2S2_DL_MASK, len_2);
2060 if (rt5682->master[RT5682_AIF2]) {
2061 snd_soc_component_update_bits(component,
2062 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2063 pre_div << RT5682_I2S2_M_PD_SFT);
2064 }
2065 if (params_channels(params) == 1)
2066 snd_soc_component_update_bits(component,
2067 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2068 RT5682_I2S2_MONO_EN);
2069 else
2070 snd_soc_component_update_bits(component,
2071 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2072 RT5682_I2S2_MONO_DIS);
2073 break;
2074 default:
2075 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2076 return -EINVAL;
2077 }
2078
2079 return 0;
2080 }
2081
2082 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2083 {
2084 struct snd_soc_component *component = dai->component;
2085 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2086 unsigned int reg_val = 0, tdm_ctrl = 0;
2087
2088 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2089 case SND_SOC_DAIFMT_CBM_CFM:
2090 rt5682->master[dai->id] = 1;
2091 break;
2092 case SND_SOC_DAIFMT_CBS_CFS:
2093 rt5682->master[dai->id] = 0;
2094 break;
2095 default:
2096 return -EINVAL;
2097 }
2098
2099 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2100 case SND_SOC_DAIFMT_NB_NF:
2101 break;
2102 case SND_SOC_DAIFMT_IB_NF:
2103 reg_val |= RT5682_I2S_BP_INV;
2104 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2105 break;
2106 case SND_SOC_DAIFMT_NB_IF:
2107 if (dai->id == RT5682_AIF1)
2108 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2109 else
2110 return -EINVAL;
2111 break;
2112 case SND_SOC_DAIFMT_IB_IF:
2113 if (dai->id == RT5682_AIF1)
2114 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2115 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2116 else
2117 return -EINVAL;
2118 break;
2119 default:
2120 return -EINVAL;
2121 }
2122
2123 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2124 case SND_SOC_DAIFMT_I2S:
2125 break;
2126 case SND_SOC_DAIFMT_LEFT_J:
2127 reg_val |= RT5682_I2S_DF_LEFT;
2128 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2129 break;
2130 case SND_SOC_DAIFMT_DSP_A:
2131 reg_val |= RT5682_I2S_DF_PCM_A;
2132 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2133 break;
2134 case SND_SOC_DAIFMT_DSP_B:
2135 reg_val |= RT5682_I2S_DF_PCM_B;
2136 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2137 break;
2138 default:
2139 return -EINVAL;
2140 }
2141
2142 switch (dai->id) {
2143 case RT5682_AIF1:
2144 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2145 RT5682_I2S_DF_MASK, reg_val);
2146 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2147 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2148 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2149 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2150 tdm_ctrl | rt5682->master[dai->id]);
2151 break;
2152 case RT5682_AIF2:
2153 if (rt5682->master[dai->id] == 0)
2154 reg_val |= RT5682_I2S2_MS_S;
2155 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2156 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2157 RT5682_I2S_DF_MASK, reg_val);
2158 break;
2159 default:
2160 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2161 return -EINVAL;
2162 }
2163 return 0;
2164 }
2165
2166 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2167 int clk_id, int source, unsigned int freq, int dir)
2168 {
2169 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2170 unsigned int reg_val = 0, src = 0;
2171
2172 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2173 return 0;
2174
2175 switch (clk_id) {
2176 case RT5682_SCLK_S_MCLK:
2177 reg_val |= RT5682_SCLK_SRC_MCLK;
2178 src = RT5682_CLK_SRC_MCLK;
2179 break;
2180 case RT5682_SCLK_S_PLL1:
2181 reg_val |= RT5682_SCLK_SRC_PLL1;
2182 src = RT5682_CLK_SRC_PLL1;
2183 break;
2184 case RT5682_SCLK_S_PLL2:
2185 reg_val |= RT5682_SCLK_SRC_PLL2;
2186 src = RT5682_CLK_SRC_PLL2;
2187 break;
2188 case RT5682_SCLK_S_RCCLK:
2189 reg_val |= RT5682_SCLK_SRC_RCCLK;
2190 src = RT5682_CLK_SRC_RCCLK;
2191 break;
2192 default:
2193 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2194 return -EINVAL;
2195 }
2196 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2197 RT5682_SCLK_SRC_MASK, reg_val);
2198
2199 if (rt5682->master[RT5682_AIF2]) {
2200 snd_soc_component_update_bits(component,
2201 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2202 src << RT5682_I2S2_SRC_SFT);
2203 }
2204
2205 rt5682->sysclk = freq;
2206 rt5682->sysclk_src = clk_id;
2207
2208 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2209 freq, clk_id);
2210
2211 return 0;
2212 }
2213
2214 static int rt5682_set_component_pll(struct snd_soc_component *component,
2215 int pll_id, int source, unsigned int freq_in,
2216 unsigned int freq_out)
2217 {
2218 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2219 struct rl6231_pll_code pll_code;
2220 int ret;
2221
2222 if (source == rt5682->pll_src && freq_in == rt5682->pll_in &&
2223 freq_out == rt5682->pll_out)
2224 return 0;
2225
2226 if (!freq_in || !freq_out) {
2227 dev_dbg(component->dev, "PLL disabled\n");
2228
2229 rt5682->pll_in = 0;
2230 rt5682->pll_out = 0;
2231 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2232 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2233 return 0;
2234 }
2235
2236 switch (source) {
2237 case RT5682_PLL1_S_MCLK:
2238 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2239 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK);
2240 break;
2241 case RT5682_PLL1_S_BCLK1:
2242 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2243 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1);
2244 break;
2245 default:
2246 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2247 return -EINVAL;
2248 }
2249
2250 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2251 if (ret < 0) {
2252 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2253 return ret;
2254 }
2255
2256 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2257 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2258 pll_code.n_code, pll_code.k_code);
2259
2260 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2261 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2262 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2263 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2264 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2265
2266 rt5682->pll_in = freq_in;
2267 rt5682->pll_out = freq_out;
2268 rt5682->pll_src = source;
2269
2270 return 0;
2271 }
2272
2273 static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2274 {
2275 struct snd_soc_component *component = dai->component;
2276 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2277
2278 rt5682->bclk[dai->id] = ratio;
2279
2280 switch (ratio) {
2281 case 64:
2282 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2283 RT5682_I2S2_BCLK_MS2_MASK,
2284 RT5682_I2S2_BCLK_MS2_64);
2285 break;
2286 case 32:
2287 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2288 RT5682_I2S2_BCLK_MS2_MASK,
2289 RT5682_I2S2_BCLK_MS2_32);
2290 break;
2291 default:
2292 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
2293 return -EINVAL;
2294 }
2295
2296 return 0;
2297 }
2298
2299 static int rt5682_set_bias_level(struct snd_soc_component *component,
2300 enum snd_soc_bias_level level)
2301 {
2302 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2303
2304 switch (level) {
2305 case SND_SOC_BIAS_PREPARE:
2306 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2307 RT5682_PWR_BG, RT5682_PWR_BG);
2308 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2309 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2310 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2311 break;
2312
2313 case SND_SOC_BIAS_STANDBY:
2314 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2315 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2316 break;
2317 case SND_SOC_BIAS_OFF:
2318 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2319 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2320 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2321 RT5682_PWR_BG, 0);
2322 break;
2323
2324 default:
2325 break;
2326 }
2327
2328 return 0;
2329 }
2330
2331 static int rt5682_probe(struct snd_soc_component *component)
2332 {
2333 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2334
2335 rt5682->component = component;
2336
2337 return 0;
2338 }
2339
2340 static void rt5682_remove(struct snd_soc_component *component)
2341 {
2342 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2343
2344 rt5682_reset(rt5682->regmap);
2345 }
2346
2347 #ifdef CONFIG_PM
2348 static int rt5682_suspend(struct snd_soc_component *component)
2349 {
2350 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2351
2352 regcache_cache_only(rt5682->regmap, true);
2353 regcache_mark_dirty(rt5682->regmap);
2354 return 0;
2355 }
2356
2357 static int rt5682_resume(struct snd_soc_component *component)
2358 {
2359 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2360
2361 regcache_cache_only(rt5682->regmap, false);
2362 regcache_sync(rt5682->regmap);
2363
2364 rt5682_irq(0, rt5682);
2365
2366 return 0;
2367 }
2368 #else
2369 #define rt5682_suspend NULL
2370 #define rt5682_resume NULL
2371 #endif
2372
2373 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2374 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2375 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2376
2377 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2378 .hw_params = rt5682_hw_params,
2379 .set_fmt = rt5682_set_dai_fmt,
2380 .set_tdm_slot = rt5682_set_tdm_slot,
2381 };
2382
2383 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2384 .hw_params = rt5682_hw_params,
2385 .set_fmt = rt5682_set_dai_fmt,
2386 .set_bclk_ratio = rt5682_set_bclk_ratio,
2387 };
2388
2389 static struct snd_soc_dai_driver rt5682_dai[] = {
2390 {
2391 .name = "rt5682-aif1",
2392 .id = RT5682_AIF1,
2393 .playback = {
2394 .stream_name = "AIF1 Playback",
2395 .channels_min = 1,
2396 .channels_max = 2,
2397 .rates = RT5682_STEREO_RATES,
2398 .formats = RT5682_FORMATS,
2399 },
2400 .capture = {
2401 .stream_name = "AIF1 Capture",
2402 .channels_min = 1,
2403 .channels_max = 2,
2404 .rates = RT5682_STEREO_RATES,
2405 .formats = RT5682_FORMATS,
2406 },
2407 .ops = &rt5682_aif1_dai_ops,
2408 },
2409 {
2410 .name = "rt5682-aif2",
2411 .id = RT5682_AIF2,
2412 .capture = {
2413 .stream_name = "AIF2 Capture",
2414 .channels_min = 1,
2415 .channels_max = 2,
2416 .rates = RT5682_STEREO_RATES,
2417 .formats = RT5682_FORMATS,
2418 },
2419 .ops = &rt5682_aif2_dai_ops,
2420 },
2421 };
2422
2423 static const struct snd_soc_component_driver soc_component_dev_rt5682 = {
2424 .probe = rt5682_probe,
2425 .remove = rt5682_remove,
2426 .suspend = rt5682_suspend,
2427 .resume = rt5682_resume,
2428 .set_bias_level = rt5682_set_bias_level,
2429 .controls = rt5682_snd_controls,
2430 .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2431 .dapm_widgets = rt5682_dapm_widgets,
2432 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2433 .dapm_routes = rt5682_dapm_routes,
2434 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2435 .set_sysclk = rt5682_set_component_sysclk,
2436 .set_pll = rt5682_set_component_pll,
2437 .set_jack = rt5682_set_jack_detect,
2438 .use_pmdown_time = 1,
2439 .endianness = 1,
2440 .non_legacy_dai_naming = 1,
2441 };
2442
2443 static const struct regmap_config rt5682_regmap = {
2444 .reg_bits = 16,
2445 .val_bits = 16,
2446 .max_register = RT5682_I2C_MODE,
2447 .volatile_reg = rt5682_volatile_register,
2448 .readable_reg = rt5682_readable_register,
2449 .cache_type = REGCACHE_RBTREE,
2450 .reg_defaults = rt5682_reg,
2451 .num_reg_defaults = ARRAY_SIZE(rt5682_reg),
2452 .use_single_read = true,
2453 .use_single_write = true,
2454 };
2455
2456 static const struct i2c_device_id rt5682_i2c_id[] = {
2457 {"rt5682", 0},
2458 {}
2459 };
2460 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id);
2461
2462 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2463 {
2464
2465 device_property_read_u32(dev, "realtek,dmic1-data-pin",
2466 &rt5682->pdata.dmic1_data_pin);
2467 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2468 &rt5682->pdata.dmic1_clk_pin);
2469 device_property_read_u32(dev, "realtek,jd-src",
2470 &rt5682->pdata.jd_src);
2471
2472 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2473 "realtek,ldo1-en-gpios", 0);
2474
2475 return 0;
2476 }
2477
2478 static void rt5682_calibrate(struct rt5682_priv *rt5682)
2479 {
2480 int value, count;
2481
2482 mutex_lock(&rt5682->calibrate_mutex);
2483
2484 rt5682_reset(rt5682->regmap);
2485 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
2486 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
2487 usleep_range(15000, 20000);
2488 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
2489 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
2490 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
2491 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
2492 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
2493 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
2494 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
2495 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
2496 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
2497 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
2498 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
2499 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2500 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
2501 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
2502 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2503
2504 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
2505
2506 for (count = 0; count < 60; count++) {
2507 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
2508 if (!(value & 0x8000))
2509 break;
2510
2511 usleep_range(10000, 10005);
2512 }
2513
2514 if (count >= 60)
2515 pr_err("HP Calibration Failure\n");
2516
2517
2518 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x02af);
2519 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
2520 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
2521 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
2522 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
2523 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
2524 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
2525
2526 mutex_unlock(&rt5682->calibrate_mutex);
2527
2528 }
2529
2530 static int rt5682_i2c_probe(struct i2c_client *i2c,
2531 const struct i2c_device_id *id)
2532 {
2533 struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev);
2534 struct rt5682_priv *rt5682;
2535 int i, ret;
2536 unsigned int val;
2537
2538 rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv),
2539 GFP_KERNEL);
2540
2541 if (rt5682 == NULL)
2542 return -ENOMEM;
2543
2544 i2c_set_clientdata(i2c, rt5682);
2545
2546 rt5682->pdata = i2s_default_platform_data;
2547
2548 if (pdata)
2549 rt5682->pdata = *pdata;
2550 else
2551 rt5682_parse_dt(rt5682, &i2c->dev);
2552
2553 rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap);
2554 if (IS_ERR(rt5682->regmap)) {
2555 ret = PTR_ERR(rt5682->regmap);
2556 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2557 ret);
2558 return ret;
2559 }
2560
2561 for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++)
2562 rt5682->supplies[i].supply = rt5682_supply_names[i];
2563
2564 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies),
2565 rt5682->supplies);
2566 if (ret != 0) {
2567 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2568 return ret;
2569 }
2570
2571 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies),
2572 rt5682->supplies);
2573 if (ret != 0) {
2574 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2575 return ret;
2576 }
2577
2578 if (gpio_is_valid(rt5682->pdata.ldo1_en)) {
2579 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en,
2580 GPIOF_OUT_INIT_HIGH, "rt5682"))
2581 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
2582 }
2583
2584
2585 usleep_range(300000, 350000);
2586
2587 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1);
2588 usleep_range(10000, 15000);
2589
2590 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
2591 if (val != DEVICE_ID) {
2592 pr_err("Device with ID register %x is not rt5682\n", val);
2593 return -ENODEV;
2594 }
2595
2596 rt5682_reset(rt5682->regmap);
2597
2598 mutex_init(&rt5682->calibrate_mutex);
2599 rt5682_calibrate(rt5682);
2600
2601 ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
2602 ARRAY_SIZE(patch_list));
2603 if (ret != 0)
2604 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2605
2606 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
2607
2608
2609 if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) {
2610 switch (rt5682->pdata.dmic1_data_pin) {
2611 case RT5682_DMIC1_DATA_GPIO2:
2612 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2613 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2);
2614 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2615 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA);
2616 break;
2617
2618 case RT5682_DMIC1_DATA_GPIO5:
2619 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2620 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5);
2621 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2622 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA);
2623 break;
2624
2625 default:
2626 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
2627 break;
2628 }
2629
2630 switch (rt5682->pdata.dmic1_clk_pin) {
2631 case RT5682_DMIC1_CLK_GPIO1:
2632 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2633 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK);
2634 break;
2635
2636 case RT5682_DMIC1_CLK_GPIO3:
2637 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2638 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK);
2639 break;
2640
2641 default:
2642 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
2643 break;
2644 }
2645 }
2646
2647 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2648 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
2649 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
2650 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
2651 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2652 RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK,
2653 RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1);
2654 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
2655 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
2656 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
2657 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
2658 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
2659
2660 INIT_DELAYED_WORK(&rt5682->jack_detect_work,
2661 rt5682_jack_detect_handler);
2662 INIT_DELAYED_WORK(&rt5682->jd_check_work,
2663 rt5682_jd_check_handler);
2664
2665
2666 if (i2c->irq) {
2667 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2668 rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2669 | IRQF_ONESHOT, "rt5682", rt5682);
2670 if (ret)
2671 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2672
2673 }
2674
2675 return devm_snd_soc_register_component(&i2c->dev,
2676 &soc_component_dev_rt5682,
2677 rt5682_dai, ARRAY_SIZE(rt5682_dai));
2678 }
2679
2680 static void rt5682_i2c_shutdown(struct i2c_client *client)
2681 {
2682 struct rt5682_priv *rt5682 = i2c_get_clientdata(client);
2683
2684 rt5682_reset(rt5682->regmap);
2685 }
2686
2687 #ifdef CONFIG_OF
2688 static const struct of_device_id rt5682_of_match[] = {
2689 {.compatible = "realtek,rt5682i"},
2690 {},
2691 };
2692 MODULE_DEVICE_TABLE(of, rt5682_of_match);
2693 #endif
2694
2695 #ifdef CONFIG_ACPI
2696 static const struct acpi_device_id rt5682_acpi_match[] = {
2697 {"10EC5682", 0,},
2698 {},
2699 };
2700 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match);
2701 #endif
2702
2703 static struct i2c_driver rt5682_i2c_driver = {
2704 .driver = {
2705 .name = "rt5682",
2706 .of_match_table = of_match_ptr(rt5682_of_match),
2707 .acpi_match_table = ACPI_PTR(rt5682_acpi_match),
2708 },
2709 .probe = rt5682_i2c_probe,
2710 .shutdown = rt5682_i2c_shutdown,
2711 .id_table = rt5682_i2c_id,
2712 };
2713 module_i2c_driver(rt5682_i2c_driver);
2714
2715 MODULE_DESCRIPTION("ASoC RT5682 driver");
2716 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2717 MODULE_LICENSE("GPL v2");