root/sound/soc/codecs/wm8903.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * wm8903.h - WM8903 audio codec interface
   4  *
   5  * Copyright 2008 Wolfson Microelectronics PLC.
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  */
   8 
   9 #ifndef _WM8903_H
  10 #define _WM8903_H
  11 
  12 #include <linux/i2c.h>
  13 
  14 extern int wm8903_mic_detect(struct snd_soc_component *component,
  15                              struct snd_soc_jack *jack,
  16                              int det, int shrt);
  17 
  18 
  19 /*
  20  * Register values.
  21  */
  22 #define WM8903_SW_RESET_AND_ID                  0x00
  23 #define WM8903_REVISION_NUMBER                  0x01
  24 #define WM8903_BIAS_CONTROL_0                   0x04
  25 #define WM8903_VMID_CONTROL_0                   0x05
  26 #define WM8903_MIC_BIAS_CONTROL_0               0x06
  27 #define WM8903_ANALOGUE_DAC_0                   0x08
  28 #define WM8903_ANALOGUE_ADC_0                   0x0A
  29 #define WM8903_POWER_MANAGEMENT_0               0x0C
  30 #define WM8903_POWER_MANAGEMENT_1               0x0D
  31 #define WM8903_POWER_MANAGEMENT_2               0x0E
  32 #define WM8903_POWER_MANAGEMENT_3               0x0F
  33 #define WM8903_POWER_MANAGEMENT_4               0x10
  34 #define WM8903_POWER_MANAGEMENT_5               0x11
  35 #define WM8903_POWER_MANAGEMENT_6               0x12
  36 #define WM8903_CLOCK_RATES_0                    0x14
  37 #define WM8903_CLOCK_RATES_1                    0x15
  38 #define WM8903_CLOCK_RATES_2                    0x16
  39 #define WM8903_AUDIO_INTERFACE_0                0x18
  40 #define WM8903_AUDIO_INTERFACE_1                0x19
  41 #define WM8903_AUDIO_INTERFACE_2                0x1A
  42 #define WM8903_AUDIO_INTERFACE_3                0x1B
  43 #define WM8903_DAC_DIGITAL_VOLUME_LEFT          0x1E
  44 #define WM8903_DAC_DIGITAL_VOLUME_RIGHT         0x1F
  45 #define WM8903_DAC_DIGITAL_0                    0x20
  46 #define WM8903_DAC_DIGITAL_1                    0x21
  47 #define WM8903_ADC_DIGITAL_VOLUME_LEFT          0x24
  48 #define WM8903_ADC_DIGITAL_VOLUME_RIGHT         0x25
  49 #define WM8903_ADC_DIGITAL_0                    0x26
  50 #define WM8903_DIGITAL_MICROPHONE_0             0x27
  51 #define WM8903_DRC_0                            0x28
  52 #define WM8903_DRC_1                            0x29
  53 #define WM8903_DRC_2                            0x2A
  54 #define WM8903_DRC_3                            0x2B
  55 #define WM8903_ANALOGUE_LEFT_INPUT_0            0x2C
  56 #define WM8903_ANALOGUE_RIGHT_INPUT_0           0x2D
  57 #define WM8903_ANALOGUE_LEFT_INPUT_1            0x2E
  58 #define WM8903_ANALOGUE_RIGHT_INPUT_1           0x2F
  59 #define WM8903_ANALOGUE_LEFT_MIX_0              0x32
  60 #define WM8903_ANALOGUE_RIGHT_MIX_0             0x33
  61 #define WM8903_ANALOGUE_SPK_MIX_LEFT_0          0x34
  62 #define WM8903_ANALOGUE_SPK_MIX_LEFT_1          0x35
  63 #define WM8903_ANALOGUE_SPK_MIX_RIGHT_0         0x36
  64 #define WM8903_ANALOGUE_SPK_MIX_RIGHT_1         0x37
  65 #define WM8903_ANALOGUE_OUT1_LEFT               0x39
  66 #define WM8903_ANALOGUE_OUT1_RIGHT              0x3A
  67 #define WM8903_ANALOGUE_OUT2_LEFT               0x3B
  68 #define WM8903_ANALOGUE_OUT2_RIGHT              0x3C
  69 #define WM8903_ANALOGUE_OUT3_LEFT               0x3E
  70 #define WM8903_ANALOGUE_OUT3_RIGHT              0x3F
  71 #define WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0    0x41
  72 #define WM8903_DC_SERVO_0                       0x43
  73 #define WM8903_DC_SERVO_2                       0x45
  74 #define WM8903_DC_SERVO_4                       0x47
  75 #define WM8903_DC_SERVO_5                       0x48
  76 #define WM8903_DC_SERVO_6                       0x49
  77 #define WM8903_DC_SERVO_7                       0x4A
  78 #define WM8903_DC_SERVO_READBACK_1              0x51
  79 #define WM8903_DC_SERVO_READBACK_2              0x52
  80 #define WM8903_DC_SERVO_READBACK_3              0x53
  81 #define WM8903_DC_SERVO_READBACK_4              0x54
  82 #define WM8903_ANALOGUE_HP_0                    0x5A
  83 #define WM8903_ANALOGUE_LINEOUT_0               0x5E
  84 #define WM8903_CHARGE_PUMP_0                    0x62
  85 #define WM8903_CLASS_W_0                        0x68
  86 #define WM8903_WRITE_SEQUENCER_0                0x6C
  87 #define WM8903_WRITE_SEQUENCER_1                0x6D
  88 #define WM8903_WRITE_SEQUENCER_2                0x6E
  89 #define WM8903_WRITE_SEQUENCER_3                0x6F
  90 #define WM8903_WRITE_SEQUENCER_4                0x70
  91 #define WM8903_CONTROL_INTERFACE                0x72
  92 #define WM8903_GPIO_CONTROL_1                   0x74
  93 #define WM8903_GPIO_CONTROL_2                   0x75
  94 #define WM8903_GPIO_CONTROL_3                   0x76
  95 #define WM8903_GPIO_CONTROL_4                   0x77
  96 #define WM8903_GPIO_CONTROL_5                   0x78
  97 #define WM8903_INTERRUPT_STATUS_1               0x79
  98 #define WM8903_INTERRUPT_STATUS_1_MASK          0x7A
  99 #define WM8903_INTERRUPT_POLARITY_1             0x7B
 100 #define WM8903_INTERRUPT_CONTROL                0x7E
 101 #define WM8903_CLOCK_RATE_TEST_4                0xA4
 102 #define WM8903_ANALOGUE_OUTPUT_BIAS_0           0xAC
 103 
 104 #define WM8903_REGISTER_COUNT                   75
 105 #define WM8903_MAX_REGISTER                     0xAC
 106 
 107 /*
 108  * Field Definitions.
 109  */
 110 
 111 /*
 112  * R0 (0x00) - SW Reset and ID
 113  */
 114 #define WM8903_SW_RESET_DEV_ID1_MASK            0xFFFF  /* SW_RESET_DEV_ID1 - [15:0] */
 115 #define WM8903_SW_RESET_DEV_ID1_SHIFT                0  /* SW_RESET_DEV_ID1 - [15:0] */
 116 #define WM8903_SW_RESET_DEV_ID1_WIDTH               16  /* SW_RESET_DEV_ID1 - [15:0] */
 117 
 118 /*
 119  * R1 (0x01) - Revision Number
 120  */
 121 #define WM8903_CHIP_REV_MASK                    0x000F  /* CHIP_REV - [3:0] */
 122 #define WM8903_CHIP_REV_SHIFT                        0  /* CHIP_REV - [3:0] */
 123 #define WM8903_CHIP_REV_WIDTH                        4  /* CHIP_REV - [3:0] */
 124 
 125 /*
 126  * R4 (0x04) - Bias Control 0
 127  */
 128 #define WM8903_POBCTRL                          0x0010  /* POBCTRL */
 129 #define WM8903_POBCTRL_MASK                     0x0010  /* POBCTRL */
 130 #define WM8903_POBCTRL_SHIFT                         4  /* POBCTRL */
 131 #define WM8903_POBCTRL_WIDTH                         1  /* POBCTRL */
 132 #define WM8903_ISEL_MASK                        0x000C  /* ISEL - [3:2] */
 133 #define WM8903_ISEL_SHIFT                            2  /* ISEL - [3:2] */
 134 #define WM8903_ISEL_WIDTH                            2  /* ISEL - [3:2] */
 135 #define WM8903_STARTUP_BIAS_ENA                 0x0002  /* STARTUP_BIAS_ENA */
 136 #define WM8903_STARTUP_BIAS_ENA_MASK            0x0002  /* STARTUP_BIAS_ENA */
 137 #define WM8903_STARTUP_BIAS_ENA_SHIFT                1  /* STARTUP_BIAS_ENA */
 138 #define WM8903_STARTUP_BIAS_ENA_WIDTH                1  /* STARTUP_BIAS_ENA */
 139 #define WM8903_BIAS_ENA                         0x0001  /* BIAS_ENA */
 140 #define WM8903_BIAS_ENA_MASK                    0x0001  /* BIAS_ENA */
 141 #define WM8903_BIAS_ENA_SHIFT                        0  /* BIAS_ENA */
 142 #define WM8903_BIAS_ENA_WIDTH                        1  /* BIAS_ENA */
 143 
 144 /*
 145  * R5 (0x05) - VMID Control 0
 146  */
 147 #define WM8903_VMID_TIE_ENA                     0x0080  /* VMID_TIE_ENA */
 148 #define WM8903_VMID_TIE_ENA_MASK                0x0080  /* VMID_TIE_ENA */
 149 #define WM8903_VMID_TIE_ENA_SHIFT                    7  /* VMID_TIE_ENA */
 150 #define WM8903_VMID_TIE_ENA_WIDTH                    1  /* VMID_TIE_ENA */
 151 #define WM8903_BUFIO_ENA                        0x0040  /* BUFIO_ENA */
 152 #define WM8903_BUFIO_ENA_MASK                   0x0040  /* BUFIO_ENA */
 153 #define WM8903_BUFIO_ENA_SHIFT                       6  /* BUFIO_ENA */
 154 #define WM8903_BUFIO_ENA_WIDTH                       1  /* BUFIO_ENA */
 155 #define WM8903_VMID_IO_ENA                      0x0020  /* VMID_IO_ENA */
 156 #define WM8903_VMID_IO_ENA_MASK                 0x0020  /* VMID_IO_ENA */
 157 #define WM8903_VMID_IO_ENA_SHIFT                     5  /* VMID_IO_ENA */
 158 #define WM8903_VMID_IO_ENA_WIDTH                     1  /* VMID_IO_ENA */
 159 #define WM8903_VMID_SOFT_MASK                   0x0018  /* VMID_SOFT - [4:3] */
 160 #define WM8903_VMID_SOFT_SHIFT                       3  /* VMID_SOFT - [4:3] */
 161 #define WM8903_VMID_SOFT_WIDTH                       2  /* VMID_SOFT - [4:3] */
 162 #define WM8903_VMID_RES_MASK                    0x0006  /* VMID_RES - [2:1] */
 163 #define WM8903_VMID_RES_SHIFT                        1  /* VMID_RES - [2:1] */
 164 #define WM8903_VMID_RES_WIDTH                        2  /* VMID_RES - [2:1] */
 165 #define WM8903_VMID_BUF_ENA                     0x0001  /* VMID_BUF_ENA */
 166 #define WM8903_VMID_BUF_ENA_MASK                0x0001  /* VMID_BUF_ENA */
 167 #define WM8903_VMID_BUF_ENA_SHIFT                    0  /* VMID_BUF_ENA */
 168 #define WM8903_VMID_BUF_ENA_WIDTH                    1  /* VMID_BUF_ENA */
 169 
 170 #define WM8903_VMID_RES_50K                          2
 171 #define WM8903_VMID_RES_250K                         4
 172 #define WM8903_VMID_RES_5K                           6
 173 
 174 /*
 175  * R8 (0x08) - Analogue DAC 0
 176  */
 177 #define WM8903_DACBIAS_SEL_MASK                 0x0018  /* DACBIAS_SEL - [4:3] */
 178 #define WM8903_DACBIAS_SEL_SHIFT                     3  /* DACBIAS_SEL - [4:3] */
 179 #define WM8903_DACBIAS_SEL_WIDTH                     2  /* DACBIAS_SEL - [4:3] */
 180 #define WM8903_DACVMID_BIAS_SEL_MASK            0x0006  /* DACVMID_BIAS_SEL - [2:1] */
 181 #define WM8903_DACVMID_BIAS_SEL_SHIFT                1  /* DACVMID_BIAS_SEL - [2:1] */
 182 #define WM8903_DACVMID_BIAS_SEL_WIDTH                2  /* DACVMID_BIAS_SEL - [2:1] */
 183 
 184 /*
 185  * R10 (0x0A) - Analogue ADC 0
 186  */
 187 #define WM8903_ADC_OSR128                       0x0001  /* ADC_OSR128 */
 188 #define WM8903_ADC_OSR128_MASK                  0x0001  /* ADC_OSR128 */
 189 #define WM8903_ADC_OSR128_SHIFT                      0  /* ADC_OSR128 */
 190 #define WM8903_ADC_OSR128_WIDTH                      1  /* ADC_OSR128 */
 191 
 192 /*
 193  * R12 (0x0C) - Power Management 0
 194  */
 195 #define WM8903_INL_ENA                          0x0002  /* INL_ENA */
 196 #define WM8903_INL_ENA_MASK                     0x0002  /* INL_ENA */
 197 #define WM8903_INL_ENA_SHIFT                         1  /* INL_ENA */
 198 #define WM8903_INL_ENA_WIDTH                         1  /* INL_ENA */
 199 #define WM8903_INR_ENA                          0x0001  /* INR_ENA */
 200 #define WM8903_INR_ENA_MASK                     0x0001  /* INR_ENA */
 201 #define WM8903_INR_ENA_SHIFT                         0  /* INR_ENA */
 202 #define WM8903_INR_ENA_WIDTH                         1  /* INR_ENA */
 203 
 204 /*
 205  * R13 (0x0D) - Power Management 1
 206  */
 207 #define WM8903_MIXOUTL_ENA                      0x0002  /* MIXOUTL_ENA */
 208 #define WM8903_MIXOUTL_ENA_MASK                 0x0002  /* MIXOUTL_ENA */
 209 #define WM8903_MIXOUTL_ENA_SHIFT                     1  /* MIXOUTL_ENA */
 210 #define WM8903_MIXOUTL_ENA_WIDTH                     1  /* MIXOUTL_ENA */
 211 #define WM8903_MIXOUTR_ENA                      0x0001  /* MIXOUTR_ENA */
 212 #define WM8903_MIXOUTR_ENA_MASK                 0x0001  /* MIXOUTR_ENA */
 213 #define WM8903_MIXOUTR_ENA_SHIFT                     0  /* MIXOUTR_ENA */
 214 #define WM8903_MIXOUTR_ENA_WIDTH                     1  /* MIXOUTR_ENA */
 215 
 216 /*
 217  * R14 (0x0E) - Power Management 2
 218  */
 219 #define WM8903_HPL_PGA_ENA                      0x0002  /* HPL_PGA_ENA */
 220 #define WM8903_HPL_PGA_ENA_MASK                 0x0002  /* HPL_PGA_ENA */
 221 #define WM8903_HPL_PGA_ENA_SHIFT                     1  /* HPL_PGA_ENA */
 222 #define WM8903_HPL_PGA_ENA_WIDTH                     1  /* HPL_PGA_ENA */
 223 #define WM8903_HPR_PGA_ENA                      0x0001  /* HPR_PGA_ENA */
 224 #define WM8903_HPR_PGA_ENA_MASK                 0x0001  /* HPR_PGA_ENA */
 225 #define WM8903_HPR_PGA_ENA_SHIFT                     0  /* HPR_PGA_ENA */
 226 #define WM8903_HPR_PGA_ENA_WIDTH                     1  /* HPR_PGA_ENA */
 227 
 228 /*
 229  * R15 (0x0F) - Power Management 3
 230  */
 231 #define WM8903_LINEOUTL_PGA_ENA                 0x0002  /* LINEOUTL_PGA_ENA */
 232 #define WM8903_LINEOUTL_PGA_ENA_MASK            0x0002  /* LINEOUTL_PGA_ENA */
 233 #define WM8903_LINEOUTL_PGA_ENA_SHIFT                1  /* LINEOUTL_PGA_ENA */
 234 #define WM8903_LINEOUTL_PGA_ENA_WIDTH                1  /* LINEOUTL_PGA_ENA */
 235 #define WM8903_LINEOUTR_PGA_ENA                 0x0001  /* LINEOUTR_PGA_ENA */
 236 #define WM8903_LINEOUTR_PGA_ENA_MASK            0x0001  /* LINEOUTR_PGA_ENA */
 237 #define WM8903_LINEOUTR_PGA_ENA_SHIFT                0  /* LINEOUTR_PGA_ENA */
 238 #define WM8903_LINEOUTR_PGA_ENA_WIDTH                1  /* LINEOUTR_PGA_ENA */
 239 
 240 /*
 241  * R16 (0x10) - Power Management 4
 242  */
 243 #define WM8903_MIXSPKL_ENA                      0x0002  /* MIXSPKL_ENA */
 244 #define WM8903_MIXSPKL_ENA_MASK                 0x0002  /* MIXSPKL_ENA */
 245 #define WM8903_MIXSPKL_ENA_SHIFT                     1  /* MIXSPKL_ENA */
 246 #define WM8903_MIXSPKL_ENA_WIDTH                     1  /* MIXSPKL_ENA */
 247 #define WM8903_MIXSPKR_ENA                      0x0001  /* MIXSPKR_ENA */
 248 #define WM8903_MIXSPKR_ENA_MASK                 0x0001  /* MIXSPKR_ENA */
 249 #define WM8903_MIXSPKR_ENA_SHIFT                     0  /* MIXSPKR_ENA */
 250 #define WM8903_MIXSPKR_ENA_WIDTH                     1  /* MIXSPKR_ENA */
 251 
 252 /*
 253  * R17 (0x11) - Power Management 5
 254  */
 255 #define WM8903_SPKL_ENA                         0x0002  /* SPKL_ENA */
 256 #define WM8903_SPKL_ENA_MASK                    0x0002  /* SPKL_ENA */
 257 #define WM8903_SPKL_ENA_SHIFT                        1  /* SPKL_ENA */
 258 #define WM8903_SPKL_ENA_WIDTH                        1  /* SPKL_ENA */
 259 #define WM8903_SPKR_ENA                         0x0001  /* SPKR_ENA */
 260 #define WM8903_SPKR_ENA_MASK                    0x0001  /* SPKR_ENA */
 261 #define WM8903_SPKR_ENA_SHIFT                        0  /* SPKR_ENA */
 262 #define WM8903_SPKR_ENA_WIDTH                        1  /* SPKR_ENA */
 263 
 264 /*
 265  * R18 (0x12) - Power Management 6
 266  */
 267 #define WM8903_DACL_ENA                         0x0008  /* DACL_ENA */
 268 #define WM8903_DACL_ENA_MASK                    0x0008  /* DACL_ENA */
 269 #define WM8903_DACL_ENA_SHIFT                        3  /* DACL_ENA */
 270 #define WM8903_DACL_ENA_WIDTH                        1  /* DACL_ENA */
 271 #define WM8903_DACR_ENA                         0x0004  /* DACR_ENA */
 272 #define WM8903_DACR_ENA_MASK                    0x0004  /* DACR_ENA */
 273 #define WM8903_DACR_ENA_SHIFT                        2  /* DACR_ENA */
 274 #define WM8903_DACR_ENA_WIDTH                        1  /* DACR_ENA */
 275 #define WM8903_ADCL_ENA                         0x0002  /* ADCL_ENA */
 276 #define WM8903_ADCL_ENA_MASK                    0x0002  /* ADCL_ENA */
 277 #define WM8903_ADCL_ENA_SHIFT                        1  /* ADCL_ENA */
 278 #define WM8903_ADCL_ENA_WIDTH                        1  /* ADCL_ENA */
 279 #define WM8903_ADCR_ENA                         0x0001  /* ADCR_ENA */
 280 #define WM8903_ADCR_ENA_MASK                    0x0001  /* ADCR_ENA */
 281 #define WM8903_ADCR_ENA_SHIFT                        0  /* ADCR_ENA */
 282 #define WM8903_ADCR_ENA_WIDTH                        1  /* ADCR_ENA */
 283 
 284 /*
 285  * R20 (0x14) - Clock Rates 0
 286  */
 287 #define WM8903_MCLKDIV2                         0x0001  /* MCLKDIV2 */
 288 #define WM8903_MCLKDIV2_MASK                    0x0001  /* MCLKDIV2 */
 289 #define WM8903_MCLKDIV2_SHIFT                        0  /* MCLKDIV2 */
 290 #define WM8903_MCLKDIV2_WIDTH                        1  /* MCLKDIV2 */
 291 
 292 /*
 293  * R21 (0x15) - Clock Rates 1
 294  */
 295 #define WM8903_CLK_SYS_RATE_MASK                0x3C00  /* CLK_SYS_RATE - [13:10] */
 296 #define WM8903_CLK_SYS_RATE_SHIFT                   10  /* CLK_SYS_RATE - [13:10] */
 297 #define WM8903_CLK_SYS_RATE_WIDTH                    4  /* CLK_SYS_RATE - [13:10] */
 298 #define WM8903_CLK_SYS_MODE_MASK                0x0300  /* CLK_SYS_MODE - [9:8] */
 299 #define WM8903_CLK_SYS_MODE_SHIFT                    8  /* CLK_SYS_MODE - [9:8] */
 300 #define WM8903_CLK_SYS_MODE_WIDTH                    2  /* CLK_SYS_MODE - [9:8] */
 301 #define WM8903_SAMPLE_RATE_MASK                 0x000F  /* SAMPLE_RATE - [3:0] */
 302 #define WM8903_SAMPLE_RATE_SHIFT                     0  /* SAMPLE_RATE - [3:0] */
 303 #define WM8903_SAMPLE_RATE_WIDTH                     4  /* SAMPLE_RATE - [3:0] */
 304 
 305 /*
 306  * R22 (0x16) - Clock Rates 2
 307  */
 308 #define WM8903_CLK_SYS_ENA                      0x0004  /* CLK_SYS_ENA */
 309 #define WM8903_CLK_SYS_ENA_MASK                 0x0004  /* CLK_SYS_ENA */
 310 #define WM8903_CLK_SYS_ENA_SHIFT                     2  /* CLK_SYS_ENA */
 311 #define WM8903_CLK_SYS_ENA_WIDTH                     1  /* CLK_SYS_ENA */
 312 #define WM8903_CLK_DSP_ENA                      0x0002  /* CLK_DSP_ENA */
 313 #define WM8903_CLK_DSP_ENA_MASK                 0x0002  /* CLK_DSP_ENA */
 314 #define WM8903_CLK_DSP_ENA_SHIFT                     1  /* CLK_DSP_ENA */
 315 #define WM8903_CLK_DSP_ENA_WIDTH                     1  /* CLK_DSP_ENA */
 316 #define WM8903_TO_ENA                           0x0001  /* TO_ENA */
 317 #define WM8903_TO_ENA_MASK                      0x0001  /* TO_ENA */
 318 #define WM8903_TO_ENA_SHIFT                          0  /* TO_ENA */
 319 #define WM8903_TO_ENA_WIDTH                          1  /* TO_ENA */
 320 
 321 /*
 322  * R24 (0x18) - Audio Interface 0
 323  */
 324 #define WM8903_DACL_DATINV                      0x1000  /* DACL_DATINV */
 325 #define WM8903_DACL_DATINV_MASK                 0x1000  /* DACL_DATINV */
 326 #define WM8903_DACL_DATINV_SHIFT                    12  /* DACL_DATINV */
 327 #define WM8903_DACL_DATINV_WIDTH                     1  /* DACL_DATINV */
 328 #define WM8903_DACR_DATINV                      0x0800  /* DACR_DATINV */
 329 #define WM8903_DACR_DATINV_MASK                 0x0800  /* DACR_DATINV */
 330 #define WM8903_DACR_DATINV_SHIFT                    11  /* DACR_DATINV */
 331 #define WM8903_DACR_DATINV_WIDTH                     1  /* DACR_DATINV */
 332 #define WM8903_DAC_BOOST_MASK                   0x0600  /* DAC_BOOST - [10:9] */
 333 #define WM8903_DAC_BOOST_SHIFT                       9  /* DAC_BOOST - [10:9] */
 334 #define WM8903_DAC_BOOST_WIDTH                       2  /* DAC_BOOST - [10:9] */
 335 #define WM8903_LOOPBACK                         0x0100  /* LOOPBACK */
 336 #define WM8903_LOOPBACK_MASK                    0x0100  /* LOOPBACK */
 337 #define WM8903_LOOPBACK_SHIFT                        8  /* LOOPBACK */
 338 #define WM8903_LOOPBACK_WIDTH                        1  /* LOOPBACK */
 339 #define WM8903_AIFADCL_SRC                      0x0080  /* AIFADCL_SRC */
 340 #define WM8903_AIFADCL_SRC_MASK                 0x0080  /* AIFADCL_SRC */
 341 #define WM8903_AIFADCL_SRC_SHIFT                     7  /* AIFADCL_SRC */
 342 #define WM8903_AIFADCL_SRC_WIDTH                     1  /* AIFADCL_SRC */
 343 #define WM8903_AIFADCR_SRC                      0x0040  /* AIFADCR_SRC */
 344 #define WM8903_AIFADCR_SRC_MASK                 0x0040  /* AIFADCR_SRC */
 345 #define WM8903_AIFADCR_SRC_SHIFT                     6  /* AIFADCR_SRC */
 346 #define WM8903_AIFADCR_SRC_WIDTH                     1  /* AIFADCR_SRC */
 347 #define WM8903_AIFDACL_SRC                      0x0020  /* AIFDACL_SRC */
 348 #define WM8903_AIFDACL_SRC_MASK                 0x0020  /* AIFDACL_SRC */
 349 #define WM8903_AIFDACL_SRC_SHIFT                     5  /* AIFDACL_SRC */
 350 #define WM8903_AIFDACL_SRC_WIDTH                     1  /* AIFDACL_SRC */
 351 #define WM8903_AIFDACR_SRC                      0x0010  /* AIFDACR_SRC */
 352 #define WM8903_AIFDACR_SRC_MASK                 0x0010  /* AIFDACR_SRC */
 353 #define WM8903_AIFDACR_SRC_SHIFT                     4  /* AIFDACR_SRC */
 354 #define WM8903_AIFDACR_SRC_WIDTH                     1  /* AIFDACR_SRC */
 355 #define WM8903_ADC_COMP                         0x0008  /* ADC_COMP */
 356 #define WM8903_ADC_COMP_MASK                    0x0008  /* ADC_COMP */
 357 #define WM8903_ADC_COMP_SHIFT                        3  /* ADC_COMP */
 358 #define WM8903_ADC_COMP_WIDTH                        1  /* ADC_COMP */
 359 #define WM8903_ADC_COMPMODE                     0x0004  /* ADC_COMPMODE */
 360 #define WM8903_ADC_COMPMODE_MASK                0x0004  /* ADC_COMPMODE */
 361 #define WM8903_ADC_COMPMODE_SHIFT                    2  /* ADC_COMPMODE */
 362 #define WM8903_ADC_COMPMODE_WIDTH                    1  /* ADC_COMPMODE */
 363 #define WM8903_DAC_COMP                         0x0002  /* DAC_COMP */
 364 #define WM8903_DAC_COMP_MASK                    0x0002  /* DAC_COMP */
 365 #define WM8903_DAC_COMP_SHIFT                        1  /* DAC_COMP */
 366 #define WM8903_DAC_COMP_WIDTH                        1  /* DAC_COMP */
 367 #define WM8903_DAC_COMPMODE                     0x0001  /* DAC_COMPMODE */
 368 #define WM8903_DAC_COMPMODE_MASK                0x0001  /* DAC_COMPMODE */
 369 #define WM8903_DAC_COMPMODE_SHIFT                    0  /* DAC_COMPMODE */
 370 #define WM8903_DAC_COMPMODE_WIDTH                    1  /* DAC_COMPMODE */
 371 
 372 /*
 373  * R25 (0x19) - Audio Interface 1
 374  */
 375 #define WM8903_AIFDAC_TDM                       0x2000  /* AIFDAC_TDM */
 376 #define WM8903_AIFDAC_TDM_MASK                  0x2000  /* AIFDAC_TDM */
 377 #define WM8903_AIFDAC_TDM_SHIFT                     13  /* AIFDAC_TDM */
 378 #define WM8903_AIFDAC_TDM_WIDTH                      1  /* AIFDAC_TDM */
 379 #define WM8903_AIFDAC_TDM_CHAN                  0x1000  /* AIFDAC_TDM_CHAN */
 380 #define WM8903_AIFDAC_TDM_CHAN_MASK             0x1000  /* AIFDAC_TDM_CHAN */
 381 #define WM8903_AIFDAC_TDM_CHAN_SHIFT                12  /* AIFDAC_TDM_CHAN */
 382 #define WM8903_AIFDAC_TDM_CHAN_WIDTH                 1  /* AIFDAC_TDM_CHAN */
 383 #define WM8903_AIFADC_TDM                       0x0800  /* AIFADC_TDM */
 384 #define WM8903_AIFADC_TDM_MASK                  0x0800  /* AIFADC_TDM */
 385 #define WM8903_AIFADC_TDM_SHIFT                     11  /* AIFADC_TDM */
 386 #define WM8903_AIFADC_TDM_WIDTH                      1  /* AIFADC_TDM */
 387 #define WM8903_AIFADC_TDM_CHAN                  0x0400  /* AIFADC_TDM_CHAN */
 388 #define WM8903_AIFADC_TDM_CHAN_MASK             0x0400  /* AIFADC_TDM_CHAN */
 389 #define WM8903_AIFADC_TDM_CHAN_SHIFT                10  /* AIFADC_TDM_CHAN */
 390 #define WM8903_AIFADC_TDM_CHAN_WIDTH                 1  /* AIFADC_TDM_CHAN */
 391 #define WM8903_LRCLK_DIR                        0x0200  /* LRCLK_DIR */
 392 #define WM8903_LRCLK_DIR_MASK                   0x0200  /* LRCLK_DIR */
 393 #define WM8903_LRCLK_DIR_SHIFT                       9  /* LRCLK_DIR */
 394 #define WM8903_LRCLK_DIR_WIDTH                       1  /* LRCLK_DIR */
 395 #define WM8903_AIF_BCLK_INV                     0x0080  /* AIF_BCLK_INV */
 396 #define WM8903_AIF_BCLK_INV_MASK                0x0080  /* AIF_BCLK_INV */
 397 #define WM8903_AIF_BCLK_INV_SHIFT                    7  /* AIF_BCLK_INV */
 398 #define WM8903_AIF_BCLK_INV_WIDTH                    1  /* AIF_BCLK_INV */
 399 #define WM8903_BCLK_DIR                         0x0040  /* BCLK_DIR */
 400 #define WM8903_BCLK_DIR_MASK                    0x0040  /* BCLK_DIR */
 401 #define WM8903_BCLK_DIR_SHIFT                        6  /* BCLK_DIR */
 402 #define WM8903_BCLK_DIR_WIDTH                        1  /* BCLK_DIR */
 403 #define WM8903_AIF_LRCLK_INV                    0x0010  /* AIF_LRCLK_INV */
 404 #define WM8903_AIF_LRCLK_INV_MASK               0x0010  /* AIF_LRCLK_INV */
 405 #define WM8903_AIF_LRCLK_INV_SHIFT                   4  /* AIF_LRCLK_INV */
 406 #define WM8903_AIF_LRCLK_INV_WIDTH                   1  /* AIF_LRCLK_INV */
 407 #define WM8903_AIF_WL_MASK                      0x000C  /* AIF_WL - [3:2] */
 408 #define WM8903_AIF_WL_SHIFT                          2  /* AIF_WL - [3:2] */
 409 #define WM8903_AIF_WL_WIDTH                          2  /* AIF_WL - [3:2] */
 410 #define WM8903_AIF_FMT_MASK                     0x0003  /* AIF_FMT - [1:0] */
 411 #define WM8903_AIF_FMT_SHIFT                         0  /* AIF_FMT - [1:0] */
 412 #define WM8903_AIF_FMT_WIDTH                         2  /* AIF_FMT - [1:0] */
 413 
 414 /*
 415  * R26 (0x1A) - Audio Interface 2
 416  */
 417 #define WM8903_BCLK_DIV_MASK                    0x001F  /* BCLK_DIV - [4:0] */
 418 #define WM8903_BCLK_DIV_SHIFT                        0  /* BCLK_DIV - [4:0] */
 419 #define WM8903_BCLK_DIV_WIDTH                        5  /* BCLK_DIV - [4:0] */
 420 
 421 /*
 422  * R27 (0x1B) - Audio Interface 3
 423  */
 424 #define WM8903_LRCLK_RATE_MASK                  0x07FF  /* LRCLK_RATE - [10:0] */
 425 #define WM8903_LRCLK_RATE_SHIFT                      0  /* LRCLK_RATE - [10:0] */
 426 #define WM8903_LRCLK_RATE_WIDTH                     11  /* LRCLK_RATE - [10:0] */
 427 
 428 /*
 429  * R30 (0x1E) - DAC Digital Volume Left
 430  */
 431 #define WM8903_DACVU                            0x0100  /* DACVU */
 432 #define WM8903_DACVU_MASK                       0x0100  /* DACVU */
 433 #define WM8903_DACVU_SHIFT                           8  /* DACVU */
 434 #define WM8903_DACVU_WIDTH                           1  /* DACVU */
 435 #define WM8903_DACL_VOL_MASK                    0x00FF  /* DACL_VOL - [7:0] */
 436 #define WM8903_DACL_VOL_SHIFT                        0  /* DACL_VOL - [7:0] */
 437 #define WM8903_DACL_VOL_WIDTH                        8  /* DACL_VOL - [7:0] */
 438 
 439 /*
 440  * R31 (0x1F) - DAC Digital Volume Right
 441  */
 442 #define WM8903_DACVU                            0x0100  /* DACVU */
 443 #define WM8903_DACVU_MASK                       0x0100  /* DACVU */
 444 #define WM8903_DACVU_SHIFT                           8  /* DACVU */
 445 #define WM8903_DACVU_WIDTH                           1  /* DACVU */
 446 #define WM8903_DACR_VOL_MASK                    0x00FF  /* DACR_VOL - [7:0] */
 447 #define WM8903_DACR_VOL_SHIFT                        0  /* DACR_VOL - [7:0] */
 448 #define WM8903_DACR_VOL_WIDTH                        8  /* DACR_VOL - [7:0] */
 449 
 450 /*
 451  * R32 (0x20) - DAC Digital 0
 452  */
 453 #define WM8903_ADCL_DAC_SVOL_MASK               0x0F00  /* ADCL_DAC_SVOL - [11:8] */
 454 #define WM8903_ADCL_DAC_SVOL_SHIFT                   8  /* ADCL_DAC_SVOL - [11:8] */
 455 #define WM8903_ADCL_DAC_SVOL_WIDTH                   4  /* ADCL_DAC_SVOL - [11:8] */
 456 #define WM8903_ADCR_DAC_SVOL_MASK               0x00F0  /* ADCR_DAC_SVOL - [7:4] */
 457 #define WM8903_ADCR_DAC_SVOL_SHIFT                   4  /* ADCR_DAC_SVOL - [7:4] */
 458 #define WM8903_ADCR_DAC_SVOL_WIDTH                   4  /* ADCR_DAC_SVOL - [7:4] */
 459 #define WM8903_ADC_TO_DACL_MASK                 0x000C  /* ADC_TO_DACL - [3:2] */
 460 #define WM8903_ADC_TO_DACL_SHIFT                     2  /* ADC_TO_DACL - [3:2] */
 461 #define WM8903_ADC_TO_DACL_WIDTH                     2  /* ADC_TO_DACL - [3:2] */
 462 #define WM8903_ADC_TO_DACR_MASK                 0x0003  /* ADC_TO_DACR - [1:0] */
 463 #define WM8903_ADC_TO_DACR_SHIFT                     0  /* ADC_TO_DACR - [1:0] */
 464 #define WM8903_ADC_TO_DACR_WIDTH                     2  /* ADC_TO_DACR - [1:0] */
 465 
 466 /*
 467  * R33 (0x21) - DAC Digital 1
 468  */
 469 #define WM8903_DAC_MONO                         0x1000  /* DAC_MONO */
 470 #define WM8903_DAC_MONO_MASK                    0x1000  /* DAC_MONO */
 471 #define WM8903_DAC_MONO_SHIFT                       12  /* DAC_MONO */
 472 #define WM8903_DAC_MONO_WIDTH                        1  /* DAC_MONO */
 473 #define WM8903_DAC_SB_FILT                      0x0800  /* DAC_SB_FILT */
 474 #define WM8903_DAC_SB_FILT_MASK                 0x0800  /* DAC_SB_FILT */
 475 #define WM8903_DAC_SB_FILT_SHIFT                    11  /* DAC_SB_FILT */
 476 #define WM8903_DAC_SB_FILT_WIDTH                     1  /* DAC_SB_FILT */
 477 #define WM8903_DAC_MUTERATE                     0x0400  /* DAC_MUTERATE */
 478 #define WM8903_DAC_MUTERATE_MASK                0x0400  /* DAC_MUTERATE */
 479 #define WM8903_DAC_MUTERATE_SHIFT                   10  /* DAC_MUTERATE */
 480 #define WM8903_DAC_MUTERATE_WIDTH                    1  /* DAC_MUTERATE */
 481 #define WM8903_DAC_MUTEMODE                     0x0200  /* DAC_MUTEMODE */
 482 #define WM8903_DAC_MUTEMODE_MASK                0x0200  /* DAC_MUTEMODE */
 483 #define WM8903_DAC_MUTEMODE_SHIFT                    9  /* DAC_MUTEMODE */
 484 #define WM8903_DAC_MUTEMODE_WIDTH                    1  /* DAC_MUTEMODE */
 485 #define WM8903_DAC_MUTE                         0x0008  /* DAC_MUTE */
 486 #define WM8903_DAC_MUTE_MASK                    0x0008  /* DAC_MUTE */
 487 #define WM8903_DAC_MUTE_SHIFT                        3  /* DAC_MUTE */
 488 #define WM8903_DAC_MUTE_WIDTH                        1  /* DAC_MUTE */
 489 #define WM8903_DEEMPH_MASK                      0x0006  /* DEEMPH - [2:1] */
 490 #define WM8903_DEEMPH_SHIFT                          1  /* DEEMPH - [2:1] */
 491 #define WM8903_DEEMPH_WIDTH                          2  /* DEEMPH - [2:1] */
 492 
 493 /*
 494  * R36 (0x24) - ADC Digital Volume Left
 495  */
 496 #define WM8903_ADCVU                            0x0100  /* ADCVU */
 497 #define WM8903_ADCVU_MASK                       0x0100  /* ADCVU */
 498 #define WM8903_ADCVU_SHIFT                           8  /* ADCVU */
 499 #define WM8903_ADCVU_WIDTH                           1  /* ADCVU */
 500 #define WM8903_ADCL_VOL_MASK                    0x00FF  /* ADCL_VOL - [7:0] */
 501 #define WM8903_ADCL_VOL_SHIFT                        0  /* ADCL_VOL - [7:0] */
 502 #define WM8903_ADCL_VOL_WIDTH                        8  /* ADCL_VOL - [7:0] */
 503 
 504 /*
 505  * R37 (0x25) - ADC Digital Volume Right
 506  */
 507 #define WM8903_ADCVU                            0x0100  /* ADCVU */
 508 #define WM8903_ADCVU_MASK                       0x0100  /* ADCVU */
 509 #define WM8903_ADCVU_SHIFT                           8  /* ADCVU */
 510 #define WM8903_ADCVU_WIDTH                           1  /* ADCVU */
 511 #define WM8903_ADCR_VOL_MASK                    0x00FF  /* ADCR_VOL - [7:0] */
 512 #define WM8903_ADCR_VOL_SHIFT                        0  /* ADCR_VOL - [7:0] */
 513 #define WM8903_ADCR_VOL_WIDTH                        8  /* ADCR_VOL - [7:0] */
 514 
 515 /*
 516  * R38 (0x26) - ADC Digital 0
 517  */
 518 #define WM8903_ADC_HPF_CUT_MASK                 0x0060  /* ADC_HPF_CUT - [6:5] */
 519 #define WM8903_ADC_HPF_CUT_SHIFT                     5  /* ADC_HPF_CUT - [6:5] */
 520 #define WM8903_ADC_HPF_CUT_WIDTH                     2  /* ADC_HPF_CUT - [6:5] */
 521 #define WM8903_ADC_HPF_ENA                      0x0010  /* ADC_HPF_ENA */
 522 #define WM8903_ADC_HPF_ENA_MASK                 0x0010  /* ADC_HPF_ENA */
 523 #define WM8903_ADC_HPF_ENA_SHIFT                     4  /* ADC_HPF_ENA */
 524 #define WM8903_ADC_HPF_ENA_WIDTH                     1  /* ADC_HPF_ENA */
 525 #define WM8903_ADCL_DATINV                      0x0002  /* ADCL_DATINV */
 526 #define WM8903_ADCL_DATINV_MASK                 0x0002  /* ADCL_DATINV */
 527 #define WM8903_ADCL_DATINV_SHIFT                     1  /* ADCL_DATINV */
 528 #define WM8903_ADCL_DATINV_WIDTH                     1  /* ADCL_DATINV */
 529 #define WM8903_ADCR_DATINV                      0x0001  /* ADCR_DATINV */
 530 #define WM8903_ADCR_DATINV_MASK                 0x0001  /* ADCR_DATINV */
 531 #define WM8903_ADCR_DATINV_SHIFT                     0  /* ADCR_DATINV */
 532 #define WM8903_ADCR_DATINV_WIDTH                     1  /* ADCR_DATINV */
 533 
 534 /*
 535  * R39 (0x27) - Digital Microphone 0
 536  */
 537 #define WM8903_DIGMIC_MODE_SEL                  0x0100  /* DIGMIC_MODE_SEL */
 538 #define WM8903_DIGMIC_MODE_SEL_MASK             0x0100  /* DIGMIC_MODE_SEL */
 539 #define WM8903_DIGMIC_MODE_SEL_SHIFT                 8  /* DIGMIC_MODE_SEL */
 540 #define WM8903_DIGMIC_MODE_SEL_WIDTH                 1  /* DIGMIC_MODE_SEL */
 541 #define WM8903_DIGMIC_CLK_SEL_L_MASK            0x00C0  /* DIGMIC_CLK_SEL_L - [7:6] */
 542 #define WM8903_DIGMIC_CLK_SEL_L_SHIFT                6  /* DIGMIC_CLK_SEL_L - [7:6] */
 543 #define WM8903_DIGMIC_CLK_SEL_L_WIDTH                2  /* DIGMIC_CLK_SEL_L - [7:6] */
 544 #define WM8903_DIGMIC_CLK_SEL_R_MASK            0x0030  /* DIGMIC_CLK_SEL_R - [5:4] */
 545 #define WM8903_DIGMIC_CLK_SEL_R_SHIFT                4  /* DIGMIC_CLK_SEL_R - [5:4] */
 546 #define WM8903_DIGMIC_CLK_SEL_R_WIDTH                2  /* DIGMIC_CLK_SEL_R - [5:4] */
 547 #define WM8903_DIGMIC_CLK_SEL_RT_MASK           0x000C  /* DIGMIC_CLK_SEL_RT - [3:2] */
 548 #define WM8903_DIGMIC_CLK_SEL_RT_SHIFT               2  /* DIGMIC_CLK_SEL_RT - [3:2] */
 549 #define WM8903_DIGMIC_CLK_SEL_RT_WIDTH               2  /* DIGMIC_CLK_SEL_RT - [3:2] */
 550 #define WM8903_DIGMIC_CLK_SEL_MASK              0x0003  /* DIGMIC_CLK_SEL - [1:0] */
 551 #define WM8903_DIGMIC_CLK_SEL_SHIFT                  0  /* DIGMIC_CLK_SEL - [1:0] */
 552 #define WM8903_DIGMIC_CLK_SEL_WIDTH                  2  /* DIGMIC_CLK_SEL - [1:0] */
 553 
 554 /*
 555  * R40 (0x28) - DRC 0
 556  */
 557 #define WM8903_DRC_ENA                          0x8000  /* DRC_ENA */
 558 #define WM8903_DRC_ENA_MASK                     0x8000  /* DRC_ENA */
 559 #define WM8903_DRC_ENA_SHIFT                        15  /* DRC_ENA */
 560 #define WM8903_DRC_ENA_WIDTH                         1  /* DRC_ENA */
 561 #define WM8903_DRC_THRESH_HYST_MASK             0x1800  /* DRC_THRESH_HYST - [12:11] */
 562 #define WM8903_DRC_THRESH_HYST_SHIFT                11  /* DRC_THRESH_HYST - [12:11] */
 563 #define WM8903_DRC_THRESH_HYST_WIDTH                 2  /* DRC_THRESH_HYST - [12:11] */
 564 #define WM8903_DRC_STARTUP_GAIN_MASK            0x07C0  /* DRC_STARTUP_GAIN - [10:6] */
 565 #define WM8903_DRC_STARTUP_GAIN_SHIFT                6  /* DRC_STARTUP_GAIN - [10:6] */
 566 #define WM8903_DRC_STARTUP_GAIN_WIDTH                5  /* DRC_STARTUP_GAIN - [10:6] */
 567 #define WM8903_DRC_FF_DELAY                     0x0020  /* DRC_FF_DELAY */
 568 #define WM8903_DRC_FF_DELAY_MASK                0x0020  /* DRC_FF_DELAY */
 569 #define WM8903_DRC_FF_DELAY_SHIFT                    5  /* DRC_FF_DELAY */
 570 #define WM8903_DRC_FF_DELAY_WIDTH                    1  /* DRC_FF_DELAY */
 571 #define WM8903_DRC_SMOOTH_ENA                   0x0008  /* DRC_SMOOTH_ENA */
 572 #define WM8903_DRC_SMOOTH_ENA_MASK              0x0008  /* DRC_SMOOTH_ENA */
 573 #define WM8903_DRC_SMOOTH_ENA_SHIFT                  3  /* DRC_SMOOTH_ENA */
 574 #define WM8903_DRC_SMOOTH_ENA_WIDTH                  1  /* DRC_SMOOTH_ENA */
 575 #define WM8903_DRC_QR_ENA                       0x0004  /* DRC_QR_ENA */
 576 #define WM8903_DRC_QR_ENA_MASK                  0x0004  /* DRC_QR_ENA */
 577 #define WM8903_DRC_QR_ENA_SHIFT                      2  /* DRC_QR_ENA */
 578 #define WM8903_DRC_QR_ENA_WIDTH                      1  /* DRC_QR_ENA */
 579 #define WM8903_DRC_ANTICLIP_ENA                 0x0002  /* DRC_ANTICLIP_ENA */
 580 #define WM8903_DRC_ANTICLIP_ENA_MASK            0x0002  /* DRC_ANTICLIP_ENA */
 581 #define WM8903_DRC_ANTICLIP_ENA_SHIFT                1  /* DRC_ANTICLIP_ENA */
 582 #define WM8903_DRC_ANTICLIP_ENA_WIDTH                1  /* DRC_ANTICLIP_ENA */
 583 #define WM8903_DRC_HYST_ENA                     0x0001  /* DRC_HYST_ENA */
 584 #define WM8903_DRC_HYST_ENA_MASK                0x0001  /* DRC_HYST_ENA */
 585 #define WM8903_DRC_HYST_ENA_SHIFT                    0  /* DRC_HYST_ENA */
 586 #define WM8903_DRC_HYST_ENA_WIDTH                    1  /* DRC_HYST_ENA */
 587 
 588 /*
 589  * R41 (0x29) - DRC 1
 590  */
 591 #define WM8903_DRC_ATTACK_RATE_MASK             0xF000  /* DRC_ATTACK_RATE - [15:12] */
 592 #define WM8903_DRC_ATTACK_RATE_SHIFT                12  /* DRC_ATTACK_RATE - [15:12] */
 593 #define WM8903_DRC_ATTACK_RATE_WIDTH                 4  /* DRC_ATTACK_RATE - [15:12] */
 594 #define WM8903_DRC_DECAY_RATE_MASK              0x0F00  /* DRC_DECAY_RATE - [11:8] */
 595 #define WM8903_DRC_DECAY_RATE_SHIFT                  8  /* DRC_DECAY_RATE - [11:8] */
 596 #define WM8903_DRC_DECAY_RATE_WIDTH                  4  /* DRC_DECAY_RATE - [11:8] */
 597 #define WM8903_DRC_THRESH_QR_MASK               0x00C0  /* DRC_THRESH_QR - [7:6] */
 598 #define WM8903_DRC_THRESH_QR_SHIFT                   6  /* DRC_THRESH_QR - [7:6] */
 599 #define WM8903_DRC_THRESH_QR_WIDTH                   2  /* DRC_THRESH_QR - [7:6] */
 600 #define WM8903_DRC_RATE_QR_MASK                 0x0030  /* DRC_RATE_QR - [5:4] */
 601 #define WM8903_DRC_RATE_QR_SHIFT                     4  /* DRC_RATE_QR - [5:4] */
 602 #define WM8903_DRC_RATE_QR_WIDTH                     2  /* DRC_RATE_QR - [5:4] */
 603 #define WM8903_DRC_MINGAIN_MASK                 0x000C  /* DRC_MINGAIN - [3:2] */
 604 #define WM8903_DRC_MINGAIN_SHIFT                     2  /* DRC_MINGAIN - [3:2] */
 605 #define WM8903_DRC_MINGAIN_WIDTH                     2  /* DRC_MINGAIN - [3:2] */
 606 #define WM8903_DRC_MAXGAIN_MASK                 0x0003  /* DRC_MAXGAIN - [1:0] */
 607 #define WM8903_DRC_MAXGAIN_SHIFT                     0  /* DRC_MAXGAIN - [1:0] */
 608 #define WM8903_DRC_MAXGAIN_WIDTH                     2  /* DRC_MAXGAIN - [1:0] */
 609 
 610 /*
 611  * R42 (0x2A) - DRC 2
 612  */
 613 #define WM8903_DRC_R0_SLOPE_COMP_MASK           0x0038  /* DRC_R0_SLOPE_COMP - [5:3] */
 614 #define WM8903_DRC_R0_SLOPE_COMP_SHIFT               3  /* DRC_R0_SLOPE_COMP - [5:3] */
 615 #define WM8903_DRC_R0_SLOPE_COMP_WIDTH               3  /* DRC_R0_SLOPE_COMP - [5:3] */
 616 #define WM8903_DRC_R1_SLOPE_COMP_MASK           0x0007  /* DRC_R1_SLOPE_COMP - [2:0] */
 617 #define WM8903_DRC_R1_SLOPE_COMP_SHIFT               0  /* DRC_R1_SLOPE_COMP - [2:0] */
 618 #define WM8903_DRC_R1_SLOPE_COMP_WIDTH               3  /* DRC_R1_SLOPE_COMP - [2:0] */
 619 
 620 /*
 621  * R43 (0x2B) - DRC 3
 622  */
 623 #define WM8903_DRC_THRESH_COMP_MASK             0x07E0  /* DRC_THRESH_COMP - [10:5] */
 624 #define WM8903_DRC_THRESH_COMP_SHIFT                 5  /* DRC_THRESH_COMP - [10:5] */
 625 #define WM8903_DRC_THRESH_COMP_WIDTH                 6  /* DRC_THRESH_COMP - [10:5] */
 626 #define WM8903_DRC_AMP_COMP_MASK                0x001F  /* DRC_AMP_COMP - [4:0] */
 627 #define WM8903_DRC_AMP_COMP_SHIFT                    0  /* DRC_AMP_COMP - [4:0] */
 628 #define WM8903_DRC_AMP_COMP_WIDTH                    5  /* DRC_AMP_COMP - [4:0] */
 629 
 630 /*
 631  * R44 (0x2C) - Analogue Left Input 0
 632  */
 633 #define WM8903_LINMUTE                          0x0080  /* LINMUTE */
 634 #define WM8903_LINMUTE_MASK                     0x0080  /* LINMUTE */
 635 #define WM8903_LINMUTE_SHIFT                         7  /* LINMUTE */
 636 #define WM8903_LINMUTE_WIDTH                         1  /* LINMUTE */
 637 #define WM8903_LIN_VOL_MASK                     0x001F  /* LIN_VOL - [4:0] */
 638 #define WM8903_LIN_VOL_SHIFT                         0  /* LIN_VOL - [4:0] */
 639 #define WM8903_LIN_VOL_WIDTH                         5  /* LIN_VOL - [4:0] */
 640 
 641 /*
 642  * R45 (0x2D) - Analogue Right Input 0
 643  */
 644 #define WM8903_RINMUTE                          0x0080  /* RINMUTE */
 645 #define WM8903_RINMUTE_MASK                     0x0080  /* RINMUTE */
 646 #define WM8903_RINMUTE_SHIFT                         7  /* RINMUTE */
 647 #define WM8903_RINMUTE_WIDTH                         1  /* RINMUTE */
 648 #define WM8903_RIN_VOL_MASK                     0x001F  /* RIN_VOL - [4:0] */
 649 #define WM8903_RIN_VOL_SHIFT                         0  /* RIN_VOL - [4:0] */
 650 #define WM8903_RIN_VOL_WIDTH                         5  /* RIN_VOL - [4:0] */
 651 
 652 /*
 653  * R46 (0x2E) - Analogue Left Input 1
 654  */
 655 #define WM8903_INL_CM_ENA                       0x0040  /* INL_CM_ENA */
 656 #define WM8903_INL_CM_ENA_MASK                  0x0040  /* INL_CM_ENA */
 657 #define WM8903_INL_CM_ENA_SHIFT                      6  /* INL_CM_ENA */
 658 #define WM8903_INL_CM_ENA_WIDTH                      1  /* INL_CM_ENA */
 659 #define WM8903_L_IP_SEL_N_MASK                  0x0030  /* L_IP_SEL_N - [5:4] */
 660 #define WM8903_L_IP_SEL_N_SHIFT                      4  /* L_IP_SEL_N - [5:4] */
 661 #define WM8903_L_IP_SEL_N_WIDTH                      2  /* L_IP_SEL_N - [5:4] */
 662 #define WM8903_L_IP_SEL_P_MASK                  0x000C  /* L_IP_SEL_P - [3:2] */
 663 #define WM8903_L_IP_SEL_P_SHIFT                      2  /* L_IP_SEL_P - [3:2] */
 664 #define WM8903_L_IP_SEL_P_WIDTH                      2  /* L_IP_SEL_P - [3:2] */
 665 #define WM8903_L_MODE_MASK                      0x0003  /* L_MODE - [1:0] */
 666 #define WM8903_L_MODE_SHIFT                          0  /* L_MODE - [1:0] */
 667 #define WM8903_L_MODE_WIDTH                          2  /* L_MODE - [1:0] */
 668 
 669 /*
 670  * R47 (0x2F) - Analogue Right Input 1
 671  */
 672 #define WM8903_INR_CM_ENA                       0x0040  /* INR_CM_ENA */
 673 #define WM8903_INR_CM_ENA_MASK                  0x0040  /* INR_CM_ENA */
 674 #define WM8903_INR_CM_ENA_SHIFT                      6  /* INR_CM_ENA */
 675 #define WM8903_INR_CM_ENA_WIDTH                      1  /* INR_CM_ENA */
 676 #define WM8903_R_IP_SEL_N_MASK                  0x0030  /* R_IP_SEL_N - [5:4] */
 677 #define WM8903_R_IP_SEL_N_SHIFT                      4  /* R_IP_SEL_N - [5:4] */
 678 #define WM8903_R_IP_SEL_N_WIDTH                      2  /* R_IP_SEL_N - [5:4] */
 679 #define WM8903_R_IP_SEL_P_MASK                  0x000C  /* R_IP_SEL_P - [3:2] */
 680 #define WM8903_R_IP_SEL_P_SHIFT                      2  /* R_IP_SEL_P - [3:2] */
 681 #define WM8903_R_IP_SEL_P_WIDTH                      2  /* R_IP_SEL_P - [3:2] */
 682 #define WM8903_R_MODE_MASK                      0x0003  /* R_MODE - [1:0] */
 683 #define WM8903_R_MODE_SHIFT                          0  /* R_MODE - [1:0] */
 684 #define WM8903_R_MODE_WIDTH                          2  /* R_MODE - [1:0] */
 685 
 686 /*
 687  * R50 (0x32) - Analogue Left Mix 0
 688  */
 689 #define WM8903_DACL_TO_MIXOUTL                  0x0008  /* DACL_TO_MIXOUTL */
 690 #define WM8903_DACL_TO_MIXOUTL_MASK             0x0008  /* DACL_TO_MIXOUTL */
 691 #define WM8903_DACL_TO_MIXOUTL_SHIFT                 3  /* DACL_TO_MIXOUTL */
 692 #define WM8903_DACL_TO_MIXOUTL_WIDTH                 1  /* DACL_TO_MIXOUTL */
 693 #define WM8903_DACR_TO_MIXOUTL                  0x0004  /* DACR_TO_MIXOUTL */
 694 #define WM8903_DACR_TO_MIXOUTL_MASK             0x0004  /* DACR_TO_MIXOUTL */
 695 #define WM8903_DACR_TO_MIXOUTL_SHIFT                 2  /* DACR_TO_MIXOUTL */
 696 #define WM8903_DACR_TO_MIXOUTL_WIDTH                 1  /* DACR_TO_MIXOUTL */
 697 #define WM8903_BYPASSL_TO_MIXOUTL               0x0002  /* BYPASSL_TO_MIXOUTL */
 698 #define WM8903_BYPASSL_TO_MIXOUTL_MASK          0x0002  /* BYPASSL_TO_MIXOUTL */
 699 #define WM8903_BYPASSL_TO_MIXOUTL_SHIFT              1  /* BYPASSL_TO_MIXOUTL */
 700 #define WM8903_BYPASSL_TO_MIXOUTL_WIDTH              1  /* BYPASSL_TO_MIXOUTL */
 701 #define WM8903_BYPASSR_TO_MIXOUTL               0x0001  /* BYPASSR_TO_MIXOUTL */
 702 #define WM8903_BYPASSR_TO_MIXOUTL_MASK          0x0001  /* BYPASSR_TO_MIXOUTL */
 703 #define WM8903_BYPASSR_TO_MIXOUTL_SHIFT              0  /* BYPASSR_TO_MIXOUTL */
 704 #define WM8903_BYPASSR_TO_MIXOUTL_WIDTH              1  /* BYPASSR_TO_MIXOUTL */
 705 
 706 /*
 707  * R51 (0x33) - Analogue Right Mix 0
 708  */
 709 #define WM8903_DACL_TO_MIXOUTR                  0x0008  /* DACL_TO_MIXOUTR */
 710 #define WM8903_DACL_TO_MIXOUTR_MASK             0x0008  /* DACL_TO_MIXOUTR */
 711 #define WM8903_DACL_TO_MIXOUTR_SHIFT                 3  /* DACL_TO_MIXOUTR */
 712 #define WM8903_DACL_TO_MIXOUTR_WIDTH                 1  /* DACL_TO_MIXOUTR */
 713 #define WM8903_DACR_TO_MIXOUTR                  0x0004  /* DACR_TO_MIXOUTR */
 714 #define WM8903_DACR_TO_MIXOUTR_MASK             0x0004  /* DACR_TO_MIXOUTR */
 715 #define WM8903_DACR_TO_MIXOUTR_SHIFT                 2  /* DACR_TO_MIXOUTR */
 716 #define WM8903_DACR_TO_MIXOUTR_WIDTH                 1  /* DACR_TO_MIXOUTR */
 717 #define WM8903_BYPASSL_TO_MIXOUTR               0x0002  /* BYPASSL_TO_MIXOUTR */
 718 #define WM8903_BYPASSL_TO_MIXOUTR_MASK          0x0002  /* BYPASSL_TO_MIXOUTR */
 719 #define WM8903_BYPASSL_TO_MIXOUTR_SHIFT              1  /* BYPASSL_TO_MIXOUTR */
 720 #define WM8903_BYPASSL_TO_MIXOUTR_WIDTH              1  /* BYPASSL_TO_MIXOUTR */
 721 #define WM8903_BYPASSR_TO_MIXOUTR               0x0001  /* BYPASSR_TO_MIXOUTR */
 722 #define WM8903_BYPASSR_TO_MIXOUTR_MASK          0x0001  /* BYPASSR_TO_MIXOUTR */
 723 #define WM8903_BYPASSR_TO_MIXOUTR_SHIFT              0  /* BYPASSR_TO_MIXOUTR */
 724 #define WM8903_BYPASSR_TO_MIXOUTR_WIDTH              1  /* BYPASSR_TO_MIXOUTR */
 725 
 726 /*
 727  * R52 (0x34) - Analogue Spk Mix Left 0
 728  */
 729 #define WM8903_DACL_TO_MIXSPKL                  0x0008  /* DACL_TO_MIXSPKL */
 730 #define WM8903_DACL_TO_MIXSPKL_MASK             0x0008  /* DACL_TO_MIXSPKL */
 731 #define WM8903_DACL_TO_MIXSPKL_SHIFT                 3  /* DACL_TO_MIXSPKL */
 732 #define WM8903_DACL_TO_MIXSPKL_WIDTH                 1  /* DACL_TO_MIXSPKL */
 733 #define WM8903_DACR_TO_MIXSPKL                  0x0004  /* DACR_TO_MIXSPKL */
 734 #define WM8903_DACR_TO_MIXSPKL_MASK             0x0004  /* DACR_TO_MIXSPKL */
 735 #define WM8903_DACR_TO_MIXSPKL_SHIFT                 2  /* DACR_TO_MIXSPKL */
 736 #define WM8903_DACR_TO_MIXSPKL_WIDTH                 1  /* DACR_TO_MIXSPKL */
 737 #define WM8903_BYPASSL_TO_MIXSPKL               0x0002  /* BYPASSL_TO_MIXSPKL */
 738 #define WM8903_BYPASSL_TO_MIXSPKL_MASK          0x0002  /* BYPASSL_TO_MIXSPKL */
 739 #define WM8903_BYPASSL_TO_MIXSPKL_SHIFT              1  /* BYPASSL_TO_MIXSPKL */
 740 #define WM8903_BYPASSL_TO_MIXSPKL_WIDTH              1  /* BYPASSL_TO_MIXSPKL */
 741 #define WM8903_BYPASSR_TO_MIXSPKL               0x0001  /* BYPASSR_TO_MIXSPKL */
 742 #define WM8903_BYPASSR_TO_MIXSPKL_MASK          0x0001  /* BYPASSR_TO_MIXSPKL */
 743 #define WM8903_BYPASSR_TO_MIXSPKL_SHIFT              0  /* BYPASSR_TO_MIXSPKL */
 744 #define WM8903_BYPASSR_TO_MIXSPKL_WIDTH              1  /* BYPASSR_TO_MIXSPKL */
 745 
 746 /*
 747  * R53 (0x35) - Analogue Spk Mix Left 1
 748  */
 749 #define WM8903_DACL_MIXSPKL_VOL                 0x0008  /* DACL_MIXSPKL_VOL */
 750 #define WM8903_DACL_MIXSPKL_VOL_MASK            0x0008  /* DACL_MIXSPKL_VOL */
 751 #define WM8903_DACL_MIXSPKL_VOL_SHIFT                3  /* DACL_MIXSPKL_VOL */
 752 #define WM8903_DACL_MIXSPKL_VOL_WIDTH                1  /* DACL_MIXSPKL_VOL */
 753 #define WM8903_DACR_MIXSPKL_VOL                 0x0004  /* DACR_MIXSPKL_VOL */
 754 #define WM8903_DACR_MIXSPKL_VOL_MASK            0x0004  /* DACR_MIXSPKL_VOL */
 755 #define WM8903_DACR_MIXSPKL_VOL_SHIFT                2  /* DACR_MIXSPKL_VOL */
 756 #define WM8903_DACR_MIXSPKL_VOL_WIDTH                1  /* DACR_MIXSPKL_VOL */
 757 #define WM8903_BYPASSL_MIXSPKL_VOL              0x0002  /* BYPASSL_MIXSPKL_VOL */
 758 #define WM8903_BYPASSL_MIXSPKL_VOL_MASK         0x0002  /* BYPASSL_MIXSPKL_VOL */
 759 #define WM8903_BYPASSL_MIXSPKL_VOL_SHIFT             1  /* BYPASSL_MIXSPKL_VOL */
 760 #define WM8903_BYPASSL_MIXSPKL_VOL_WIDTH             1  /* BYPASSL_MIXSPKL_VOL */
 761 #define WM8903_BYPASSR_MIXSPKL_VOL              0x0001  /* BYPASSR_MIXSPKL_VOL */
 762 #define WM8903_BYPASSR_MIXSPKL_VOL_MASK         0x0001  /* BYPASSR_MIXSPKL_VOL */
 763 #define WM8903_BYPASSR_MIXSPKL_VOL_SHIFT             0  /* BYPASSR_MIXSPKL_VOL */
 764 #define WM8903_BYPASSR_MIXSPKL_VOL_WIDTH             1  /* BYPASSR_MIXSPKL_VOL */
 765 
 766 /*
 767  * R54 (0x36) - Analogue Spk Mix Right 0
 768  */
 769 #define WM8903_DACL_TO_MIXSPKR                  0x0008  /* DACL_TO_MIXSPKR */
 770 #define WM8903_DACL_TO_MIXSPKR_MASK             0x0008  /* DACL_TO_MIXSPKR */
 771 #define WM8903_DACL_TO_MIXSPKR_SHIFT                 3  /* DACL_TO_MIXSPKR */
 772 #define WM8903_DACL_TO_MIXSPKR_WIDTH                 1  /* DACL_TO_MIXSPKR */
 773 #define WM8903_DACR_TO_MIXSPKR                  0x0004  /* DACR_TO_MIXSPKR */
 774 #define WM8903_DACR_TO_MIXSPKR_MASK             0x0004  /* DACR_TO_MIXSPKR */
 775 #define WM8903_DACR_TO_MIXSPKR_SHIFT                 2  /* DACR_TO_MIXSPKR */
 776 #define WM8903_DACR_TO_MIXSPKR_WIDTH                 1  /* DACR_TO_MIXSPKR */
 777 #define WM8903_BYPASSL_TO_MIXSPKR               0x0002  /* BYPASSL_TO_MIXSPKR */
 778 #define WM8903_BYPASSL_TO_MIXSPKR_MASK          0x0002  /* BYPASSL_TO_MIXSPKR */
 779 #define WM8903_BYPASSL_TO_MIXSPKR_SHIFT              1  /* BYPASSL_TO_MIXSPKR */
 780 #define WM8903_BYPASSL_TO_MIXSPKR_WIDTH              1  /* BYPASSL_TO_MIXSPKR */
 781 #define WM8903_BYPASSR_TO_MIXSPKR               0x0001  /* BYPASSR_TO_MIXSPKR */
 782 #define WM8903_BYPASSR_TO_MIXSPKR_MASK          0x0001  /* BYPASSR_TO_MIXSPKR */
 783 #define WM8903_BYPASSR_TO_MIXSPKR_SHIFT              0  /* BYPASSR_TO_MIXSPKR */
 784 #define WM8903_BYPASSR_TO_MIXSPKR_WIDTH              1  /* BYPASSR_TO_MIXSPKR */
 785 
 786 /*
 787  * R55 (0x37) - Analogue Spk Mix Right 1
 788  */
 789 #define WM8903_DACL_MIXSPKR_VOL                 0x0008  /* DACL_MIXSPKR_VOL */
 790 #define WM8903_DACL_MIXSPKR_VOL_MASK            0x0008  /* DACL_MIXSPKR_VOL */
 791 #define WM8903_DACL_MIXSPKR_VOL_SHIFT                3  /* DACL_MIXSPKR_VOL */
 792 #define WM8903_DACL_MIXSPKR_VOL_WIDTH                1  /* DACL_MIXSPKR_VOL */
 793 #define WM8903_DACR_MIXSPKR_VOL                 0x0004  /* DACR_MIXSPKR_VOL */
 794 #define WM8903_DACR_MIXSPKR_VOL_MASK            0x0004  /* DACR_MIXSPKR_VOL */
 795 #define WM8903_DACR_MIXSPKR_VOL_SHIFT                2  /* DACR_MIXSPKR_VOL */
 796 #define WM8903_DACR_MIXSPKR_VOL_WIDTH                1  /* DACR_MIXSPKR_VOL */
 797 #define WM8903_BYPASSL_MIXSPKR_VOL              0x0002  /* BYPASSL_MIXSPKR_VOL */
 798 #define WM8903_BYPASSL_MIXSPKR_VOL_MASK         0x0002  /* BYPASSL_MIXSPKR_VOL */
 799 #define WM8903_BYPASSL_MIXSPKR_VOL_SHIFT             1  /* BYPASSL_MIXSPKR_VOL */
 800 #define WM8903_BYPASSL_MIXSPKR_VOL_WIDTH             1  /* BYPASSL_MIXSPKR_VOL */
 801 #define WM8903_BYPASSR_MIXSPKR_VOL              0x0001  /* BYPASSR_MIXSPKR_VOL */
 802 #define WM8903_BYPASSR_MIXSPKR_VOL_MASK         0x0001  /* BYPASSR_MIXSPKR_VOL */
 803 #define WM8903_BYPASSR_MIXSPKR_VOL_SHIFT             0  /* BYPASSR_MIXSPKR_VOL */
 804 #define WM8903_BYPASSR_MIXSPKR_VOL_WIDTH             1  /* BYPASSR_MIXSPKR_VOL */
 805 
 806 /*
 807  * R57 (0x39) - Analogue OUT1 Left
 808  */
 809 #define WM8903_HPL_MUTE                         0x0100  /* HPL_MUTE */
 810 #define WM8903_HPL_MUTE_MASK                    0x0100  /* HPL_MUTE */
 811 #define WM8903_HPL_MUTE_SHIFT                        8  /* HPL_MUTE */
 812 #define WM8903_HPL_MUTE_WIDTH                        1  /* HPL_MUTE */
 813 #define WM8903_HPOUTVU                          0x0080  /* HPOUTVU */
 814 #define WM8903_HPOUTVU_MASK                     0x0080  /* HPOUTVU */
 815 #define WM8903_HPOUTVU_SHIFT                         7  /* HPOUTVU */
 816 #define WM8903_HPOUTVU_WIDTH                         1  /* HPOUTVU */
 817 #define WM8903_HPOUTLZC                         0x0040  /* HPOUTLZC */
 818 #define WM8903_HPOUTLZC_MASK                    0x0040  /* HPOUTLZC */
 819 #define WM8903_HPOUTLZC_SHIFT                        6  /* HPOUTLZC */
 820 #define WM8903_HPOUTLZC_WIDTH                        1  /* HPOUTLZC */
 821 #define WM8903_HPOUTL_VOL_MASK                  0x003F  /* HPOUTL_VOL - [5:0] */
 822 #define WM8903_HPOUTL_VOL_SHIFT                      0  /* HPOUTL_VOL - [5:0] */
 823 #define WM8903_HPOUTL_VOL_WIDTH                      6  /* HPOUTL_VOL - [5:0] */
 824 
 825 /*
 826  * R58 (0x3A) - Analogue OUT1 Right
 827  */
 828 #define WM8903_HPR_MUTE                         0x0100  /* HPR_MUTE */
 829 #define WM8903_HPR_MUTE_MASK                    0x0100  /* HPR_MUTE */
 830 #define WM8903_HPR_MUTE_SHIFT                        8  /* HPR_MUTE */
 831 #define WM8903_HPR_MUTE_WIDTH                        1  /* HPR_MUTE */
 832 #define WM8903_HPOUTVU                          0x0080  /* HPOUTVU */
 833 #define WM8903_HPOUTVU_MASK                     0x0080  /* HPOUTVU */
 834 #define WM8903_HPOUTVU_SHIFT                         7  /* HPOUTVU */
 835 #define WM8903_HPOUTVU_WIDTH                         1  /* HPOUTVU */
 836 #define WM8903_HPOUTRZC                         0x0040  /* HPOUTRZC */
 837 #define WM8903_HPOUTRZC_MASK                    0x0040  /* HPOUTRZC */
 838 #define WM8903_HPOUTRZC_SHIFT                        6  /* HPOUTRZC */
 839 #define WM8903_HPOUTRZC_WIDTH                        1  /* HPOUTRZC */
 840 #define WM8903_HPOUTR_VOL_MASK                  0x003F  /* HPOUTR_VOL - [5:0] */
 841 #define WM8903_HPOUTR_VOL_SHIFT                      0  /* HPOUTR_VOL - [5:0] */
 842 #define WM8903_HPOUTR_VOL_WIDTH                      6  /* HPOUTR_VOL - [5:0] */
 843 
 844 /*
 845  * R59 (0x3B) - Analogue OUT2 Left
 846  */
 847 #define WM8903_LINEOUTL_MUTE                    0x0100  /* LINEOUTL_MUTE */
 848 #define WM8903_LINEOUTL_MUTE_MASK               0x0100  /* LINEOUTL_MUTE */
 849 #define WM8903_LINEOUTL_MUTE_SHIFT                   8  /* LINEOUTL_MUTE */
 850 #define WM8903_LINEOUTL_MUTE_WIDTH                   1  /* LINEOUTL_MUTE */
 851 #define WM8903_LINEOUTVU                        0x0080  /* LINEOUTVU */
 852 #define WM8903_LINEOUTVU_MASK                   0x0080  /* LINEOUTVU */
 853 #define WM8903_LINEOUTVU_SHIFT                       7  /* LINEOUTVU */
 854 #define WM8903_LINEOUTVU_WIDTH                       1  /* LINEOUTVU */
 855 #define WM8903_LINEOUTLZC                       0x0040  /* LINEOUTLZC */
 856 #define WM8903_LINEOUTLZC_MASK                  0x0040  /* LINEOUTLZC */
 857 #define WM8903_LINEOUTLZC_SHIFT                      6  /* LINEOUTLZC */
 858 #define WM8903_LINEOUTLZC_WIDTH                      1  /* LINEOUTLZC */
 859 #define WM8903_LINEOUTL_VOL_MASK                0x003F  /* LINEOUTL_VOL - [5:0] */
 860 #define WM8903_LINEOUTL_VOL_SHIFT                    0  /* LINEOUTL_VOL - [5:0] */
 861 #define WM8903_LINEOUTL_VOL_WIDTH                    6  /* LINEOUTL_VOL - [5:0] */
 862 
 863 /*
 864  * R60 (0x3C) - Analogue OUT2 Right
 865  */
 866 #define WM8903_LINEOUTR_MUTE                    0x0100  /* LINEOUTR_MUTE */
 867 #define WM8903_LINEOUTR_MUTE_MASK               0x0100  /* LINEOUTR_MUTE */
 868 #define WM8903_LINEOUTR_MUTE_SHIFT                   8  /* LINEOUTR_MUTE */
 869 #define WM8903_LINEOUTR_MUTE_WIDTH                   1  /* LINEOUTR_MUTE */
 870 #define WM8903_LINEOUTVU                        0x0080  /* LINEOUTVU */
 871 #define WM8903_LINEOUTVU_MASK                   0x0080  /* LINEOUTVU */
 872 #define WM8903_LINEOUTVU_SHIFT                       7  /* LINEOUTVU */
 873 #define WM8903_LINEOUTVU_WIDTH                       1  /* LINEOUTVU */
 874 #define WM8903_LINEOUTRZC                       0x0040  /* LINEOUTRZC */
 875 #define WM8903_LINEOUTRZC_MASK                  0x0040  /* LINEOUTRZC */
 876 #define WM8903_LINEOUTRZC_SHIFT                      6  /* LINEOUTRZC */
 877 #define WM8903_LINEOUTRZC_WIDTH                      1  /* LINEOUTRZC */
 878 #define WM8903_LINEOUTR_VOL_MASK                0x003F  /* LINEOUTR_VOL - [5:0] */
 879 #define WM8903_LINEOUTR_VOL_SHIFT                    0  /* LINEOUTR_VOL - [5:0] */
 880 #define WM8903_LINEOUTR_VOL_WIDTH                    6  /* LINEOUTR_VOL - [5:0] */
 881 
 882 /*
 883  * R62 (0x3E) - Analogue OUT3 Left
 884  */
 885 #define WM8903_SPKL_MUTE                        0x0100  /* SPKL_MUTE */
 886 #define WM8903_SPKL_MUTE_MASK                   0x0100  /* SPKL_MUTE */
 887 #define WM8903_SPKL_MUTE_SHIFT                       8  /* SPKL_MUTE */
 888 #define WM8903_SPKL_MUTE_WIDTH                       1  /* SPKL_MUTE */
 889 #define WM8903_SPKVU                            0x0080  /* SPKVU */
 890 #define WM8903_SPKVU_MASK                       0x0080  /* SPKVU */
 891 #define WM8903_SPKVU_SHIFT                           7  /* SPKVU */
 892 #define WM8903_SPKVU_WIDTH                           1  /* SPKVU */
 893 #define WM8903_SPKLZC                           0x0040  /* SPKLZC */
 894 #define WM8903_SPKLZC_MASK                      0x0040  /* SPKLZC */
 895 #define WM8903_SPKLZC_SHIFT                          6  /* SPKLZC */
 896 #define WM8903_SPKLZC_WIDTH                          1  /* SPKLZC */
 897 #define WM8903_SPKL_VOL_MASK                    0x003F  /* SPKL_VOL - [5:0] */
 898 #define WM8903_SPKL_VOL_SHIFT                        0  /* SPKL_VOL - [5:0] */
 899 #define WM8903_SPKL_VOL_WIDTH                        6  /* SPKL_VOL - [5:0] */
 900 
 901 /*
 902  * R63 (0x3F) - Analogue OUT3 Right
 903  */
 904 #define WM8903_SPKR_MUTE                        0x0100  /* SPKR_MUTE */
 905 #define WM8903_SPKR_MUTE_MASK                   0x0100  /* SPKR_MUTE */
 906 #define WM8903_SPKR_MUTE_SHIFT                       8  /* SPKR_MUTE */
 907 #define WM8903_SPKR_MUTE_WIDTH                       1  /* SPKR_MUTE */
 908 #define WM8903_SPKVU                            0x0080  /* SPKVU */
 909 #define WM8903_SPKVU_MASK                       0x0080  /* SPKVU */
 910 #define WM8903_SPKVU_SHIFT                           7  /* SPKVU */
 911 #define WM8903_SPKVU_WIDTH                           1  /* SPKVU */
 912 #define WM8903_SPKRZC                           0x0040  /* SPKRZC */
 913 #define WM8903_SPKRZC_MASK                      0x0040  /* SPKRZC */
 914 #define WM8903_SPKRZC_SHIFT                          6  /* SPKRZC */
 915 #define WM8903_SPKRZC_WIDTH                          1  /* SPKRZC */
 916 #define WM8903_SPKR_VOL_MASK                    0x003F  /* SPKR_VOL - [5:0] */
 917 #define WM8903_SPKR_VOL_SHIFT                        0  /* SPKR_VOL - [5:0] */
 918 #define WM8903_SPKR_VOL_WIDTH                        6  /* SPKR_VOL - [5:0] */
 919 
 920 /*
 921  * R65 (0x41) - Analogue SPK Output Control 0
 922  */
 923 #define WM8903_SPK_DISCHARGE                    0x0002  /* SPK_DISCHARGE */
 924 #define WM8903_SPK_DISCHARGE_MASK               0x0002  /* SPK_DISCHARGE */
 925 #define WM8903_SPK_DISCHARGE_SHIFT                   1  /* SPK_DISCHARGE */
 926 #define WM8903_SPK_DISCHARGE_WIDTH                   1  /* SPK_DISCHARGE */
 927 #define WM8903_VROI                             0x0001  /* VROI */
 928 #define WM8903_VROI_MASK                        0x0001  /* VROI */
 929 #define WM8903_VROI_SHIFT                            0  /* VROI */
 930 #define WM8903_VROI_WIDTH                            1  /* VROI */
 931 
 932 /*
 933  * R67 (0x43) - DC Servo 0
 934  */
 935 #define WM8903_DCS_MASTER_ENA                   0x0010  /* DCS_MASTER_ENA */
 936 #define WM8903_DCS_MASTER_ENA_MASK              0x0010  /* DCS_MASTER_ENA */
 937 #define WM8903_DCS_MASTER_ENA_SHIFT                  4  /* DCS_MASTER_ENA */
 938 #define WM8903_DCS_MASTER_ENA_WIDTH                  1  /* DCS_MASTER_ENA */
 939 #define WM8903_DCS_ENA_MASK                     0x000F  /* DCS_ENA - [3:0] */
 940 #define WM8903_DCS_ENA_SHIFT                         0  /* DCS_ENA - [3:0] */
 941 #define WM8903_DCS_ENA_WIDTH                         4  /* DCS_ENA - [3:0] */
 942 
 943 /*
 944  * R69 (0x45) - DC Servo 2
 945  */
 946 #define WM8903_DCS_MODE_MASK                    0x0003  /* DCS_MODE - [1:0] */
 947 #define WM8903_DCS_MODE_SHIFT                        0  /* DCS_MODE - [1:0] */
 948 #define WM8903_DCS_MODE_WIDTH                        2  /* DCS_MODE - [1:0] */
 949 
 950 /*
 951  * R90 (0x5A) - Analogue HP 0
 952  */
 953 #define WM8903_HPL_RMV_SHORT                    0x0080  /* HPL_RMV_SHORT */
 954 #define WM8903_HPL_RMV_SHORT_MASK               0x0080  /* HPL_RMV_SHORT */
 955 #define WM8903_HPL_RMV_SHORT_SHIFT                   7  /* HPL_RMV_SHORT */
 956 #define WM8903_HPL_RMV_SHORT_WIDTH                   1  /* HPL_RMV_SHORT */
 957 #define WM8903_HPL_ENA_OUTP                     0x0040  /* HPL_ENA_OUTP */
 958 #define WM8903_HPL_ENA_OUTP_MASK                0x0040  /* HPL_ENA_OUTP */
 959 #define WM8903_HPL_ENA_OUTP_SHIFT                    6  /* HPL_ENA_OUTP */
 960 #define WM8903_HPL_ENA_OUTP_WIDTH                    1  /* HPL_ENA_OUTP */
 961 #define WM8903_HPL_ENA_DLY                      0x0020  /* HPL_ENA_DLY */
 962 #define WM8903_HPL_ENA_DLY_MASK                 0x0020  /* HPL_ENA_DLY */
 963 #define WM8903_HPL_ENA_DLY_SHIFT                     5  /* HPL_ENA_DLY */
 964 #define WM8903_HPL_ENA_DLY_WIDTH                     1  /* HPL_ENA_DLY */
 965 #define WM8903_HPL_ENA                          0x0010  /* HPL_ENA */
 966 #define WM8903_HPL_ENA_MASK                     0x0010  /* HPL_ENA */
 967 #define WM8903_HPL_ENA_SHIFT                         4  /* HPL_ENA */
 968 #define WM8903_HPL_ENA_WIDTH                         1  /* HPL_ENA */
 969 #define WM8903_HPR_RMV_SHORT                    0x0008  /* HPR_RMV_SHORT */
 970 #define WM8903_HPR_RMV_SHORT_MASK               0x0008  /* HPR_RMV_SHORT */
 971 #define WM8903_HPR_RMV_SHORT_SHIFT                   3  /* HPR_RMV_SHORT */
 972 #define WM8903_HPR_RMV_SHORT_WIDTH                   1  /* HPR_RMV_SHORT */
 973 #define WM8903_HPR_ENA_OUTP                     0x0004  /* HPR_ENA_OUTP */
 974 #define WM8903_HPR_ENA_OUTP_MASK                0x0004  /* HPR_ENA_OUTP */
 975 #define WM8903_HPR_ENA_OUTP_SHIFT                    2  /* HPR_ENA_OUTP */
 976 #define WM8903_HPR_ENA_OUTP_WIDTH                    1  /* HPR_ENA_OUTP */
 977 #define WM8903_HPR_ENA_DLY                      0x0002  /* HPR_ENA_DLY */
 978 #define WM8903_HPR_ENA_DLY_MASK                 0x0002  /* HPR_ENA_DLY */
 979 #define WM8903_HPR_ENA_DLY_SHIFT                     1  /* HPR_ENA_DLY */
 980 #define WM8903_HPR_ENA_DLY_WIDTH                     1  /* HPR_ENA_DLY */
 981 #define WM8903_HPR_ENA                          0x0001  /* HPR_ENA */
 982 #define WM8903_HPR_ENA_MASK                     0x0001  /* HPR_ENA */
 983 #define WM8903_HPR_ENA_SHIFT                         0  /* HPR_ENA */
 984 #define WM8903_HPR_ENA_WIDTH                         1  /* HPR_ENA */
 985 
 986 /*
 987  * R94 (0x5E) - Analogue Lineout 0
 988  */
 989 #define WM8903_LINEOUTL_RMV_SHORT               0x0080  /* LINEOUTL_RMV_SHORT */
 990 #define WM8903_LINEOUTL_RMV_SHORT_MASK          0x0080  /* LINEOUTL_RMV_SHORT */
 991 #define WM8903_LINEOUTL_RMV_SHORT_SHIFT              7  /* LINEOUTL_RMV_SHORT */
 992 #define WM8903_LINEOUTL_RMV_SHORT_WIDTH              1  /* LINEOUTL_RMV_SHORT */
 993 #define WM8903_LINEOUTL_ENA_OUTP                0x0040  /* LINEOUTL_ENA_OUTP */
 994 #define WM8903_LINEOUTL_ENA_OUTP_MASK           0x0040  /* LINEOUTL_ENA_OUTP */
 995 #define WM8903_LINEOUTL_ENA_OUTP_SHIFT               6  /* LINEOUTL_ENA_OUTP */
 996 #define WM8903_LINEOUTL_ENA_OUTP_WIDTH               1  /* LINEOUTL_ENA_OUTP */
 997 #define WM8903_LINEOUTL_ENA_DLY                 0x0020  /* LINEOUTL_ENA_DLY */
 998 #define WM8903_LINEOUTL_ENA_DLY_MASK            0x0020  /* LINEOUTL_ENA_DLY */
 999 #define WM8903_LINEOUTL_ENA_DLY_SHIFT                5  /* LINEOUTL_ENA_DLY */
1000 #define WM8903_LINEOUTL_ENA_DLY_WIDTH                1  /* LINEOUTL_ENA_DLY */
1001 #define WM8903_LINEOUTL_ENA                     0x0010  /* LINEOUTL_ENA */
1002 #define WM8903_LINEOUTL_ENA_MASK                0x0010  /* LINEOUTL_ENA */
1003 #define WM8903_LINEOUTL_ENA_SHIFT                    4  /* LINEOUTL_ENA */
1004 #define WM8903_LINEOUTL_ENA_WIDTH                    1  /* LINEOUTL_ENA */
1005 #define WM8903_LINEOUTR_RMV_SHORT               0x0008  /* LINEOUTR_RMV_SHORT */
1006 #define WM8903_LINEOUTR_RMV_SHORT_MASK          0x0008  /* LINEOUTR_RMV_SHORT */
1007 #define WM8903_LINEOUTR_RMV_SHORT_SHIFT              3  /* LINEOUTR_RMV_SHORT */
1008 #define WM8903_LINEOUTR_RMV_SHORT_WIDTH              1  /* LINEOUTR_RMV_SHORT */
1009 #define WM8903_LINEOUTR_ENA_OUTP                0x0004  /* LINEOUTR_ENA_OUTP */
1010 #define WM8903_LINEOUTR_ENA_OUTP_MASK           0x0004  /* LINEOUTR_ENA_OUTP */
1011 #define WM8903_LINEOUTR_ENA_OUTP_SHIFT               2  /* LINEOUTR_ENA_OUTP */
1012 #define WM8903_LINEOUTR_ENA_OUTP_WIDTH               1  /* LINEOUTR_ENA_OUTP */
1013 #define WM8903_LINEOUTR_ENA_DLY                 0x0002  /* LINEOUTR_ENA_DLY */
1014 #define WM8903_LINEOUTR_ENA_DLY_MASK            0x0002  /* LINEOUTR_ENA_DLY */
1015 #define WM8903_LINEOUTR_ENA_DLY_SHIFT                1  /* LINEOUTR_ENA_DLY */
1016 #define WM8903_LINEOUTR_ENA_DLY_WIDTH                1  /* LINEOUTR_ENA_DLY */
1017 #define WM8903_LINEOUTR_ENA                     0x0001  /* LINEOUTR_ENA */
1018 #define WM8903_LINEOUTR_ENA_MASK                0x0001  /* LINEOUTR_ENA */
1019 #define WM8903_LINEOUTR_ENA_SHIFT                    0  /* LINEOUTR_ENA */
1020 #define WM8903_LINEOUTR_ENA_WIDTH                    1  /* LINEOUTR_ENA */
1021 
1022 /*
1023  * R98 (0x62) - Charge Pump 0
1024  */
1025 #define WM8903_CP_ENA                           0x0001  /* CP_ENA */
1026 #define WM8903_CP_ENA_MASK                      0x0001  /* CP_ENA */
1027 #define WM8903_CP_ENA_SHIFT                          0  /* CP_ENA */
1028 #define WM8903_CP_ENA_WIDTH                          1  /* CP_ENA */
1029 
1030 /*
1031  * R104 (0x68) - Class W 0
1032  */
1033 #define WM8903_CP_DYN_FREQ                      0x0002  /* CP_DYN_FREQ */
1034 #define WM8903_CP_DYN_FREQ_MASK                 0x0002  /* CP_DYN_FREQ */
1035 #define WM8903_CP_DYN_FREQ_SHIFT                     1  /* CP_DYN_FREQ */
1036 #define WM8903_CP_DYN_FREQ_WIDTH                     1  /* CP_DYN_FREQ */
1037 #define WM8903_CP_DYN_V                         0x0001  /* CP_DYN_V */
1038 #define WM8903_CP_DYN_V_MASK                    0x0001  /* CP_DYN_V */
1039 #define WM8903_CP_DYN_V_SHIFT                        0  /* CP_DYN_V */
1040 #define WM8903_CP_DYN_V_WIDTH                        1  /* CP_DYN_V */
1041 
1042 /*
1043  * R108 (0x6C) - Write Sequencer 0
1044  */
1045 #define WM8903_WSEQ_ENA                         0x0100  /* WSEQ_ENA */
1046 #define WM8903_WSEQ_ENA_MASK                    0x0100  /* WSEQ_ENA */
1047 #define WM8903_WSEQ_ENA_SHIFT                        8  /* WSEQ_ENA */
1048 #define WM8903_WSEQ_ENA_WIDTH                        1  /* WSEQ_ENA */
1049 #define WM8903_WSEQ_WRITE_INDEX_MASK            0x001F  /* WSEQ_WRITE_INDEX - [4:0] */
1050 #define WM8903_WSEQ_WRITE_INDEX_SHIFT                0  /* WSEQ_WRITE_INDEX - [4:0] */
1051 #define WM8903_WSEQ_WRITE_INDEX_WIDTH                5  /* WSEQ_WRITE_INDEX - [4:0] */
1052 
1053 /*
1054  * R109 (0x6D) - Write Sequencer 1
1055  */
1056 #define WM8903_WSEQ_DATA_WIDTH_MASK             0x7000  /* WSEQ_DATA_WIDTH - [14:12] */
1057 #define WM8903_WSEQ_DATA_WIDTH_SHIFT                12  /* WSEQ_DATA_WIDTH - [14:12] */
1058 #define WM8903_WSEQ_DATA_WIDTH_WIDTH                 3  /* WSEQ_DATA_WIDTH - [14:12] */
1059 #define WM8903_WSEQ_DATA_START_MASK             0x0F00  /* WSEQ_DATA_START - [11:8] */
1060 #define WM8903_WSEQ_DATA_START_SHIFT                 8  /* WSEQ_DATA_START - [11:8] */
1061 #define WM8903_WSEQ_DATA_START_WIDTH                 4  /* WSEQ_DATA_START - [11:8] */
1062 #define WM8903_WSEQ_ADDR_MASK                   0x00FF  /* WSEQ_ADDR - [7:0] */
1063 #define WM8903_WSEQ_ADDR_SHIFT                       0  /* WSEQ_ADDR - [7:0] */
1064 #define WM8903_WSEQ_ADDR_WIDTH                       8  /* WSEQ_ADDR - [7:0] */
1065 
1066 /*
1067  * R110 (0x6E) - Write Sequencer 2
1068  */
1069 #define WM8903_WSEQ_EOS                         0x4000  /* WSEQ_EOS */
1070 #define WM8903_WSEQ_EOS_MASK                    0x4000  /* WSEQ_EOS */
1071 #define WM8903_WSEQ_EOS_SHIFT                       14  /* WSEQ_EOS */
1072 #define WM8903_WSEQ_EOS_WIDTH                        1  /* WSEQ_EOS */
1073 #define WM8903_WSEQ_DELAY_MASK                  0x0F00  /* WSEQ_DELAY - [11:8] */
1074 #define WM8903_WSEQ_DELAY_SHIFT                      8  /* WSEQ_DELAY - [11:8] */
1075 #define WM8903_WSEQ_DELAY_WIDTH                      4  /* WSEQ_DELAY - [11:8] */
1076 #define WM8903_WSEQ_DATA_MASK                   0x00FF  /* WSEQ_DATA - [7:0] */
1077 #define WM8903_WSEQ_DATA_SHIFT                       0  /* WSEQ_DATA - [7:0] */
1078 #define WM8903_WSEQ_DATA_WIDTH                       8  /* WSEQ_DATA - [7:0] */
1079 
1080 /*
1081  * R111 (0x6F) - Write Sequencer 3
1082  */
1083 #define WM8903_WSEQ_ABORT                       0x0200  /* WSEQ_ABORT */
1084 #define WM8903_WSEQ_ABORT_MASK                  0x0200  /* WSEQ_ABORT */
1085 #define WM8903_WSEQ_ABORT_SHIFT                      9  /* WSEQ_ABORT */
1086 #define WM8903_WSEQ_ABORT_WIDTH                      1  /* WSEQ_ABORT */
1087 #define WM8903_WSEQ_START                       0x0100  /* WSEQ_START */
1088 #define WM8903_WSEQ_START_MASK                  0x0100  /* WSEQ_START */
1089 #define WM8903_WSEQ_START_SHIFT                      8  /* WSEQ_START */
1090 #define WM8903_WSEQ_START_WIDTH                      1  /* WSEQ_START */
1091 #define WM8903_WSEQ_START_INDEX_MASK            0x003F  /* WSEQ_START_INDEX - [5:0] */
1092 #define WM8903_WSEQ_START_INDEX_SHIFT                0  /* WSEQ_START_INDEX - [5:0] */
1093 #define WM8903_WSEQ_START_INDEX_WIDTH                6  /* WSEQ_START_INDEX - [5:0] */
1094 
1095 /*
1096  * R112 (0x70) - Write Sequencer 4
1097  */
1098 #define WM8903_WSEQ_CURRENT_INDEX_MASK          0x03F0  /* WSEQ_CURRENT_INDEX - [9:4] */
1099 #define WM8903_WSEQ_CURRENT_INDEX_SHIFT              4  /* WSEQ_CURRENT_INDEX - [9:4] */
1100 #define WM8903_WSEQ_CURRENT_INDEX_WIDTH              6  /* WSEQ_CURRENT_INDEX - [9:4] */
1101 #define WM8903_WSEQ_BUSY                        0x0001  /* WSEQ_BUSY */
1102 #define WM8903_WSEQ_BUSY_MASK                   0x0001  /* WSEQ_BUSY */
1103 #define WM8903_WSEQ_BUSY_SHIFT                       0  /* WSEQ_BUSY */
1104 #define WM8903_WSEQ_BUSY_WIDTH                       1  /* WSEQ_BUSY */
1105 
1106 /*
1107  * R114 (0x72) - Control Interface
1108  */
1109 #define WM8903_MASK_WRITE_ENA                   0x0001  /* MASK_WRITE_ENA */
1110 #define WM8903_MASK_WRITE_ENA_MASK              0x0001  /* MASK_WRITE_ENA */
1111 #define WM8903_MASK_WRITE_ENA_SHIFT                  0  /* MASK_WRITE_ENA */
1112 #define WM8903_MASK_WRITE_ENA_WIDTH                  1  /* MASK_WRITE_ENA */
1113 
1114 /*
1115  * R121 (0x79) - Interrupt Status 1
1116  */
1117 #define WM8903_MICSHRT_EINT                     0x8000  /* MICSHRT_EINT */
1118 #define WM8903_MICSHRT_EINT_MASK                0x8000  /* MICSHRT_EINT */
1119 #define WM8903_MICSHRT_EINT_SHIFT                   15  /* MICSHRT_EINT */
1120 #define WM8903_MICSHRT_EINT_WIDTH                    1  /* MICSHRT_EINT */
1121 #define WM8903_MICDET_EINT                      0x4000  /* MICDET_EINT */
1122 #define WM8903_MICDET_EINT_MASK                 0x4000  /* MICDET_EINT */
1123 #define WM8903_MICDET_EINT_SHIFT                    14  /* MICDET_EINT */
1124 #define WM8903_MICDET_EINT_WIDTH                     1  /* MICDET_EINT */
1125 #define WM8903_WSEQ_BUSY_EINT                   0x2000  /* WSEQ_BUSY_EINT */
1126 #define WM8903_WSEQ_BUSY_EINT_MASK              0x2000  /* WSEQ_BUSY_EINT */
1127 #define WM8903_WSEQ_BUSY_EINT_SHIFT                 13  /* WSEQ_BUSY_EINT */
1128 #define WM8903_WSEQ_BUSY_EINT_WIDTH                  1  /* WSEQ_BUSY_EINT */
1129 #define WM8903_GP5_EINT                         0x0010  /* GP5_EINT */
1130 #define WM8903_GP5_EINT_MASK                    0x0010  /* GP5_EINT */
1131 #define WM8903_GP5_EINT_SHIFT                        4  /* GP5_EINT */
1132 #define WM8903_GP5_EINT_WIDTH                        1  /* GP5_EINT */
1133 #define WM8903_GP4_EINT                         0x0008  /* GP4_EINT */
1134 #define WM8903_GP4_EINT_MASK                    0x0008  /* GP4_EINT */
1135 #define WM8903_GP4_EINT_SHIFT                        3  /* GP4_EINT */
1136 #define WM8903_GP4_EINT_WIDTH                        1  /* GP4_EINT */
1137 #define WM8903_GP3_EINT                         0x0004  /* GP3_EINT */
1138 #define WM8903_GP3_EINT_MASK                    0x0004  /* GP3_EINT */
1139 #define WM8903_GP3_EINT_SHIFT                        2  /* GP3_EINT */
1140 #define WM8903_GP3_EINT_WIDTH                        1  /* GP3_EINT */
1141 #define WM8903_GP2_EINT                         0x0002  /* GP2_EINT */
1142 #define WM8903_GP2_EINT_MASK                    0x0002  /* GP2_EINT */
1143 #define WM8903_GP2_EINT_SHIFT                        1  /* GP2_EINT */
1144 #define WM8903_GP2_EINT_WIDTH                        1  /* GP2_EINT */
1145 #define WM8903_GP1_EINT                         0x0001  /* GP1_EINT */
1146 #define WM8903_GP1_EINT_MASK                    0x0001  /* GP1_EINT */
1147 #define WM8903_GP1_EINT_SHIFT                        0  /* GP1_EINT */
1148 #define WM8903_GP1_EINT_WIDTH                        1  /* GP1_EINT */
1149 
1150 /*
1151  * R122 (0x7A) - Interrupt Status 1 Mask
1152  */
1153 #define WM8903_IM_MICSHRT_EINT                  0x8000  /* IM_MICSHRT_EINT */
1154 #define WM8903_IM_MICSHRT_EINT_MASK             0x8000  /* IM_MICSHRT_EINT */
1155 #define WM8903_IM_MICSHRT_EINT_SHIFT                15  /* IM_MICSHRT_EINT */
1156 #define WM8903_IM_MICSHRT_EINT_WIDTH                 1  /* IM_MICSHRT_EINT */
1157 #define WM8903_IM_MICDET_EINT                   0x4000  /* IM_MICDET_EINT */
1158 #define WM8903_IM_MICDET_EINT_MASK              0x4000  /* IM_MICDET_EINT */
1159 #define WM8903_IM_MICDET_EINT_SHIFT                 14  /* IM_MICDET_EINT */
1160 #define WM8903_IM_MICDET_EINT_WIDTH                  1  /* IM_MICDET_EINT */
1161 #define WM8903_IM_WSEQ_BUSY_EINT                0x2000  /* IM_WSEQ_BUSY_EINT */
1162 #define WM8903_IM_WSEQ_BUSY_EINT_MASK           0x2000  /* IM_WSEQ_BUSY_EINT */
1163 #define WM8903_IM_WSEQ_BUSY_EINT_SHIFT              13  /* IM_WSEQ_BUSY_EINT */
1164 #define WM8903_IM_WSEQ_BUSY_EINT_WIDTH               1  /* IM_WSEQ_BUSY_EINT */
1165 #define WM8903_IM_GP5_EINT                      0x0010  /* IM_GP5_EINT */
1166 #define WM8903_IM_GP5_EINT_MASK                 0x0010  /* IM_GP5_EINT */
1167 #define WM8903_IM_GP5_EINT_SHIFT                     4  /* IM_GP5_EINT */
1168 #define WM8903_IM_GP5_EINT_WIDTH                     1  /* IM_GP5_EINT */
1169 #define WM8903_IM_GP4_EINT                      0x0008  /* IM_GP4_EINT */
1170 #define WM8903_IM_GP4_EINT_MASK                 0x0008  /* IM_GP4_EINT */
1171 #define WM8903_IM_GP4_EINT_SHIFT                     3  /* IM_GP4_EINT */
1172 #define WM8903_IM_GP4_EINT_WIDTH                     1  /* IM_GP4_EINT */
1173 #define WM8903_IM_GP3_EINT                      0x0004  /* IM_GP3_EINT */
1174 #define WM8903_IM_GP3_EINT_MASK                 0x0004  /* IM_GP3_EINT */
1175 #define WM8903_IM_GP3_EINT_SHIFT                     2  /* IM_GP3_EINT */
1176 #define WM8903_IM_GP3_EINT_WIDTH                     1  /* IM_GP3_EINT */
1177 #define WM8903_IM_GP2_EINT                      0x0002  /* IM_GP2_EINT */
1178 #define WM8903_IM_GP2_EINT_MASK                 0x0002  /* IM_GP2_EINT */
1179 #define WM8903_IM_GP2_EINT_SHIFT                     1  /* IM_GP2_EINT */
1180 #define WM8903_IM_GP2_EINT_WIDTH                     1  /* IM_GP2_EINT */
1181 #define WM8903_IM_GP1_EINT                      0x0001  /* IM_GP1_EINT */
1182 #define WM8903_IM_GP1_EINT_MASK                 0x0001  /* IM_GP1_EINT */
1183 #define WM8903_IM_GP1_EINT_SHIFT                     0  /* IM_GP1_EINT */
1184 #define WM8903_IM_GP1_EINT_WIDTH                     1  /* IM_GP1_EINT */
1185 
1186 /*
1187  * R123 (0x7B) - Interrupt Polarity 1
1188  */
1189 #define WM8903_MICSHRT_INV                      0x8000  /* MICSHRT_INV */
1190 #define WM8903_MICSHRT_INV_MASK                 0x8000  /* MICSHRT_INV */
1191 #define WM8903_MICSHRT_INV_SHIFT                    15  /* MICSHRT_INV */
1192 #define WM8903_MICSHRT_INV_WIDTH                     1  /* MICSHRT_INV */
1193 #define WM8903_MICDET_INV                       0x4000  /* MICDET_INV */
1194 #define WM8903_MICDET_INV_MASK                  0x4000  /* MICDET_INV */
1195 #define WM8903_MICDET_INV_SHIFT                     14  /* MICDET_INV */
1196 #define WM8903_MICDET_INV_WIDTH                      1  /* MICDET_INV */
1197 
1198 /*
1199  * R126 (0x7E) - Interrupt Control
1200  */
1201 #define WM8903_IRQ_POL                          0x0001  /* IRQ_POL */
1202 #define WM8903_IRQ_POL_MASK                     0x0001  /* IRQ_POL */
1203 #define WM8903_IRQ_POL_SHIFT                         0  /* IRQ_POL */
1204 #define WM8903_IRQ_POL_WIDTH                         1  /* IRQ_POL */
1205 
1206 /*
1207  * R164 (0xA4) - Clock Rate Test 4
1208  */
1209 #define WM8903_ADC_DIG_MIC                      0x0200  /* ADC_DIG_MIC */
1210 #define WM8903_ADC_DIG_MIC_MASK                 0x0200  /* ADC_DIG_MIC */
1211 #define WM8903_ADC_DIG_MIC_SHIFT                     9  /* ADC_DIG_MIC */
1212 #define WM8903_ADC_DIG_MIC_WIDTH                     1  /* ADC_DIG_MIC */
1213 
1214 /*
1215  * R172 (0xAC) - Analogue Output Bias 0
1216  */
1217 #define WM8903_PGA_BIAS_MASK                    0x0070  /* PGA_BIAS - [6:4] */
1218 #define WM8903_PGA_BIAS_SHIFT                        4  /* PGA_BIAS - [6:4] */
1219 #define WM8903_PGA_BIAS_WIDTH                        3  /* PGA_BIAS - [6:4] */
1220 
1221 #endif