sound/soc/codecs/nau8825.c

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This source file includes following definitions.
nau8825_sema_acquire
nau8825_sema_release
nau8825_sema_reset
nau8825_hpvol_ramp
nau8825_intlog10_dec3
nau8825_xtalk_sidetone
nau8825_xtalk_baktab_index_by_reg
nau8825_xtalk_backup
nau8825_xtalk_restore
nau8825_xtalk_prepare_dac
nau8825_xtalk_prepare_adc
nau8825_xtalk_clock
nau8825_xtalk_prepare
nau8825_xtalk_clean_dac
nau8825_xtalk_clean_adc
nau8825_xtalk_clean
nau8825_xtalk_imm_start
nau8825_xtalk_imm_stop
nau8825_xtalk_measure
nau8825_xtalk_work
nau8825_xtalk_cancel
nau8825_readable_reg
nau8825_writeable_reg
nau8825_volatile_reg
nau8825_adc_event
nau8825_pump_event
nau8825_output_dac_event
nau8825_biq_coeff_get
nau8825_biq_coeff_put
nau8825_clock_check
nau8825_hw_params
nau8825_set_dai_fmt
nau8825_enable_jack_detect
nau8825_is_jack_inserted
nau8825_restart_jack_detection
nau8825_int_status_clear_all
nau8825_eject_jack
nau8825_setup_auto_irq
nau8825_button_decode
nau8825_jack_insert
nau8825_interrupt
nau8825_setup_buttons
nau8825_init_regs
nau8825_component_probe
nau8825_component_remove
nau8825_calc_fll_param
nau8825_fll_apply
nau8825_set_pll
nau8825_mclk_prepare
nau8825_configure_mclk_as_sysclk
nau8825_configure_sysclk
nau8825_set_sysclk
nau8825_resume_setup
nau8825_set_bias_level
nau8825_suspend
nau8825_resume
nau8825_reset_chip
nau8825_print_device_properties
nau8825_read_device_properties
nau8825_setup_irq
nau8825_i2c_probe
nau8825_i2c_remove
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Nuvoton NAU8825 audio codec driver
   4  *
   5  * Copyright 2015 Google Chromium project.
   6  *  Author: Anatol Pomozov <anatol@chromium.org>
   7  * Copyright 2015 Nuvoton Technology Corp.
   8  *  Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
   9  */
  10 
  11 #include <linux/module.h>
  12 #include <linux/delay.h>
  13 #include <linux/init.h>
  14 #include <linux/i2c.h>
  15 #include <linux/regmap.h>
  16 #include <linux/slab.h>
  17 #include <linux/clk.h>
  18 #include <linux/acpi.h>
  19 #include <linux/math64.h>
  20 #include <linux/semaphore.h>
  21 
  22 #include <sound/initval.h>
  23 #include <sound/tlv.h>
  24 #include <sound/core.h>
  25 #include <sound/pcm.h>
  26 #include <sound/pcm_params.h>
  27 #include <sound/soc.h>
  28 #include <sound/jack.h>
  29 
  30 
  31 #include "nau8825.h"
  32 
  33 
  34 #define NUVOTON_CODEC_DAI "nau8825-hifi"
  35 
  36 #define NAU_FREF_MAX 13500000
  37 #define NAU_FVCO_MAX 124000000
  38 #define NAU_FVCO_MIN 90000000
  39 
  40 /* cross talk suppression detection */
  41 #define LOG10_MAGIC 646456993
  42 #define GAIN_AUGMENT 22500
  43 #define SIDETONE_BASE 207000
  44 
  45 /* the maximum frequency of CLK_ADC and CLK_DAC */
  46 #define CLK_DA_AD_MAX 6144000
  47 
  48 static int nau8825_configure_sysclk(struct nau8825 *nau8825,
  49                 int clk_id, unsigned int freq);
  50 
  51 struct nau8825_fll {
  52         int mclk_src;
  53         int ratio;
  54         int fll_frac;
  55         int fll_int;
  56         int clk_ref_div;
  57 };
  58 
  59 struct nau8825_fll_attr {
  60         unsigned int param;
  61         unsigned int val;
  62 };
  63 
  64 /* scaling for mclk from sysclk_src output */
  65 static const struct nau8825_fll_attr mclk_src_scaling[] = {
  66         { 1, 0x0 },
  67         { 2, 0x2 },
  68         { 4, 0x3 },
  69         { 8, 0x4 },
  70         { 16, 0x5 },
  71         { 32, 0x6 },
  72         { 3, 0x7 },
  73         { 6, 0xa },
  74         { 12, 0xb },
  75         { 24, 0xc },
  76         { 48, 0xd },
  77         { 96, 0xe },
  78         { 5, 0xf },
  79 };
  80 
  81 /* ratio for input clk freq */
  82 static const struct nau8825_fll_attr fll_ratio[] = {
  83         { 512000, 0x01 },
  84         { 256000, 0x02 },
  85         { 128000, 0x04 },
  86         { 64000, 0x08 },
  87         { 32000, 0x10 },
  88         { 8000, 0x20 },
  89         { 4000, 0x40 },
  90 };
  91 
  92 static const struct nau8825_fll_attr fll_pre_scalar[] = {
  93         { 1, 0x0 },
  94         { 2, 0x1 },
  95         { 4, 0x2 },
  96         { 8, 0x3 },
  97 };
  98 
  99 /* over sampling rate */
 100 struct nau8825_osr_attr {
 101         unsigned int osr;
 102         unsigned int clk_src;
 103 };
 104 
 105 static const struct nau8825_osr_attr osr_dac_sel[] = {
 106         { 64, 2 },      /* OSR 64, SRC 1/4 */
 107         { 256, 0 },     /* OSR 256, SRC 1 */
 108         { 128, 1 },     /* OSR 128, SRC 1/2 */
 109         { 0, 0 },
 110         { 32, 3 },      /* OSR 32, SRC 1/8 */
 111 };
 112 
 113 static const struct nau8825_osr_attr osr_adc_sel[] = {
 114         { 32, 3 },      /* OSR 32, SRC 1/8 */
 115         { 64, 2 },      /* OSR 64, SRC 1/4 */
 116         { 128, 1 },     /* OSR 128, SRC 1/2 */
 117         { 256, 0 },     /* OSR 256, SRC 1 */
 118 };
 119 
 120 static const struct reg_default nau8825_reg_defaults[] = {
 121         { NAU8825_REG_ENA_CTRL, 0x00ff },
 122         { NAU8825_REG_IIC_ADDR_SET, 0x0 },
 123         { NAU8825_REG_CLK_DIVIDER, 0x0050 },
 124         { NAU8825_REG_FLL1, 0x0 },
 125         { NAU8825_REG_FLL2, 0x3126 },
 126         { NAU8825_REG_FLL3, 0x0008 },
 127         { NAU8825_REG_FLL4, 0x0010 },
 128         { NAU8825_REG_FLL5, 0x0 },
 129         { NAU8825_REG_FLL6, 0x6000 },
 130         { NAU8825_REG_FLL_VCO_RSV, 0xf13c },
 131         { NAU8825_REG_HSD_CTRL, 0x000c },
 132         { NAU8825_REG_JACK_DET_CTRL, 0x0 },
 133         { NAU8825_REG_INTERRUPT_MASK, 0x0 },
 134         { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
 135         { NAU8825_REG_SAR_CTRL, 0x0015 },
 136         { NAU8825_REG_KEYDET_CTRL, 0x0110 },
 137         { NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
 138         { NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
 139         { NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
 140         { NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
 141         { NAU8825_REG_GPIO34_CTRL, 0x0 },
 142         { NAU8825_REG_GPIO12_CTRL, 0x0 },
 143         { NAU8825_REG_TDM_CTRL, 0x0 },
 144         { NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
 145         { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
 146         { NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
 147         { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
 148         { NAU8825_REG_BIQ_CTRL, 0x0 },
 149         { NAU8825_REG_BIQ_COF1, 0x0 },
 150         { NAU8825_REG_BIQ_COF2, 0x0 },
 151         { NAU8825_REG_BIQ_COF3, 0x0 },
 152         { NAU8825_REG_BIQ_COF4, 0x0 },
 153         { NAU8825_REG_BIQ_COF5, 0x0 },
 154         { NAU8825_REG_BIQ_COF6, 0x0 },
 155         { NAU8825_REG_BIQ_COF7, 0x0 },
 156         { NAU8825_REG_BIQ_COF8, 0x0 },
 157         { NAU8825_REG_BIQ_COF9, 0x0 },
 158         { NAU8825_REG_BIQ_COF10, 0x0 },
 159         { NAU8825_REG_ADC_RATE, 0x0010 },
 160         { NAU8825_REG_DAC_CTRL1, 0x0001 },
 161         { NAU8825_REG_DAC_CTRL2, 0x0 },
 162         { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
 163         { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
 164         { NAU8825_REG_MUTE_CTRL, 0x0 },
 165         { NAU8825_REG_HSVOL_CTRL, 0x0 },
 166         { NAU8825_REG_DACL_CTRL, 0x02cf },
 167         { NAU8825_REG_DACR_CTRL, 0x00cf },
 168         { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
 169         { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
 170         { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
 171         { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
 172         { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
 173         { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
 174         { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
 175         { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
 176         { NAU8825_REG_IMM_MODE_CTRL, 0x0 },
 177         { NAU8825_REG_CLASSG_CTRL, 0x0 },
 178         { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
 179         { NAU8825_REG_MISC_CTRL, 0x0 },
 180         { NAU8825_REG_BIAS_ADJ, 0x0 },
 181         { NAU8825_REG_TRIM_SETTINGS, 0x0 },
 182         { NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
 183         { NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
 184         { NAU8825_REG_ANALOG_ADC_1, 0x0011 },
 185         { NAU8825_REG_ANALOG_ADC_2, 0x0020 },
 186         { NAU8825_REG_RDAC, 0x0008 },
 187         { NAU8825_REG_MIC_BIAS, 0x0006 },
 188         { NAU8825_REG_BOOST, 0x0 },
 189         { NAU8825_REG_FEPGA, 0x0 },
 190         { NAU8825_REG_POWER_UP_CONTROL, 0x0 },
 191         { NAU8825_REG_CHARGE_PUMP, 0x0 },
 192 };
 193 
 194 /* register backup table when cross talk detection */
 195 static struct reg_default nau8825_xtalk_baktab[] = {
 196         { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
 197         { NAU8825_REG_HSVOL_CTRL, 0 },
 198         { NAU8825_REG_DACL_CTRL, 0x00cf },
 199         { NAU8825_REG_DACR_CTRL, 0x02cf },
 200 };
 201 
 202 static const unsigned short logtable[256] = {
 203         0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7,
 204         0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508,
 205         0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6,
 206         0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37,
 207         0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f,
 208         0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41,
 209         0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1,
 210         0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142,
 211         0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68,
 212         0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355,
 213         0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c,
 214         0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490,
 215         0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3,
 216         0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507,
 217         0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe,
 218         0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca,
 219         0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c,
 220         0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7,
 221         0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c,
 222         0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c,
 223         0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a,
 224         0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065,
 225         0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730,
 226         0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc,
 227         0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469,
 228         0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9,
 229         0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c,
 230         0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765,
 231         0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83,
 232         0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387,
 233         0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973,
 234         0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47
 235 };
 236 
 237 /**
 238  * nau8825_sema_acquire - acquire the semaphore of nau88l25
 239  * @nau8825:  component to register the codec private data with
 240  * @timeout: how long in jiffies to wait before failure or zero to wait
 241  * until release
 242  *
 243  * Attempts to acquire the semaphore with number of jiffies. If no more
 244  * tasks are allowed to acquire the semaphore, calling this function will
 245  * put the task to sleep. If the semaphore is not released within the
 246  * specified number of jiffies, this function returns.
 247  * If the semaphore is not released within the specified number of jiffies,
 248  * this function returns -ETIME. If the sleep is interrupted by a signal,
 249  * this function will return -EINTR. It returns 0 if the semaphore was
 250  * acquired successfully.
 251  *
 252  * Acquires the semaphore without jiffies. Try to acquire the semaphore
 253  * atomically. Returns 0 if the semaphore has been acquired successfully
 254  * or 1 if it it cannot be acquired.
 255  */
 256 static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
 257 {
 258         int ret;
 259 
 260         if (timeout) {
 261                 ret = down_timeout(&nau8825->xtalk_sem, timeout);
 262                 if (ret < 0)
 263                         dev_warn(nau8825->dev, "Acquire semaphore timeout\n");
 264         } else {
 265                 ret = down_trylock(&nau8825->xtalk_sem);
 266                 if (ret)
 267                         dev_warn(nau8825->dev, "Acquire semaphore fail\n");
 268         }
 269 
 270         return ret;
 271 }
 272 
 273 /**
 274  * nau8825_sema_release - release the semaphore of nau88l25
 275  * @nau8825:  component to register the codec private data with
 276  *
 277  * Release the semaphore which may be called from any context and
 278  * even by tasks which have never called down().
 279  */
 280 static inline void nau8825_sema_release(struct nau8825 *nau8825)
 281 {
 282         up(&nau8825->xtalk_sem);
 283 }
 284 
 285 /**
 286  * nau8825_sema_reset - reset the semaphore for nau88l25
 287  * @nau8825:  component to register the codec private data with
 288  *
 289  * Reset the counter of the semaphore. Call this function to restart
 290  * a new round task management.
 291  */
 292 static inline void nau8825_sema_reset(struct nau8825 *nau8825)
 293 {
 294         nau8825->xtalk_sem.count = 1;
 295 }
 296 
 297 /**
 298  * Ramp up the headphone volume change gradually to target level.
 299  *
 300  * @nau8825:  component to register the codec private data with
 301  * @vol_from: the volume to start up
 302  * @vol_to: the target volume
 303  * @step: the volume span to move on
 304  *
 305  * The headphone volume is from 0dB to minimum -54dB and -1dB per step.
 306  * If the volume changes sharp, there is a pop noise heard in headphone. We
 307  * provide the function to ramp up the volume up or down by delaying 10ms
 308  * per step.
 309  */
 310 static void nau8825_hpvol_ramp(struct nau8825 *nau8825,
 311         unsigned int vol_from, unsigned int vol_to, unsigned int step)
 312 {
 313         unsigned int value, volume, ramp_up, from, to;
 314 
 315         if (vol_from == vol_to || step == 0) {
 316                 return;
 317         } else if (vol_from < vol_to) {
 318                 ramp_up = true;
 319                 from = vol_from;
 320                 to = vol_to;
 321         } else {
 322                 ramp_up = false;
 323                 from = vol_to;
 324                 to = vol_from;
 325         }
 326         /* only handle volume from 0dB to minimum -54dB */
 327         if (to > NAU8825_HP_VOL_MIN)
 328                 to = NAU8825_HP_VOL_MIN;
 329 
 330         for (volume = from; volume < to; volume += step) {
 331                 if (ramp_up)
 332                         value = volume;
 333                 else
 334                         value = to - volume + from;
 335                 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
 336                         NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
 337                         (value << NAU8825_HPL_VOL_SFT) | value);
 338                 usleep_range(10000, 10500);
 339         }
 340         if (ramp_up)
 341                 value = to;
 342         else
 343                 value = from;
 344         regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
 345                 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
 346                 (value << NAU8825_HPL_VOL_SFT) | value);
 347 }
 348 
 349 /**
 350  * Computes log10 of a value; the result is round off to 3 decimal. This func-
 351  * tion takes reference to dvb-math. The source code locates as the following.
 352  * Linux/drivers/media/dvb-core/dvb_math.c
 353  * @value:  input for log10
 354  *
 355  * return log10(value) * 1000
 356  */
 357 static u32 nau8825_intlog10_dec3(u32 value)
 358 {
 359         u32 msb, logentry, significand, interpolation, log10val;
 360         u64 log2val;
 361 
 362         /* first detect the msb (count begins at 0) */
 363         msb = fls(value) - 1;
 364         /**
 365          *      now we use a logtable after the following method:
 366          *
 367          *      log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24
 368          *      where x = msb and therefore 1 <= y < 2
 369          *      first y is determined by shifting the value left
 370          *      so that msb is bit 31
 371          *              0x00231f56 -> 0x8C7D5800
 372          *      the result is y * 2^31 -> "significand"
 373          *      then the highest 9 bits are used for a table lookup
 374          *      the highest bit is discarded because it's always set
 375          *      the highest nine bits in our example are 100011000
 376          *      so we would use the entry 0x18
 377          */
 378         significand = value << (31 - msb);
 379         logentry = (significand >> 23) & 0xff;
 380         /**
 381          *      last step we do is interpolation because of the
 382          *      limitations of the log table the error is that part of
 383          *      the significand which isn't used for lookup then we
 384          *      compute the ratio between the error and the next table entry
 385          *      and interpolate it between the log table entry used and the
 386          *      next one the biggest error possible is 0x7fffff
 387          *      (in our example it's 0x7D5800)
 388          *      needed value for next table entry is 0x800000
 389          *      so the interpolation is
 390          *      (error / 0x800000) * (logtable_next - logtable_current)
 391          *      in the implementation the division is moved to the end for
 392          *      better accuracy there is also an overflow correction if
 393          *      logtable_next is 256
 394          */
 395         interpolation = ((significand & 0x7fffff) *
 396                 ((logtable[(logentry + 1) & 0xff] -
 397                 logtable[logentry]) & 0xffff)) >> 15;
 398 
 399         log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation);
 400         /**
 401          *      log10(x) = log2(x) * log10(2)
 402          */
 403         log10val = (log2val * LOG10_MAGIC) >> 31;
 404         /**
 405          *      the result is round off to 3 decimal
 406          */
 407         return log10val / ((1 << 24) / 1000);
 408 }
 409 
 410 /**
 411  * computes cross talk suppression sidetone gain.
 412  *
 413  * @sig_org: orignal signal level
 414  * @sig_cros: cross talk signal level
 415  *
 416  * The orignal and cross talk signal vlues need to be characterized.
 417  * Once these values have been characterized, this sidetone value
 418  * can be converted to decibel with the equation below.
 419  * sidetone = 20 * log (original signal level / crosstalk signal level)
 420  *
 421  * return cross talk sidetone gain
 422  */
 423 static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros)
 424 {
 425         u32 gain, sidetone;
 426 
 427         if (WARN_ON(sig_org == 0 || sig_cros == 0))
 428                 return 0;
 429 
 430         sig_org = nau8825_intlog10_dec3(sig_org);
 431         sig_cros = nau8825_intlog10_dec3(sig_cros);
 432         if (sig_org >= sig_cros)
 433                 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT;
 434         else
 435                 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT;
 436         sidetone = SIDETONE_BASE - gain * 2;
 437         sidetone /= 1000;
 438 
 439         return sidetone;
 440 }
 441 
 442 static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg)
 443 {
 444         int index;
 445 
 446         for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++)
 447                 if (nau8825_xtalk_baktab[index].reg == reg)
 448                         return index;
 449         return -EINVAL;
 450 }
 451 
 452 static void nau8825_xtalk_backup(struct nau8825 *nau8825)
 453 {
 454         int i;
 455 
 456         if (nau8825->xtalk_baktab_initialized)
 457                 return;
 458 
 459         /* Backup some register values to backup table */
 460         for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++)
 461                 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
 462                                 &nau8825_xtalk_baktab[i].def);
 463 
 464         nau8825->xtalk_baktab_initialized = true;
 465 }
 466 
 467 static void nau8825_xtalk_restore(struct nau8825 *nau8825, bool cause_cancel)
 468 {
 469         int i, volume;
 470 
 471         if (!nau8825->xtalk_baktab_initialized)
 472                 return;
 473 
 474         /* Restore register values from backup table; When the driver restores
 475          * the headphone volume in XTALK_DONE state, it needs recover to
 476          * original level gradually with 3dB per step for less pop noise.
 477          * Otherwise, the restore should do ASAP.
 478          */
 479         for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) {
 480                 if (!cause_cancel && nau8825_xtalk_baktab[i].reg ==
 481                         NAU8825_REG_HSVOL_CTRL) {
 482                         /* Ramping up the volume change to reduce pop noise */
 483                         volume = nau8825_xtalk_baktab[i].def &
 484                                 NAU8825_HPR_VOL_MASK;
 485                         nau8825_hpvol_ramp(nau8825, 0, volume, 3);
 486                         continue;
 487                 }
 488                 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
 489                                 nau8825_xtalk_baktab[i].def);
 490         }
 491 
 492         nau8825->xtalk_baktab_initialized = false;
 493 }
 494 
 495 static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825)
 496 {
 497         /* Enable power of DAC path */
 498         regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
 499                 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
 500                 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK |
 501                 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR |
 502                 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC |
 503                 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK);
 504         /* Prevent startup click by letting charge pump to ramp up and
 505          * change bump enable
 506          */
 507         regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
 508                 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN,
 509                 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN);
 510         /* Enable clock sync of DAC and DAC clock */
 511         regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
 512                 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN |
 513                 NAU8825_RDAC_FS_BCLK_ENB,
 514                 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN);
 515         /* Power up output driver with 2 stage */
 516         regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
 517                 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
 518                 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L,
 519                 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
 520                 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L);
 521         regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
 522                 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L,
 523                 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L);
 524         /* HP outputs not shouted to ground  */
 525         regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
 526                 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0);
 527         /* Enable HP boost driver */
 528         regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
 529                 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS);
 530         /* Enable class G compare path to supply 1.8V or 0.9V. */
 531         regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL,
 532                 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN,
 533                 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN);
 534 }
 535 
 536 static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825)
 537 {
 538         /* Power up left ADC and raise 5dB than Vmid for Vref  */
 539         regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
 540                 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK,
 541                 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB);
 542 }
 543 
 544 static void nau8825_xtalk_clock(struct nau8825 *nau8825)
 545 {
 546         /* Recover FLL default value */
 547         regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0);
 548         regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126);
 549         regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008);
 550         regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010);
 551         regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0);
 552         regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000);
 553         /* Enable internal VCO clock for detection signal generated */
 554         regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
 555                 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
 556         regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
 557                 NAU8825_DCO_EN);
 558         /* Given specific clock frequency of internal clock to
 559          * generate signal.
 560          */
 561         regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
 562                 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
 563         regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
 564                 NAU8825_FLL_RATIO_MASK, 0x10);
 565 }
 566 
 567 static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
 568 {
 569         int volume, index;
 570 
 571         /* Backup those registers changed by cross talk detection */
 572         nau8825_xtalk_backup(nau8825);
 573         /* Config IIS as master to output signal by codec */
 574         regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
 575                 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
 576                 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
 577                 (0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1);
 578         /* Ramp up headphone volume to 0dB to get better performance and
 579          * avoid pop noise in headphone.
 580          */
 581         index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL);
 582         if (index != -EINVAL) {
 583                 volume = nau8825_xtalk_baktab[index].def &
 584                                 NAU8825_HPR_VOL_MASK;
 585                 nau8825_hpvol_ramp(nau8825, volume, 0, 3);
 586         }
 587         nau8825_xtalk_clock(nau8825);
 588         nau8825_xtalk_prepare_dac(nau8825);
 589         nau8825_xtalk_prepare_adc(nau8825);
 590         /* Config channel path and digital gain */
 591         regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
 592                 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK,
 593                 NAU8825_DACL_CH_SEL_L | 0xab);
 594         regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
 595                 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK,
 596                 NAU8825_DACR_CH_SEL_R | 0xab);
 597         /* Config cross talk parameters and generate the 23Hz sine wave with
 598          * 1/16 full scale of signal level for impedance measurement.
 599          */
 600         regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
 601                 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK |
 602                 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK,
 603                 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th |
 604                 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN);
 605         /* RMS intrruption enable */
 606         regmap_update_bits(nau8825->regmap,
 607                 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0);
 608         /* Power up left and right DAC */
 609         regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
 610                 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
 611 }
 612 
 613 static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825)
 614 {
 615         /* Disable HP boost driver */
 616         regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
 617                 NAU8825_HP_BOOST_DIS, 0);
 618         /* HP outputs shouted to ground  */
 619         regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
 620                 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
 621                 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
 622         /* Power down left and right DAC */
 623         regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
 624                 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
 625                 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
 626         /* Enable the TESTDAC and  disable L/R HP impedance */
 627         regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
 628                 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP |
 629                 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
 630         /* Power down output driver with 2 stage */
 631         regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
 632                 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0);
 633         regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
 634                 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
 635                 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0);
 636         /* Disable clock sync of DAC and DAC clock */
 637         regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
 638                 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0);
 639         /* Disable charge pump ramp up function and change bump */
 640         regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
 641                 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0);
 642         /* Disable power of DAC path */
 643         regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
 644                 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
 645                 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0);
 646         if (!nau8825->irq)
 647                 regmap_update_bits(nau8825->regmap,
 648                         NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
 649 }
 650 
 651 static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825)
 652 {
 653         /* Power down left ADC and restore voltage to Vmid */
 654         regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
 655                 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0);
 656 }
 657 
 658 static void nau8825_xtalk_clean(struct nau8825 *nau8825, bool cause_cancel)
 659 {
 660         /* Enable internal VCO needed for interruptions */
 661         nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
 662         nau8825_xtalk_clean_dac(nau8825);
 663         nau8825_xtalk_clean_adc(nau8825);
 664         /* Clear cross talk parameters and disable */
 665         regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0);
 666         /* RMS intrruption disable */
 667         regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK,
 668                 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
 669         /* Recover default value for IIS */
 670         regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
 671                 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
 672                 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
 673         /* Restore value of specific register for cross talk */
 674         nau8825_xtalk_restore(nau8825, cause_cancel);
 675 }
 676 
 677 static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol)
 678 {
 679         /* Apply ADC volume for better cross talk performance */
 680         regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL,
 681                                 NAU8825_ADC_DIG_VOL_MASK, vol);
 682         /* Disables JKTIP(HPL) DAC channel for right to left measurement.
 683          * Do it before sending signal in order to erase pop noise.
 684          */
 685         regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
 686                 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN,
 687                 NAU8825_BIAS_TESTDACL_EN);
 688         switch (nau8825->xtalk_state) {
 689         case NAU8825_XTALK_HPR_R2L:
 690                 /* Enable right headphone impedance */
 691                 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
 692                         NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
 693                         NAU8825_BIAS_HPR_IMP);
 694                 break;
 695         case NAU8825_XTALK_HPL_R2L:
 696                 /* Enable left headphone impedance */
 697                 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
 698                         NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
 699                         NAU8825_BIAS_HPL_IMP);
 700                 break;
 701         default:
 702                 break;
 703         }
 704         msleep(100);
 705         /* Impedance measurement mode enable */
 706         regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
 707                                 NAU8825_IMM_EN, NAU8825_IMM_EN);
 708 }
 709 
 710 static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825)
 711 {
 712         /* Impedance measurement mode disable */
 713         regmap_update_bits(nau8825->regmap,
 714                 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0);
 715 }
 716 
 717 /* The cross talk measurement function can reduce cross talk across the
 718  * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal
 719  * level to determine what cross talk reduction gain is. This system works by
 720  * sending a 23Hz -24dBV sine wave into the headset output DAC and through
 721  * the PGA. The output of the PGA is then connected to an internal current
 722  * sense which measures the attenuated 23Hz signal and passing the output to
 723  * an ADC which converts the measurement to a binary code. With two separated
 724  * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data
 725  * can be separated read in IMM_RMS_L for HSR and HSL after each measurement.
 726  * Thus, the measurement function has four states to complete whole sequence.
 727  * 1. Prepare state : Prepare the resource for detection and transfer to HPR
 728  *     IMM stat to make JKR1(HPR) impedance measure.
 729  * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer
 730  *     to HPL IMM state to make JKTIP(HPL) impedance measure.
 731  * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and
 732  *     transfer to IMM state to determine suppression sidetone gain.
 733  * 4. IMM state : Computes cross talk suppression sidetone gain with orignal
 734  *     and cross talk signal level. Apply this gain and then restore codec
 735  *     configuration. Then transfer to Done state for ending.
 736  */
 737 static void nau8825_xtalk_measure(struct nau8825 *nau8825)
 738 {
 739         u32 sidetone;
 740 
 741         switch (nau8825->xtalk_state) {
 742         case NAU8825_XTALK_PREPARE:
 743                 /* In prepare state, set up clock, intrruption, DAC path, ADC
 744                  * path and cross talk detection parameters for preparation.
 745                  */
 746                 nau8825_xtalk_prepare(nau8825);
 747                 msleep(280);
 748                 /* Trigger right headphone impedance detection */
 749                 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L;
 750                 nau8825_xtalk_imm_start(nau8825, 0x00d2);
 751                 break;
 752         case NAU8825_XTALK_HPR_R2L:
 753                 /* In right headphone IMM state, read out right headphone
 754                  * impedance measure result, and then start up left side.
 755                  */
 756                 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
 757                         &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
 758                 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n",
 759                         nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
 760                 /* Disable then re-enable IMM mode to update */
 761                 nau8825_xtalk_imm_stop(nau8825);
 762                 /* Trigger left headphone impedance detection */
 763                 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L;
 764                 nau8825_xtalk_imm_start(nau8825, 0x00ff);
 765                 break;
 766         case NAU8825_XTALK_HPL_R2L:
 767                 /* In left headphone IMM state, read out left headphone
 768                  * impedance measure result, and delay some time to wait
 769                  * detection sine wave output finish. Then, we can calculate
 770                  * the cross talk suppresstion side tone according to the L/R
 771                  * headphone imedance.
 772                  */
 773                 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
 774                         &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
 775                 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n",
 776                         nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
 777                 nau8825_xtalk_imm_stop(nau8825);
 778                 msleep(150);
 779                 nau8825->xtalk_state = NAU8825_XTALK_IMM;
 780                 break;
 781         case NAU8825_XTALK_IMM:
 782                 /* In impedance measure state, the orignal and cross talk
 783                  * signal level vlues are ready. The side tone gain is deter-
 784                  * mined with these signal level. After all, restore codec
 785                  * configuration.
 786                  */
 787                 sidetone = nau8825_xtalk_sidetone(
 788                         nau8825->imp_rms[NAU8825_XTALK_HPR_R2L],
 789                         nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
 790                 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
 791                 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
 792                                         (sidetone << 8) | sidetone);
 793                 nau8825_xtalk_clean(nau8825, false);
 794                 nau8825->xtalk_state = NAU8825_XTALK_DONE;
 795                 break;
 796         default:
 797                 break;
 798         }
 799 }
 800 
 801 static void nau8825_xtalk_work(struct work_struct *work)
 802 {
 803         struct nau8825 *nau8825 = container_of(
 804                 work, struct nau8825, xtalk_work);
 805 
 806         nau8825_xtalk_measure(nau8825);
 807         /* To determine the cross talk side tone gain when reach
 808          * the impedance measure state.
 809          */
 810         if (nau8825->xtalk_state == NAU8825_XTALK_IMM)
 811                 nau8825_xtalk_measure(nau8825);
 812 
 813         /* Delay jack report until cross talk detection process
 814          * completed. It can avoid application to do playback
 815          * preparation before cross talk detection is still working.
 816          * Meanwhile, the protection of the cross talk detection
 817          * is released.
 818          */
 819         if (nau8825->xtalk_state == NAU8825_XTALK_DONE) {
 820                 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event,
 821                                 nau8825->xtalk_event_mask);
 822                 nau8825_sema_release(nau8825);
 823                 nau8825->xtalk_protect = false;
 824         }
 825 }
 826 
 827 static void nau8825_xtalk_cancel(struct nau8825 *nau8825)
 828 {
 829         /* If the crosstalk is eanbled and the process is on going,
 830          * the driver forces to cancel the crosstalk task and
 831          * restores the configuration to original status.
 832          */
 833         if (nau8825->xtalk_enable && nau8825->xtalk_state !=
 834                 NAU8825_XTALK_DONE) {
 835                 cancel_work_sync(&nau8825->xtalk_work);
 836                 nau8825_xtalk_clean(nau8825, true);
 837         }
 838         /* Reset parameters for cross talk suppression function */
 839         nau8825_sema_reset(nau8825);
 840         nau8825->xtalk_state = NAU8825_XTALK_DONE;
 841         nau8825->xtalk_protect = false;
 842 }
 843 
 844 static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
 845 {
 846         switch (reg) {
 847         case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
 848         case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
 849         case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
 850         case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
 851         case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
 852         case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
 853         case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
 854         case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
 855         case NAU8825_REG_MISC_CTRL:
 856         case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
 857         case NAU8825_REG_BIAS_ADJ:
 858         case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
 859         case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
 860         case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
 861         case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
 862                 return true;
 863         default:
 864                 return false;
 865         }
 866 
 867 }
 868 
 869 static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
 870 {
 871         switch (reg) {
 872         case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
 873         case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
 874         case NAU8825_REG_INTERRUPT_MASK:
 875         case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
 876         case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
 877         case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
 878         case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
 879         case NAU8825_REG_IMM_MODE_CTRL:
 880         case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
 881         case NAU8825_REG_MISC_CTRL:
 882         case NAU8825_REG_BIAS_ADJ:
 883         case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
 884         case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
 885         case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
 886         case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
 887                 return true;
 888         default:
 889                 return false;
 890         }
 891 }
 892 
 893 static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
 894 {
 895         switch (reg) {
 896         case NAU8825_REG_RESET:
 897         case NAU8825_REG_IRQ_STATUS:
 898         case NAU8825_REG_INT_CLR_KEY_STATUS:
 899         case NAU8825_REG_IMM_RMS_L:
 900         case NAU8825_REG_IMM_RMS_R:
 901         case NAU8825_REG_I2C_DEVICE_ID:
 902         case NAU8825_REG_SARDOUT_RAM_STATUS:
 903         case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
 904         case NAU8825_REG_GENERAL_STATUS:
 905         case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10:
 906                 return true;
 907         default:
 908                 return false;
 909         }
 910 }
 911 
 912 static int nau8825_adc_event(struct snd_soc_dapm_widget *w,
 913                 struct snd_kcontrol *kcontrol, int event)
 914 {
 915         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 916         struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
 917 
 918         switch (event) {
 919         case SND_SOC_DAPM_POST_PMU:
 920                 msleep(125);
 921                 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
 922                         NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
 923                 break;
 924         case SND_SOC_DAPM_POST_PMD:
 925                 if (!nau8825->irq)
 926                         regmap_update_bits(nau8825->regmap,
 927                                 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
 928                 break;
 929         default:
 930                 return -EINVAL;
 931         }
 932 
 933         return 0;
 934 }
 935 
 936 static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
 937         struct snd_kcontrol *kcontrol, int event)
 938 {
 939         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 940         struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
 941 
 942         switch (event) {
 943         case SND_SOC_DAPM_POST_PMU:
 944                 /* Prevent startup click by letting charge pump to ramp up */
 945                 msleep(10);
 946                 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
 947                         NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
 948                 break;
 949         case SND_SOC_DAPM_PRE_PMD:
 950                 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
 951                         NAU8825_JAMNODCLOW, 0);
 952                 break;
 953         default:
 954                 return -EINVAL;
 955         }
 956 
 957         return 0;
 958 }
 959 
 960 static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
 961         struct snd_kcontrol *kcontrol, int event)
 962 {
 963         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 964         struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
 965 
 966         switch (event) {
 967         case SND_SOC_DAPM_PRE_PMU:
 968                 /* Disables the TESTDAC to let DAC signal pass through. */
 969                 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
 970                         NAU8825_BIAS_TESTDAC_EN, 0);
 971                 break;
 972         case SND_SOC_DAPM_POST_PMD:
 973                 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
 974                         NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
 975                 break;
 976         default:
 977                 return -EINVAL;
 978         }
 979 
 980         return 0;
 981 }
 982 
 983 static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol,
 984                                      struct snd_ctl_elem_value *ucontrol)
 985 {
 986         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 987         struct soc_bytes_ext *params = (void *)kcontrol->private_value;
 988 
 989         if (!component->regmap)
 990                 return -EINVAL;
 991 
 992         regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1,
 993                 ucontrol->value.bytes.data, params->max);
 994         return 0;
 995 }
 996 
 997 static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol,
 998                                      struct snd_ctl_elem_value *ucontrol)
 999 {
1000         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1001         struct soc_bytes_ext *params = (void *)kcontrol->private_value;
1002         void *data;
1003 
1004         if (!component->regmap)
1005                 return -EINVAL;
1006 
1007         data = kmemdup(ucontrol->value.bytes.data,
1008                 params->max, GFP_KERNEL | GFP_DMA);
1009         if (!data)
1010                 return -ENOMEM;
1011 
1012         regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1013                 NAU8825_BIQ_WRT_EN, 0);
1014         regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1,
1015                 data, params->max);
1016         regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1017                 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN);
1018 
1019         kfree(data);
1020         return 0;
1021 }
1022 
1023 static const char * const nau8825_biq_path[] = {
1024         "ADC", "DAC"
1025 };
1026 
1027 static const struct soc_enum nau8825_biq_path_enum =
1028         SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT,
1029                 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path);
1030 
1031 static const char * const nau8825_adc_decimation[] = {
1032         "32", "64", "128", "256"
1033 };
1034 
1035 static const struct soc_enum nau8825_adc_decimation_enum =
1036         SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
1037                 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
1038 
1039 static const char * const nau8825_dac_oversampl[] = {
1040         "64", "256", "128", "", "32"
1041 };
1042 
1043 static const struct soc_enum nau8825_dac_oversampl_enum =
1044         SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
1045                 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
1046 
1047 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
1048 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
1049 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
1050 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
1051 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
1052 
1053 static const struct snd_kcontrol_new nau8825_controls[] = {
1054         SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1055                 0, 0xff, 0, adc_vol_tlv),
1056         SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1057                 12, 8, 0x0f, 0, sidetone_vol_tlv),
1058         SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
1059                 6, 0, 0x3f, 1, dac_vol_tlv),
1060         SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
1061                 8, 37, 0, fepga_gain_tlv),
1062         SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
1063                 0, 8, 0xff, 0, crosstalk_vol_tlv),
1064 
1065         SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
1066         SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
1067         /* programmable biquad filter */
1068         SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum),
1069         SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
1070                   nau8825_biq_coeff_get, nau8825_biq_coeff_put),
1071 };
1072 
1073 /* DAC Mux 0x33[9] and 0x34[9] */
1074 static const char * const nau8825_dac_src[] = {
1075         "DACL", "DACR",
1076 };
1077 
1078 static SOC_ENUM_SINGLE_DECL(
1079         nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
1080         NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
1081 
1082 static SOC_ENUM_SINGLE_DECL(
1083         nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
1084         NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
1085 
1086 static const struct snd_kcontrol_new nau8825_dacl_mux =
1087         SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
1088 
1089 static const struct snd_kcontrol_new nau8825_dacr_mux =
1090         SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
1091 
1092 
1093 static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
1094         SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
1095                 15, 1),
1096 
1097         SND_SOC_DAPM_INPUT("MIC"),
1098         SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
1099 
1100         SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
1101                 NULL, 0),
1102 
1103         SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0,
1104                 nau8825_adc_event, SND_SOC_DAPM_POST_PMU |
1105                 SND_SOC_DAPM_POST_PMD),
1106         SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
1107         SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
1108                 0),
1109 
1110         /* ADC for button press detection. A dapm supply widget is used to
1111          * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
1112          * during suspend.
1113          */
1114         SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
1115                 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
1116 
1117         SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
1118         SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
1119         SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
1120         SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
1121 
1122         SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
1123                 NAU8825_ENABLE_DACR_SFT, 0),
1124         SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
1125                 NAU8825_ENABLE_DACL_SFT, 0),
1126         SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
1127 
1128         SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
1129         SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
1130 
1131         SND_SOC_DAPM_PGA_S("HP amp L", 0,
1132                 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
1133         SND_SOC_DAPM_PGA_S("HP amp R", 0,
1134                 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
1135 
1136         SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
1137                 nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
1138                 SND_SOC_DAPM_PRE_PMD),
1139 
1140         SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
1141                 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
1142         SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
1143                 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
1144         SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
1145                 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
1146         SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
1147                 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
1148         SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
1149                 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
1150         SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
1151                 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
1152 
1153         SND_SOC_DAPM_PGA_S("Output DACL", 7,
1154                 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event,
1155                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1156         SND_SOC_DAPM_PGA_S("Output DACR", 7,
1157                 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event,
1158                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1159 
1160         /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
1161         SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
1162                 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
1163         SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
1164                 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
1165 
1166         /* High current HPOL/R boost driver */
1167         SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
1168                 NAU8825_REG_BOOST, 9, 1, NULL, 0),
1169 
1170         /* Class G operation control*/
1171         SND_SOC_DAPM_PGA_S("Class G", 10,
1172                 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
1173 
1174         SND_SOC_DAPM_OUTPUT("HPOL"),
1175         SND_SOC_DAPM_OUTPUT("HPOR"),
1176 };
1177 
1178 static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
1179         {"Frontend PGA", NULL, "MIC"},
1180         {"ADC", NULL, "Frontend PGA"},
1181         {"ADC", NULL, "ADC Clock"},
1182         {"ADC", NULL, "ADC Power"},
1183         {"AIFTX", NULL, "ADC"},
1184 
1185         {"DDACL", NULL, "Playback"},
1186         {"DDACR", NULL, "Playback"},
1187         {"DDACL", NULL, "DDAC Clock"},
1188         {"DDACR", NULL, "DDAC Clock"},
1189         {"DACL Mux", "DACL", "DDACL"},
1190         {"DACL Mux", "DACR", "DDACR"},
1191         {"DACR Mux", "DACL", "DDACL"},
1192         {"DACR Mux", "DACR", "DDACR"},
1193         {"HP amp L", NULL, "DACL Mux"},
1194         {"HP amp R", NULL, "DACR Mux"},
1195         {"Charge Pump", NULL, "HP amp L"},
1196         {"Charge Pump", NULL, "HP amp R"},
1197         {"ADACL", NULL, "Charge Pump"},
1198         {"ADACR", NULL, "Charge Pump"},
1199         {"ADACL Clock", NULL, "ADACL"},
1200         {"ADACR Clock", NULL, "ADACR"},
1201         {"Output Driver L Stage 1", NULL, "ADACL Clock"},
1202         {"Output Driver R Stage 1", NULL, "ADACR Clock"},
1203         {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
1204         {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
1205         {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
1206         {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
1207         {"Output DACL", NULL, "Output Driver L Stage 3"},
1208         {"Output DACR", NULL, "Output Driver R Stage 3"},
1209         {"HPOL Pulldown", NULL, "Output DACL"},
1210         {"HPOR Pulldown", NULL, "Output DACR"},
1211         {"HP Boost Driver", NULL, "HPOL Pulldown"},
1212         {"HP Boost Driver", NULL, "HPOR Pulldown"},
1213         {"Class G", NULL, "HP Boost Driver"},
1214         {"HPOL", NULL, "Class G"},
1215         {"HPOR", NULL, "Class G"},
1216 };
1217 
1218 static int nau8825_clock_check(struct nau8825 *nau8825,
1219         int stream, int rate, int osr)
1220 {
1221         int osrate;
1222 
1223         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1224                 if (osr >= ARRAY_SIZE(osr_dac_sel))
1225                         return -EINVAL;
1226                 osrate = osr_dac_sel[osr].osr;
1227         } else {
1228                 if (osr >= ARRAY_SIZE(osr_adc_sel))
1229                         return -EINVAL;
1230                 osrate = osr_adc_sel[osr].osr;
1231         }
1232 
1233         if (!osrate || rate * osr > CLK_DA_AD_MAX) {
1234                 dev_err(nau8825->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n");
1235                 return -EINVAL;
1236         }
1237 
1238         return 0;
1239 }
1240 
1241 static int nau8825_hw_params(struct snd_pcm_substream *substream,
1242                                 struct snd_pcm_hw_params *params,
1243                                 struct snd_soc_dai *dai)
1244 {
1245         struct snd_soc_component *component = dai->component;
1246         struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
1247         unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div;
1248 
1249         nau8825_sema_acquire(nau8825, 3 * HZ);
1250 
1251         /* CLK_DAC or CLK_ADC = OSR * FS
1252          * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
1253          * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
1254          * values must be selected such that the maximum frequency is less
1255          * than 6.144 MHz.
1256          */
1257         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1258                 regmap_read(nau8825->regmap, NAU8825_REG_DAC_CTRL1, &osr);
1259                 osr &= NAU8825_DAC_OVERSAMPLE_MASK;
1260                 if (nau8825_clock_check(nau8825, substream->stream,
1261                         params_rate(params), osr)) {
1262                         nau8825_sema_release(nau8825);
1263                         return -EINVAL;
1264                 }
1265                 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1266                         NAU8825_CLK_DAC_SRC_MASK,
1267                         osr_dac_sel[osr].clk_src << NAU8825_CLK_DAC_SRC_SFT);
1268         } else {
1269                 regmap_read(nau8825->regmap, NAU8825_REG_ADC_RATE, &osr);
1270                 osr &= NAU8825_ADC_SYNC_DOWN_MASK;
1271                 if (nau8825_clock_check(nau8825, substream->stream,
1272                         params_rate(params), osr)) {
1273                         nau8825_sema_release(nau8825);
1274                         return -EINVAL;
1275                 }
1276                 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1277                         NAU8825_CLK_ADC_SRC_MASK,
1278                         osr_adc_sel[osr].clk_src << NAU8825_CLK_ADC_SRC_SFT);
1279         }
1280 
1281         /* make BCLK and LRC divde configuration if the codec as master. */
1282         regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, &ctrl_val);
1283         if (ctrl_val & NAU8825_I2S_MS_MASTER) {
1284                 /* get the bclk and fs ratio */
1285                 bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
1286                 if (bclk_fs <= 32)
1287                         bclk_div = 2;
1288                 else if (bclk_fs <= 64)
1289                         bclk_div = 1;
1290                 else if (bclk_fs <= 128)
1291                         bclk_div = 0;
1292                 else {
1293                         nau8825_sema_release(nau8825);
1294                         return -EINVAL;
1295                 }
1296                 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1297                         NAU8825_I2S_LRC_DIV_MASK | NAU8825_I2S_BLK_DIV_MASK,
1298                         ((bclk_div + 1) << NAU8825_I2S_LRC_DIV_SFT) | bclk_div);
1299         }
1300 
1301         switch (params_width(params)) {
1302         case 16:
1303                 val_len |= NAU8825_I2S_DL_16;
1304                 break;
1305         case 20:
1306                 val_len |= NAU8825_I2S_DL_20;
1307                 break;
1308         case 24:
1309                 val_len |= NAU8825_I2S_DL_24;
1310                 break;
1311         case 32:
1312                 val_len |= NAU8825_I2S_DL_32;
1313                 break;
1314         default:
1315                 nau8825_sema_release(nau8825);
1316                 return -EINVAL;
1317         }
1318 
1319         regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1320                 NAU8825_I2S_DL_MASK, val_len);
1321 
1322         /* Release the semaphore. */
1323         nau8825_sema_release(nau8825);
1324 
1325         return 0;
1326 }
1327 
1328 static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1329 {
1330         struct snd_soc_component *component = codec_dai->component;
1331         struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
1332         unsigned int ctrl1_val = 0, ctrl2_val = 0;
1333 
1334         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1335         case SND_SOC_DAIFMT_CBM_CFM:
1336                 ctrl2_val |= NAU8825_I2S_MS_MASTER;
1337                 break;
1338         case SND_SOC_DAIFMT_CBS_CFS:
1339                 break;
1340         default:
1341                 return -EINVAL;
1342         }
1343 
1344         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1345         case SND_SOC_DAIFMT_NB_NF:
1346                 break;
1347         case SND_SOC_DAIFMT_IB_NF:
1348                 ctrl1_val |= NAU8825_I2S_BP_INV;
1349                 break;
1350         default:
1351                 return -EINVAL;
1352         }
1353 
1354         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1355         case SND_SOC_DAIFMT_I2S:
1356                 ctrl1_val |= NAU8825_I2S_DF_I2S;
1357                 break;
1358         case SND_SOC_DAIFMT_LEFT_J:
1359                 ctrl1_val |= NAU8825_I2S_DF_LEFT;
1360                 break;
1361         case SND_SOC_DAIFMT_RIGHT_J:
1362                 ctrl1_val |= NAU8825_I2S_DF_RIGTH;
1363                 break;
1364         case SND_SOC_DAIFMT_DSP_A:
1365                 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1366                 break;
1367         case SND_SOC_DAIFMT_DSP_B:
1368                 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1369                 ctrl1_val |= NAU8825_I2S_PCMB_EN;
1370                 break;
1371         default:
1372                 return -EINVAL;
1373         }
1374 
1375         nau8825_sema_acquire(nau8825, 3 * HZ);
1376 
1377         regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1378                 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
1379                 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
1380                 ctrl1_val);
1381         regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1382                 NAU8825_I2S_MS_MASK, ctrl2_val);
1383 
1384         /* Release the semaphore. */
1385         nau8825_sema_release(nau8825);
1386 
1387         return 0;
1388 }
1389 
1390 static const struct snd_soc_dai_ops nau8825_dai_ops = {
1391         .hw_params      = nau8825_hw_params,
1392         .set_fmt        = nau8825_set_dai_fmt,
1393 };
1394 
1395 #define NAU8825_RATES   SNDRV_PCM_RATE_8000_192000
1396 #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1397                          | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1398 
1399 static struct snd_soc_dai_driver nau8825_dai = {
1400         .name = "nau8825-hifi",
1401         .playback = {
1402                 .stream_name     = "Playback",
1403                 .channels_min    = 1,
1404                 .channels_max    = 2,
1405                 .rates           = NAU8825_RATES,
1406                 .formats         = NAU8825_FORMATS,
1407         },
1408         .capture = {
1409                 .stream_name     = "Capture",
1410                 .channels_min    = 1,
1411                 .channels_max    = 1,
1412                 .rates           = NAU8825_RATES,
1413                 .formats         = NAU8825_FORMATS,
1414         },
1415         .ops = &nau8825_dai_ops,
1416 };
1417 
1418 /**
1419  * nau8825_enable_jack_detect - Specify a jack for event reporting
1420  *
1421  * @component:  component to register the jack with
1422  * @jack: jack to use to report headset and button events on
1423  *
1424  * After this function has been called the headset insert/remove and button
1425  * events will be routed to the given jack.  Jack can be null to stop
1426  * reporting.
1427  */
1428 int nau8825_enable_jack_detect(struct snd_soc_component *component,
1429                                 struct snd_soc_jack *jack)
1430 {
1431         struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
1432         struct regmap *regmap = nau8825->regmap;
1433 
1434         nau8825->jack = jack;
1435 
1436         /* Ground HP Outputs[1:0], needed for headset auto detection
1437          * Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
1438          */
1439         regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1440                 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
1441                 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
1442 
1443         return 0;
1444 }
1445 EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
1446 
1447 
1448 static bool nau8825_is_jack_inserted(struct regmap *regmap)
1449 {
1450         bool active_high, is_high;
1451         int status, jkdet;
1452 
1453         regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet);
1454         active_high = jkdet & NAU8825_JACK_POLARITY;
1455         regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
1456         is_high = status & NAU8825_GPIO2JD1;
1457         /* return jack connection status according to jack insertion logic
1458          * active high or active low.
1459          */
1460         return active_high == is_high;
1461 }
1462 
1463 static void nau8825_restart_jack_detection(struct regmap *regmap)
1464 {
1465         /* this will restart the entire jack detection process including MIC/GND
1466          * switching and create interrupts. We have to go from 0 to 1 and back
1467          * to 0 to restart.
1468          */
1469         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1470                 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
1471         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1472                 NAU8825_JACK_DET_RESTART, 0);
1473 }
1474 
1475 static void nau8825_int_status_clear_all(struct regmap *regmap)
1476 {
1477         int active_irq, clear_irq, i;
1478 
1479         /* Reset the intrruption status from rightmost bit if the corres-
1480          * ponding irq event occurs.
1481          */
1482         regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
1483         for (i = 0; i < NAU8825_REG_DATA_LEN; i++) {
1484                 clear_irq = (0x1 << i);
1485                 if (active_irq & clear_irq)
1486                         regmap_write(regmap,
1487                                 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1488         }
1489 }
1490 
1491 static void nau8825_eject_jack(struct nau8825 *nau8825)
1492 {
1493         struct snd_soc_dapm_context *dapm = nau8825->dapm;
1494         struct regmap *regmap = nau8825->regmap;
1495 
1496         /* Force to cancel the cross talk detection process */
1497         nau8825_xtalk_cancel(nau8825);
1498 
1499         snd_soc_dapm_disable_pin(dapm, "SAR");
1500         snd_soc_dapm_disable_pin(dapm, "MICBIAS");
1501         /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
1502         regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1503                 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
1504         /* ground HPL/HPR, MICGRND1/2 */
1505         regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
1506 
1507         snd_soc_dapm_sync(dapm);
1508 
1509         /* Clear all interruption status */
1510         nau8825_int_status_clear_all(regmap);
1511 
1512         /* Enable the insertion interruption, disable the ejection inter-
1513          * ruption, and then bypass de-bounce circuit.
1514          */
1515         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
1516                 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS,
1517                 NAU8825_IRQ_EJECT_DIS);
1518         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1519                 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1520                 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN,
1521                 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1522                 NAU8825_IRQ_HEADSET_COMPLETE_EN);
1523         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1524                 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
1525 
1526         /* Disable ADC needed for interruptions at audo mode */
1527         regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1528                 NAU8825_ENABLE_ADC, 0);
1529 
1530         /* Close clock for jack type detection at manual mode */
1531         nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
1532 }
1533 
1534 /* Enable audo mode interruptions with internal clock. */
1535 static void nau8825_setup_auto_irq(struct nau8825 *nau8825)
1536 {
1537         struct regmap *regmap = nau8825->regmap;
1538 
1539         /* Enable headset jack type detection complete interruption and
1540          * jack ejection interruption.
1541          */
1542         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1543                 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
1544 
1545         /* Enable internal VCO needed for interruptions */
1546         nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
1547 
1548         /* Enable ADC needed for interruptions */
1549         regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1550                 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
1551 
1552         /* Chip needs one FSCLK cycle in order to generate interruptions,
1553          * as we cannot guarantee one will be provided by the system. Turning
1554          * master mode on then off enables us to generate that FSCLK cycle
1555          * with a minimum of contention on the clock bus.
1556          */
1557         regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1558                 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
1559         regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1560                 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
1561 
1562         /* Not bypass de-bounce circuit */
1563         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1564                 NAU8825_JACK_DET_DB_BYPASS, 0);
1565 
1566         /* Unmask all interruptions */
1567         regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
1568 
1569         /* Restart the jack detection process at auto mode */
1570         nau8825_restart_jack_detection(regmap);
1571 }
1572 
1573 static int nau8825_button_decode(int value)
1574 {
1575         int buttons = 0;
1576 
1577         /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
1578         if (value & BIT(0))
1579                 buttons |= SND_JACK_BTN_0;
1580         if (value & BIT(1))
1581                 buttons |= SND_JACK_BTN_1;
1582         if (value & BIT(2))
1583                 buttons |= SND_JACK_BTN_2;
1584         if (value & BIT(3))
1585                 buttons |= SND_JACK_BTN_3;
1586         if (value & BIT(4))
1587                 buttons |= SND_JACK_BTN_4;
1588         if (value & BIT(5))
1589                 buttons |= SND_JACK_BTN_5;
1590 
1591         return buttons;
1592 }
1593 
1594 static int nau8825_jack_insert(struct nau8825 *nau8825)
1595 {
1596         struct regmap *regmap = nau8825->regmap;
1597         struct snd_soc_dapm_context *dapm = nau8825->dapm;
1598         int jack_status_reg, mic_detected;
1599         int type = 0;
1600 
1601         regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
1602         mic_detected = (jack_status_reg >> 10) & 3;
1603         /* The JKSLV and JKR2 all detected in high impedance headset */
1604         if (mic_detected == 0x3)
1605                 nau8825->high_imped = true;
1606         else
1607                 nau8825->high_imped = false;
1608 
1609         switch (mic_detected) {
1610         case 0:
1611                 /* no mic */
1612                 type = SND_JACK_HEADPHONE;
1613                 break;
1614         case 1:
1615                 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
1616                 type = SND_JACK_HEADSET;
1617 
1618                 /* Unground MICGND1 */
1619                 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1620                         1 << 2);
1621                 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
1622                 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1623                         NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1624                         NAU8825_MICBIAS_JKR2);
1625                 /* Attach SARADC to MICGND1 */
1626                 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1627                         NAU8825_SAR_INPUT_MASK,
1628                         NAU8825_SAR_INPUT_JKR2);
1629 
1630                 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1631                 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1632                 snd_soc_dapm_sync(dapm);
1633                 break;
1634         case 2:
1635                 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
1636                 type = SND_JACK_HEADSET;
1637 
1638                 /* Unground MICGND2 */
1639                 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1640                         2 << 2);
1641                 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
1642                 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1643                         NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1644                         NAU8825_MICBIAS_JKSLV);
1645                 /* Attach SARADC to MICGND2 */
1646                 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1647                         NAU8825_SAR_INPUT_MASK,
1648                         NAU8825_SAR_INPUT_JKSLV);
1649 
1650                 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1651                 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1652                 snd_soc_dapm_sync(dapm);
1653                 break;
1654         case 3:
1655                 /* detect error case */
1656                 dev_err(nau8825->dev, "detection error; disable mic function\n");
1657                 type = SND_JACK_HEADPHONE;
1658                 break;
1659         }
1660 
1661         /* Leaving HPOL/R grounded after jack insert by default. They will be
1662          * ungrounded as part of the widget power up sequence at the beginning
1663          * of playback to reduce pop.
1664          */
1665         return type;
1666 }
1667 
1668 #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
1669                 SND_JACK_BTN_2 | SND_JACK_BTN_3)
1670 
1671 static irqreturn_t nau8825_interrupt(int irq, void *data)
1672 {
1673         struct nau8825 *nau8825 = (struct nau8825 *)data;
1674         struct regmap *regmap = nau8825->regmap;
1675         int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1676 
1677         if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
1678                 dev_err(nau8825->dev, "failed to read irq status\n");
1679                 return IRQ_NONE;
1680         }
1681 
1682         if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
1683                 NAU8825_JACK_EJECTION_DETECTED) {
1684 
1685                 nau8825_eject_jack(nau8825);
1686                 event_mask |= SND_JACK_HEADSET;
1687                 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
1688         } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
1689                 int key_status;
1690 
1691                 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
1692                         &key_status);
1693 
1694                 /* upper 8 bits of the register are for short pressed keys,
1695                  * lower 8 bits - for long pressed buttons
1696                  */
1697                 nau8825->button_pressed = nau8825_button_decode(
1698                         key_status >> 8);
1699 
1700                 event |= nau8825->button_pressed;
1701                 event_mask |= NAU8825_BUTTONS;
1702                 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
1703         } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
1704                 event_mask = NAU8825_BUTTONS;
1705                 clear_irq = NAU8825_KEY_RELEASE_IRQ;
1706         } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
1707                 if (nau8825_is_jack_inserted(regmap)) {
1708                         event |= nau8825_jack_insert(nau8825);
1709                         if (nau8825->xtalk_enable && !nau8825->high_imped) {
1710                                 /* Apply the cross talk suppression in the
1711                                  * headset without high impedance.
1712                                  */
1713                                 if (!nau8825->xtalk_protect) {
1714                                         /* Raise protection for cross talk de-
1715                                          * tection if no protection before.
1716                                          * The driver has to cancel the pro-
1717                                          * cess and restore changes if process
1718                                          * is ongoing when ejection.
1719                                          */
1720                                         int ret;
1721                                         nau8825->xtalk_protect = true;
1722                                         ret = nau8825_sema_acquire(nau8825, 0);
1723                                         if (ret)
1724                                                 nau8825->xtalk_protect = false;
1725                                 }
1726                                 /* Startup cross talk detection process */
1727                                 if (nau8825->xtalk_protect) {
1728                                         nau8825->xtalk_state =
1729                                                 NAU8825_XTALK_PREPARE;
1730                                         schedule_work(&nau8825->xtalk_work);
1731                                 }
1732                         } else {
1733                                 /* The cross talk suppression shouldn't apply
1734                                  * in the headset with high impedance. Thus,
1735                                  * relieve the protection raised before.
1736                                  */
1737                                 if (nau8825->xtalk_protect) {
1738                                         nau8825_sema_release(nau8825);
1739                                         nau8825->xtalk_protect = false;
1740                                 }
1741                         }
1742                 } else {
1743                         dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
1744                         nau8825_eject_jack(nau8825);
1745                 }
1746 
1747                 event_mask |= SND_JACK_HEADSET;
1748                 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
1749                 /* Record the interruption report event for driver to report
1750                  * the event later. The jack report will delay until cross
1751                  * talk detection process is done.
1752                  */
1753                 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) {
1754                         nau8825->xtalk_event = event;
1755                         nau8825->xtalk_event_mask = event_mask;
1756                 }
1757         } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) {
1758                 /* crosstalk detection enable and process on going */
1759                 if (nau8825->xtalk_enable && nau8825->xtalk_protect)
1760                         schedule_work(&nau8825->xtalk_work);
1761                 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
1762         } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) ==
1763                 NAU8825_JACK_INSERTION_DETECTED) {
1764                 /* One more step to check GPIO status directly. Thus, the
1765                  * driver can confirm the real insertion interruption because
1766                  * the intrruption at manual mode has bypassed debounce
1767                  * circuit which can get rid of unstable status.
1768                  */
1769                 if (nau8825_is_jack_inserted(regmap)) {
1770                         /* Turn off insertion interruption at manual mode */
1771                         regmap_update_bits(regmap,
1772                                 NAU8825_REG_INTERRUPT_DIS_CTRL,
1773                                 NAU8825_IRQ_INSERT_DIS,
1774                                 NAU8825_IRQ_INSERT_DIS);
1775                         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1776                                 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN);
1777                         /* Enable interruption for jack type detection at audo
1778                          * mode which can detect microphone and jack type.
1779                          */
1780                         nau8825_setup_auto_irq(nau8825);
1781                 }
1782         }
1783 
1784         if (!clear_irq)
1785                 clear_irq = active_irq;
1786         /* clears the rightmost interruption */
1787         regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1788 
1789         /* Delay jack report until cross talk detection is done. It can avoid
1790          * application to do playback preparation when cross talk detection
1791          * process is still working. Otherwise, the resource like clock and
1792          * power will be issued by them at the same time and conflict happens.
1793          */
1794         if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE)
1795                 snd_soc_jack_report(nau8825->jack, event, event_mask);
1796 
1797         return IRQ_HANDLED;
1798 }
1799 
1800 static void nau8825_setup_buttons(struct nau8825 *nau8825)
1801 {
1802         struct regmap *regmap = nau8825->regmap;
1803 
1804         regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1805                 NAU8825_SAR_TRACKING_GAIN_MASK,
1806                 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
1807         regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1808                 NAU8825_SAR_COMPARE_TIME_MASK,
1809                 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
1810         regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1811                 NAU8825_SAR_SAMPLING_TIME_MASK,
1812                 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
1813 
1814         regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1815                 NAU8825_KEYDET_LEVELS_NR_MASK,
1816                 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
1817         regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1818                 NAU8825_KEYDET_HYSTERESIS_MASK,
1819                 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
1820         regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1821                 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
1822                 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
1823 
1824         regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
1825                 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
1826         regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
1827                 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
1828         regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
1829                 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
1830         regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
1831                 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
1832 
1833         /* Enable short press and release interruptions */
1834         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1835                 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
1836                 0);
1837 }
1838 
1839 static void nau8825_init_regs(struct nau8825 *nau8825)
1840 {
1841         struct regmap *regmap = nau8825->regmap;
1842 
1843         /* Latch IIC LSB value */
1844         regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
1845         /* Enable Bias/Vmid */
1846         regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1847                 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
1848         regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
1849                 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
1850 
1851         /* VMID Tieoff */
1852         regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
1853                 NAU8825_BIAS_VMID_SEL_MASK,
1854                 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
1855         /* Disable Boost Driver, Automatic Short circuit protection enable */
1856         regmap_update_bits(regmap, NAU8825_REG_BOOST,
1857                 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1858                 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
1859                 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1860                 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
1861 
1862         regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1863                 NAU8825_JKDET_OUTPUT_EN,
1864                 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
1865         regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1866                 NAU8825_JKDET_PULL_EN,
1867                 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
1868         regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1869                 NAU8825_JKDET_PULL_UP,
1870                 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
1871         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1872                 NAU8825_JACK_POLARITY,
1873                 /* jkdet_polarity - 1  is for active-low */
1874                 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
1875 
1876         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1877                 NAU8825_JACK_INSERT_DEBOUNCE_MASK,
1878                 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
1879         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1880                 NAU8825_JACK_EJECT_DEBOUNCE_MASK,
1881                 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
1882 
1883         /* Pull up IRQ pin */
1884         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1885                 NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN,
1886                 NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN);
1887         /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1888         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
1889 
1890         regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1891                 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
1892 
1893         if (nau8825->sar_threshold_num)
1894                 nau8825_setup_buttons(nau8825);
1895 
1896         /* Default oversampling/decimations settings are unusable
1897          * (audible hiss). Set it to something better.
1898          */
1899         regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
1900                 NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN,
1901                 NAU8825_ADC_SYNC_DOWN_64);
1902         regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1903                 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64);
1904         /* Disable DACR/L power */
1905         regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
1906                 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
1907                 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
1908         /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
1909          * signal to avoid any glitches due to power up transients in both
1910          * the analog and digital DAC circuit.
1911          */
1912         regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1913                 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
1914         /* CICCLP off */
1915         regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1916                 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
1917 
1918         /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1919         regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
1920                 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1921                 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
1922                 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1923                 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
1924         /* Class G timer 64ms */
1925         regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
1926                 NAU8825_CLASSG_TIMER_MASK,
1927                 0x20 << NAU8825_CLASSG_TIMER_SFT);
1928         /* DAC clock delay 2ns, VREF */
1929         regmap_update_bits(regmap, NAU8825_REG_RDAC,
1930                 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
1931                 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
1932                 (0x3 << NAU8825_RDAC_VREF_SFT));
1933         /* Config L/R channel */
1934         regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
1935                 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L);
1936         regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
1937                 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R);
1938         /* Disable short Frame Sync detection logic */
1939         regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT,
1940                 NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET);
1941 }
1942 
1943 static const struct regmap_config nau8825_regmap_config = {
1944         .val_bits = NAU8825_REG_DATA_LEN,
1945         .reg_bits = NAU8825_REG_ADDR_LEN,
1946 
1947         .max_register = NAU8825_REG_MAX,
1948         .readable_reg = nau8825_readable_reg,
1949         .writeable_reg = nau8825_writeable_reg,
1950         .volatile_reg = nau8825_volatile_reg,
1951 
1952         .cache_type = REGCACHE_RBTREE,
1953         .reg_defaults = nau8825_reg_defaults,
1954         .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
1955 };
1956 
1957 static int nau8825_component_probe(struct snd_soc_component *component)
1958 {
1959         struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
1960         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1961 
1962         nau8825->dapm = dapm;
1963 
1964         return 0;
1965 }
1966 
1967 static void nau8825_component_remove(struct snd_soc_component *component)
1968 {
1969         struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
1970 
1971         /* Cancel and reset cross tak suppresstion detection funciton */
1972         nau8825_xtalk_cancel(nau8825);
1973 }
1974 
1975 /**
1976  * nau8825_calc_fll_param - Calculate FLL parameters.
1977  * @fll_in: external clock provided to codec.
1978  * @fs: sampling rate.
1979  * @fll_param: Pointer to structure of FLL parameters.
1980  *
1981  * Calculate FLL parameters to configure codec.
1982  *
1983  * Returns 0 for success or negative error code.
1984  */
1985 static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
1986                 struct nau8825_fll *fll_param)
1987 {
1988         u64 fvco, fvco_max;
1989         unsigned int fref, i, fvco_sel;
1990 
1991         /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
1992          * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1993          * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
1994          */
1995         for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1996                 fref = fll_in / fll_pre_scalar[i].param;
1997                 if (fref <= NAU_FREF_MAX)
1998                         break;
1999         }
2000         if (i == ARRAY_SIZE(fll_pre_scalar))
2001                 return -EINVAL;
2002         fll_param->clk_ref_div = fll_pre_scalar[i].val;
2003 
2004         /* Choose the FLL ratio based on FREF */
2005         for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
2006                 if (fref >= fll_ratio[i].param)
2007                         break;
2008         }
2009         if (i == ARRAY_SIZE(fll_ratio))
2010                 return -EINVAL;
2011         fll_param->ratio = fll_ratio[i].val;
2012 
2013         /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
2014          * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
2015          * guaranteed across the full range of operation.
2016          * FDCO = freq_out * 2 * mclk_src_scaling
2017          */
2018         fvco_max = 0;
2019         fvco_sel = ARRAY_SIZE(mclk_src_scaling);
2020         for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
2021                 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
2022                 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
2023                         fvco_max < fvco) {
2024                         fvco_max = fvco;
2025                         fvco_sel = i;
2026                 }
2027         }
2028         if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
2029                 return -EINVAL;
2030         fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
2031 
2032         /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
2033          * input based on FDCO, FREF and FLL ratio.
2034          */
2035         fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
2036         fll_param->fll_int = (fvco >> 16) & 0x3FF;
2037         fll_param->fll_frac = fvco & 0xFFFF;
2038         return 0;
2039 }
2040 
2041 static void nau8825_fll_apply(struct nau8825 *nau8825,
2042                 struct nau8825_fll *fll_param)
2043 {
2044         regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
2045                 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK,
2046                 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
2047         /* Make DSP operate at high speed for better performance. */
2048         regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
2049                 NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK,
2050                 fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT));
2051         /* FLL 16-bit fractional input */
2052         regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
2053         /* FLL 10-bit integer input */
2054         regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
2055                         NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
2056         /* FLL pre-scaler */
2057         regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
2058                         NAU8825_FLL_REF_DIV_MASK,
2059                         fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT);
2060         /* select divided VCO input */
2061         regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2062                 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF);
2063         /* Disable free-running mode */
2064         regmap_update_bits(nau8825->regmap,
2065                 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
2066         if (fll_param->fll_frac) {
2067                 /* set FLL loop filter enable and cutoff frequency at 500Khz */
2068                 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2069                         NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2070                         NAU8825_FLL_FTR_SW_MASK,
2071                         NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2072                         NAU8825_FLL_FTR_SW_FILTER);
2073                 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
2074                         NAU8825_SDM_EN | NAU8825_CUTOFF500,
2075                         NAU8825_SDM_EN | NAU8825_CUTOFF500);
2076         } else {
2077                 /* disable FLL loop filter and cutoff frequency */
2078                 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2079                         NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2080                         NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU);
2081                 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
2082                         NAU8825_SDM_EN | NAU8825_CUTOFF500, 0);
2083         }
2084 }
2085 
2086 /* freq_out must be 256*Fs in order to achieve the best performance */
2087 static int nau8825_set_pll(struct snd_soc_component *component, int pll_id, int source,
2088                 unsigned int freq_in, unsigned int freq_out)
2089 {
2090         struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
2091         struct nau8825_fll fll_param;
2092         int ret, fs;
2093 
2094         fs = freq_out / 256;
2095         ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
2096         if (ret < 0) {
2097                 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
2098                 return ret;
2099         }
2100         dev_dbg(component->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
2101                 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
2102                 fll_param.fll_int, fll_param.clk_ref_div);
2103 
2104         nau8825_fll_apply(nau8825, &fll_param);
2105         mdelay(2);
2106         regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
2107                         NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2108         return 0;
2109 }
2110 
2111 static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
2112 {
2113         int ret = 0;
2114 
2115         nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
2116         if (IS_ERR(nau8825->mclk)) {
2117                 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
2118                 return 0;
2119         }
2120 
2121         if (!nau8825->mclk_freq) {
2122                 ret = clk_prepare_enable(nau8825->mclk);
2123                 if (ret) {
2124                         dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2125                         return ret;
2126                 }
2127         }
2128 
2129         if (nau8825->mclk_freq != freq) {
2130                 freq = clk_round_rate(nau8825->mclk, freq);
2131                 ret = clk_set_rate(nau8825->mclk, freq);
2132                 if (ret) {
2133                         dev_err(nau8825->dev, "Unable to set mclk rate\n");
2134                         return ret;
2135                 }
2136                 nau8825->mclk_freq = freq;
2137         }
2138 
2139         return 0;
2140 }
2141 
2142 static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap)
2143 {
2144         regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2145                 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
2146         regmap_update_bits(regmap, NAU8825_REG_FLL6,
2147                 NAU8825_DCO_EN, 0);
2148         /* Make DSP operate as default setting for power saving. */
2149         regmap_update_bits(regmap, NAU8825_REG_FLL1,
2150                 NAU8825_ICTRL_LATCH_MASK, 0);
2151 }
2152 
2153 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
2154         unsigned int freq)
2155 {
2156         struct regmap *regmap = nau8825->regmap;
2157         int ret;
2158 
2159         switch (clk_id) {
2160         case NAU8825_CLK_DIS:
2161                 /* Clock provided externally and disable internal VCO clock */
2162                 nau8825_configure_mclk_as_sysclk(regmap);
2163                 if (nau8825->mclk_freq) {
2164                         clk_disable_unprepare(nau8825->mclk);
2165                         nau8825->mclk_freq = 0;
2166                 }
2167 
2168                 break;
2169         case NAU8825_CLK_MCLK:
2170                 /* Acquire the semaphore to synchronize the playback and
2171                  * interrupt handler. In order to avoid the playback inter-
2172                  * fered by cross talk process, the driver make the playback
2173                  * preparation halted until cross talk process finish.
2174                  */
2175                 nau8825_sema_acquire(nau8825, 3 * HZ);
2176                 nau8825_configure_mclk_as_sysclk(regmap);
2177                 /* MCLK not changed by clock tree */
2178                 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2179                         NAU8825_CLK_MCLK_SRC_MASK, 0);
2180                 /* Release the semaphore. */
2181                 nau8825_sema_release(nau8825);
2182 
2183                 ret = nau8825_mclk_prepare(nau8825, freq);
2184                 if (ret)
2185                         return ret;
2186 
2187                 break;
2188         case NAU8825_CLK_INTERNAL:
2189                 if (nau8825_is_jack_inserted(nau8825->regmap)) {
2190                         regmap_update_bits(regmap, NAU8825_REG_FLL6,
2191                                 NAU8825_DCO_EN, NAU8825_DCO_EN);
2192                         regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2193                                 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2194                         /* Decrease the VCO frequency and make DSP operate
2195                          * as default setting for power saving.
2196                          */
2197                         regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2198                                 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
2199                         regmap_update_bits(regmap, NAU8825_REG_FLL1,
2200                                 NAU8825_ICTRL_LATCH_MASK |
2201                                 NAU8825_FLL_RATIO_MASK, 0x10);
2202                         regmap_update_bits(regmap, NAU8825_REG_FLL6,
2203                                 NAU8825_SDM_EN, NAU8825_SDM_EN);
2204                 } else {
2205                         /* The clock turns off intentionally for power saving
2206                          * when no headset connected.
2207                          */
2208                         nau8825_configure_mclk_as_sysclk(regmap);
2209                         dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n");
2210                 }
2211                 if (nau8825->mclk_freq) {
2212                         clk_disable_unprepare(nau8825->mclk);
2213                         nau8825->mclk_freq = 0;
2214                 }
2215 
2216                 break;
2217         case NAU8825_CLK_FLL_MCLK:
2218                 /* Acquire the semaphore to synchronize the playback and
2219                  * interrupt handler. In order to avoid the playback inter-
2220                  * fered by cross talk process, the driver make the playback
2221                  * preparation halted until cross talk process finish.
2222                  */
2223                 nau8825_sema_acquire(nau8825, 3 * HZ);
2224                 /* Higher FLL reference input frequency can only set lower
2225                  * gain error, such as 0000 for input reference from MCLK
2226                  * 12.288Mhz.
2227                  */
2228                 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2229                         NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2230                         NAU8825_FLL_CLK_SRC_MCLK | 0);
2231                 /* Release the semaphore. */
2232                 nau8825_sema_release(nau8825);
2233 
2234                 ret = nau8825_mclk_prepare(nau8825, freq);
2235                 if (ret)
2236                         return ret;
2237 
2238                 break;
2239         case NAU8825_CLK_FLL_BLK:
2240                 /* Acquire the semaphore to synchronize the playback and
2241                  * interrupt handler. In order to avoid the playback inter-
2242                  * fered by cross talk process, the driver make the playback
2243                  * preparation halted until cross talk process finish.
2244                  */
2245                 nau8825_sema_acquire(nau8825, 3 * HZ);
2246                 /* If FLL reference input is from low frequency source,
2247                  * higher error gain can apply such as 0xf which has
2248                  * the most sensitive gain error correction threshold,
2249                  * Therefore, FLL has the most accurate DCO to
2250                  * target frequency.
2251                  */
2252                 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2253                         NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2254                         NAU8825_FLL_CLK_SRC_BLK |
2255                         (0xf << NAU8825_GAIN_ERR_SFT));
2256                 /* Release the semaphore. */
2257                 nau8825_sema_release(nau8825);
2258 
2259                 if (nau8825->mclk_freq) {
2260                         clk_disable_unprepare(nau8825->mclk);
2261                         nau8825->mclk_freq = 0;
2262                 }
2263 
2264                 break;
2265         case NAU8825_CLK_FLL_FS:
2266                 /* Acquire the semaphore to synchronize the playback and
2267                  * interrupt handler. In order to avoid the playback inter-
2268                  * fered by cross talk process, the driver make the playback
2269                  * preparation halted until cross talk process finish.
2270                  */
2271                 nau8825_sema_acquire(nau8825, 3 * HZ);
2272                 /* If FLL reference input is from low frequency source,
2273                  * higher error gain can apply such as 0xf which has
2274                  * the most sensitive gain error correction threshold,
2275                  * Therefore, FLL has the most accurate DCO to
2276                  * target frequency.
2277                  */
2278                 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2279                         NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2280                         NAU8825_FLL_CLK_SRC_FS |
2281                         (0xf << NAU8825_GAIN_ERR_SFT));
2282                 /* Release the semaphore. */
2283                 nau8825_sema_release(nau8825);
2284 
2285                 if (nau8825->mclk_freq) {
2286                         clk_disable_unprepare(nau8825->mclk);
2287                         nau8825->mclk_freq = 0;
2288                 }
2289 
2290                 break;
2291         default:
2292                 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
2293                 return -EINVAL;
2294         }
2295 
2296         dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
2297                 clk_id);
2298         return 0;
2299 }
2300 
2301 static int nau8825_set_sysclk(struct snd_soc_component *component, int clk_id,
2302         int source, unsigned int freq, int dir)
2303 {
2304         struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
2305 
2306         return nau8825_configure_sysclk(nau8825, clk_id, freq);
2307 }
2308 
2309 static int nau8825_resume_setup(struct nau8825 *nau8825)
2310 {
2311         struct regmap *regmap = nau8825->regmap;
2312 
2313         /* Close clock when jack type detection at manual mode */
2314         nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
2315 
2316         /* Clear all interruption status */
2317         nau8825_int_status_clear_all(regmap);
2318 
2319         /* Enable both insertion and ejection interruptions, and then
2320          * bypass de-bounce circuit.
2321          */
2322         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
2323                 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN |
2324                 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN,
2325                 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN);
2326         regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
2327                 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
2328         regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
2329                 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0);
2330 
2331         return 0;
2332 }
2333 
2334 static int nau8825_set_bias_level(struct snd_soc_component *component,
2335                                    enum snd_soc_bias_level level)
2336 {
2337         struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
2338         int ret;
2339 
2340         switch (level) {
2341         case SND_SOC_BIAS_ON:
2342                 break;
2343 
2344         case SND_SOC_BIAS_PREPARE:
2345                 break;
2346 
2347         case SND_SOC_BIAS_STANDBY:
2348                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
2349                         if (nau8825->mclk_freq) {
2350                                 ret = clk_prepare_enable(nau8825->mclk);
2351                                 if (ret) {
2352                                         dev_err(nau8825->dev, "Unable to prepare component mclk\n");
2353                                         return ret;
2354                                 }
2355                         }
2356                         /* Setup codec configuration after resume */
2357                         nau8825_resume_setup(nau8825);
2358                 }
2359                 break;
2360 
2361         case SND_SOC_BIAS_OFF:
2362                 /* Reset the configuration of jack type for detection */
2363                 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
2364                 regmap_update_bits(nau8825->regmap, NAU8825_REG_MIC_BIAS,
2365                         NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
2366                 /* ground HPL/HPR, MICGRND1/2 */
2367                 regmap_update_bits(nau8825->regmap,
2368                         NAU8825_REG_HSD_CTRL, 0xf, 0xf);
2369                 /* Cancel and reset cross talk detection funciton */
2370                 nau8825_xtalk_cancel(nau8825);
2371                 /* Turn off all interruptions before system shutdown. Keep the
2372                  * interruption quiet before resume setup completes.
2373                  */
2374                 regmap_write(nau8825->regmap,
2375                         NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff);
2376                 /* Disable ADC needed for interruptions at audo mode */
2377                 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
2378                         NAU8825_ENABLE_ADC, 0);
2379                 if (nau8825->mclk_freq)
2380                         clk_disable_unprepare(nau8825->mclk);
2381                 break;
2382         }
2383         return 0;
2384 }
2385 
2386 static int __maybe_unused nau8825_suspend(struct snd_soc_component *component)
2387 {
2388         struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
2389 
2390         disable_irq(nau8825->irq);
2391         snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
2392         /* Power down codec power; don't suppoet button wakeup */
2393         snd_soc_dapm_disable_pin(nau8825->dapm, "SAR");
2394         snd_soc_dapm_disable_pin(nau8825->dapm, "MICBIAS");
2395         snd_soc_dapm_sync(nau8825->dapm);
2396         regcache_cache_only(nau8825->regmap, true);
2397         regcache_mark_dirty(nau8825->regmap);
2398 
2399         return 0;
2400 }
2401 
2402 static int __maybe_unused nau8825_resume(struct snd_soc_component *component)
2403 {
2404         struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
2405         int ret;
2406 
2407         regcache_cache_only(nau8825->regmap, false);
2408         regcache_sync(nau8825->regmap);
2409         nau8825->xtalk_protect = true;
2410         ret = nau8825_sema_acquire(nau8825, 0);
2411         if (ret)
2412                 nau8825->xtalk_protect = false;
2413         enable_irq(nau8825->irq);
2414 
2415         return 0;
2416 }
2417 
2418 static const struct snd_soc_component_driver nau8825_component_driver = {
2419         .probe                  = nau8825_component_probe,
2420         .remove                 = nau8825_component_remove,
2421         .set_sysclk             = nau8825_set_sysclk,
2422         .set_pll                = nau8825_set_pll,
2423         .set_bias_level         = nau8825_set_bias_level,
2424         .suspend                = nau8825_suspend,
2425         .resume                 = nau8825_resume,
2426         .controls               = nau8825_controls,
2427         .num_controls           = ARRAY_SIZE(nau8825_controls),
2428         .dapm_widgets           = nau8825_dapm_widgets,
2429         .num_dapm_widgets       = ARRAY_SIZE(nau8825_dapm_widgets),
2430         .dapm_routes            = nau8825_dapm_routes,
2431         .num_dapm_routes        = ARRAY_SIZE(nau8825_dapm_routes),
2432         .suspend_bias_off       = 1,
2433         .idle_bias_on           = 1,
2434         .use_pmdown_time        = 1,
2435         .endianness             = 1,
2436         .non_legacy_dai_naming  = 1,
2437 };
2438 
2439 static void nau8825_reset_chip(struct regmap *regmap)
2440 {
2441         regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2442         regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2443 }
2444 
2445 static void nau8825_print_device_properties(struct nau8825 *nau8825)
2446 {
2447         int i;
2448         struct device *dev = nau8825->dev;
2449 
2450         dev_dbg(dev, "jkdet-enable:         %d\n", nau8825->jkdet_enable);
2451         dev_dbg(dev, "jkdet-pull-enable:    %d\n", nau8825->jkdet_pull_enable);
2452         dev_dbg(dev, "jkdet-pull-up:        %d\n", nau8825->jkdet_pull_up);
2453         dev_dbg(dev, "jkdet-polarity:       %d\n", nau8825->jkdet_polarity);
2454         dev_dbg(dev, "micbias-voltage:      %d\n", nau8825->micbias_voltage);
2455         dev_dbg(dev, "vref-impedance:       %d\n", nau8825->vref_impedance);
2456 
2457         dev_dbg(dev, "sar-threshold-num:    %d\n", nau8825->sar_threshold_num);
2458         for (i = 0; i < nau8825->sar_threshold_num; i++)
2459                 dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
2460                                 nau8825->sar_threshold[i]);
2461 
2462         dev_dbg(dev, "sar-hysteresis:       %d\n", nau8825->sar_hysteresis);
2463         dev_dbg(dev, "sar-voltage:          %d\n", nau8825->sar_voltage);
2464         dev_dbg(dev, "sar-compare-time:     %d\n", nau8825->sar_compare_time);
2465         dev_dbg(dev, "sar-sampling-time:    %d\n", nau8825->sar_sampling_time);
2466         dev_dbg(dev, "short-key-debounce:   %d\n", nau8825->key_debounce);
2467         dev_dbg(dev, "jack-insert-debounce: %d\n",
2468                         nau8825->jack_insert_debounce);
2469         dev_dbg(dev, "jack-eject-debounce:  %d\n",
2470                         nau8825->jack_eject_debounce);
2471         dev_dbg(dev, "crosstalk-enable:     %d\n",
2472                         nau8825->xtalk_enable);
2473 }
2474 
2475 static int nau8825_read_device_properties(struct device *dev,
2476         struct nau8825 *nau8825) {
2477         int ret;
2478 
2479         nau8825->jkdet_enable = device_property_read_bool(dev,
2480                 "nuvoton,jkdet-enable");
2481         nau8825->jkdet_pull_enable = device_property_read_bool(dev,
2482                 "nuvoton,jkdet-pull-enable");
2483         nau8825->jkdet_pull_up = device_property_read_bool(dev,
2484                 "nuvoton,jkdet-pull-up");
2485         ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
2486                 &nau8825->jkdet_polarity);
2487         if (ret)
2488                 nau8825->jkdet_polarity = 1;
2489         ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
2490                 &nau8825->micbias_voltage);
2491         if (ret)
2492                 nau8825->micbias_voltage = 6;
2493         ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
2494                 &nau8825->vref_impedance);
2495         if (ret)
2496                 nau8825->vref_impedance = 2;
2497         ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
2498                 &nau8825->sar_threshold_num);
2499         if (ret)
2500                 nau8825->sar_threshold_num = 4;
2501         ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
2502                 nau8825->sar_threshold, nau8825->sar_threshold_num);
2503         if (ret) {
2504                 nau8825->sar_threshold[0] = 0x08;
2505                 nau8825->sar_threshold[1] = 0x12;
2506                 nau8825->sar_threshold[2] = 0x26;
2507                 nau8825->sar_threshold[3] = 0x73;
2508         }
2509         ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
2510                 &nau8825->sar_hysteresis);
2511         if (ret)
2512                 nau8825->sar_hysteresis = 0;
2513         ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
2514                 &nau8825->sar_voltage);
2515         if (ret)
2516                 nau8825->sar_voltage = 6;
2517         ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
2518                 &nau8825->sar_compare_time);
2519         if (ret)
2520                 nau8825->sar_compare_time = 1;
2521         ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
2522                 &nau8825->sar_sampling_time);
2523         if (ret)
2524                 nau8825->sar_sampling_time = 1;
2525         ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
2526                 &nau8825->key_debounce);
2527         if (ret)
2528                 nau8825->key_debounce = 3;
2529         ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
2530                 &nau8825->jack_insert_debounce);
2531         if (ret)
2532                 nau8825->jack_insert_debounce = 7;
2533         ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
2534                 &nau8825->jack_eject_debounce);
2535         if (ret)
2536                 nau8825->jack_eject_debounce = 0;
2537         nau8825->xtalk_enable = device_property_read_bool(dev,
2538                 "nuvoton,crosstalk-enable");
2539 
2540         nau8825->mclk = devm_clk_get(dev, "mclk");
2541         if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
2542                 return -EPROBE_DEFER;
2543         } else if (PTR_ERR(nau8825->mclk) == -ENOENT) {
2544                 /* The MCLK is managed externally or not used at all */
2545                 nau8825->mclk = NULL;
2546                 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
2547         } else if (IS_ERR(nau8825->mclk)) {
2548                 return -EINVAL;
2549         }
2550 
2551         return 0;
2552 }
2553 
2554 static int nau8825_setup_irq(struct nau8825 *nau8825)
2555 {
2556         int ret;
2557 
2558         ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
2559                 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2560                 "nau8825", nau8825);
2561 
2562         if (ret) {
2563                 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
2564                         nau8825->irq, ret);
2565                 return ret;
2566         }
2567 
2568         return 0;
2569 }
2570 
2571 static int nau8825_i2c_probe(struct i2c_client *i2c,
2572         const struct i2c_device_id *id)
2573 {
2574         struct device *dev = &i2c->dev;
2575         struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
2576         int ret, value;
2577 
2578         if (!nau8825) {
2579                 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
2580                 if (!nau8825)
2581                         return -ENOMEM;
2582                 ret = nau8825_read_device_properties(dev, nau8825);
2583                 if (ret)
2584                         return ret;
2585         }
2586 
2587         i2c_set_clientdata(i2c, nau8825);
2588 
2589         nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
2590         if (IS_ERR(nau8825->regmap))
2591                 return PTR_ERR(nau8825->regmap);
2592         nau8825->dev = dev;
2593         nau8825->irq = i2c->irq;
2594         /* Initiate parameters, semaphore and work queue which are needed in
2595          * cross talk suppression measurment function.
2596          */
2597         nau8825->xtalk_state = NAU8825_XTALK_DONE;
2598         nau8825->xtalk_protect = false;
2599         nau8825->xtalk_baktab_initialized = false;
2600         sema_init(&nau8825->xtalk_sem, 1);
2601         INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
2602 
2603         nau8825_print_device_properties(nau8825);
2604 
2605         nau8825_reset_chip(nau8825->regmap);
2606         ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
2607         if (ret < 0) {
2608                 dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
2609                         ret);
2610                 return ret;
2611         }
2612         if ((value & NAU8825_SOFTWARE_ID_MASK) !=
2613                         NAU8825_SOFTWARE_ID_NAU8825) {
2614                 dev_err(dev, "Not a NAU8825 chip\n");
2615                 return -ENODEV;
2616         }
2617 
2618         nau8825_init_regs(nau8825);
2619 
2620         if (i2c->irq)
2621                 nau8825_setup_irq(nau8825);
2622 
2623         return devm_snd_soc_register_component(&i2c->dev,
2624                 &nau8825_component_driver,
2625                 &nau8825_dai, 1);
2626 }
2627 
2628 static int nau8825_i2c_remove(struct i2c_client *client)
2629 {
2630         return 0;
2631 }
2632 
2633 static const struct i2c_device_id nau8825_i2c_ids[] = {
2634         { "nau8825", 0 },
2635         { }
2636 };
2637 MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids);
2638 
2639 #ifdef CONFIG_OF
2640 static const struct of_device_id nau8825_of_ids[] = {
2641         { .compatible = "nuvoton,nau8825", },
2642         {}
2643 };
2644 MODULE_DEVICE_TABLE(of, nau8825_of_ids);
2645 #endif
2646 
2647 #ifdef CONFIG_ACPI
2648 static const struct acpi_device_id nau8825_acpi_match[] = {
2649         { "10508825", 0 },
2650         {},
2651 };
2652 MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
2653 #endif
2654 
2655 static struct i2c_driver nau8825_driver = {
2656         .driver = {
2657                 .name = "nau8825",
2658                 .of_match_table = of_match_ptr(nau8825_of_ids),
2659                 .acpi_match_table = ACPI_PTR(nau8825_acpi_match),
2660         },
2661         .probe = nau8825_i2c_probe,
2662         .remove = nau8825_i2c_remove,
2663         .id_table = nau8825_i2c_ids,
2664 };
2665 module_i2c_driver(nau8825_driver);
2666 
2667 MODULE_DESCRIPTION("ASoC nau8825 driver");
2668 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
2669 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/sound/soc/codecs/nau8825.c

DEFINITIONS
